mirror of https://github.com/efabless/caravel.git
Adding cocotb evironment with tests and scripts to run
This commit is contained in:
M0stafaRady
parent
c9c7fc5533
commit
add4c5f6c8
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*.log
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sim_build
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sim
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__pycache__
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*.
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./wb_models/housekeepingWB/__pycache__
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*.xml
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*.yml
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*.hexe
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*.elf
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# SPDX-FileCopyrightText: 2020 Efabless Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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# SPDX-License-Identifier: Apache-2.0
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PWDD := $(shell pwd)
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BLOCKS := $(shell basename $(PWDD))
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# ---- Include Partitioned Makefiles ----
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CONFIG = caravel_user_project
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# TestName = temp_partial
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# export COCOTB_ANSI_OUTPUT=0 # disable color in termianl
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export GUI=1
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export COCOTB_REDUCED_LOG_FMT=1
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# Change this line if you want to use existing cocotb test modules:
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# export PYTHONPATH := $(DESIGNS)/verilog/rtl/<your design python tests>
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# export LIBPYTHON_LOC=$(cocotb-config --libpython)
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#export VERILOG_PATH = ../../../
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#export CARAVEL_PATH = ../../../../../caravel/verilog/
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# include $(MCW_ROOT)/verilog/dv/make/env.makefile
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# #export VERILOG_PATH = ../../../
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# include $(MCW_ROOT)/verilog/dv/make/var.makefile
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# include $(MCW_ROOT)/verilog/dv/make/cpu.makefile
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# include $(MCW_ROOT)/verilog/dv/make/sim.makefile
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TESTCASE=$(TestName)
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MODULE=caravel_tests
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$(info $$MODULE is [$(MODULE)])
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cocotb:
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rm -rf sim_build/
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mkdir sim_build/
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# change project_tb.v to match your testbench
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#RTL
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iverilog -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
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-DTESTNAME=\"$(TestName)\" -DTAG=\"$(RUNTAG)\" -DSIM=\"$(SIM)\" \
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-f$(VERILOG_PATH)/includes/includes.rtl.caravel \
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-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) -o sim_build/sim.vvp caravel_top.sv
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#GL
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# iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
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# -DTESTNAME=\"$(TestName)\" -DRUNTAG=\"$(RUNTAG)\" -DSIM=\"$(SIM)\" \
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# -f$(VERILOG_PATH)/includes/includes.gl.caravel \
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# -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) -o sim_build/sim.vvp caravel_top.sv
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#CVC
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# TESTCASE=$(TestName) MODULE=caravel_tests cvc64 +interp +acc+2 \
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# +loadvpi=$(shell cocotb-config --lib-name-path vpi cvc):vlog_startup_routines_bootstrap\
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# +change_port_type +maxerrors 1\
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# +define+SIM +define+FUNCTIONAL +define+GL +define+USE_POWER_PINS +define+UNIT_DELAY=#0 \
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# +define+TESTNAME=\"$(TestName)\" +define+RUNTAG=\"$(RUNTAG)\" +define+COCOTB_SIM=1\
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# -f $(VERILOG_PATH)/includes/includes.gl+sdf.caravel \
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# -f $(USER_PROJECT_VERILOG)/includes/includes.gl+sdf.$(CONFIG) -o sim_build/sim.vvp
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# verilator --vpi --public-flat-rw --prefix Vtop \
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# -LDFLAGS "-Wl,-rpath,$(cocotb-config --prefix)/cocotb/libs \
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# -L$(cocotb-config --prefix)/cocotb/libs \
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# -lcocotbvpi_verilator -lgpi -lcocotb -lgpilog -lcocotbutils" \
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# $(cocotb-config --share)/lib/verilator/verilator.cpp\
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# -y $(VERILOG_PATH)/includes/includes.rtl.caravel \
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# -y $(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) --cc -o sim_build/sim.vvp caravel_top.sv
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# change this line to choose the comma separated test cases and the name of your python test module
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TESTCASE=$(TestName) MODULE=caravel_tests vvp -M $$(cocotb-config --prefix)/cocotb/libs -m libcocotbvpi_icarus sim_build/sim.vvp
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! grep failure results.xml
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import random
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import cocotb
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from cocotb.clock import Clock
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from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
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import cocotb.log
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import cocotb.simulator
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from cocotb.handle import SimHandleBase
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from cocotb.handle import Force
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from cocotb_coverage.coverage import *
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from cocotb.binary import BinaryValue
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import enum
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from cocotb.handle import (
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ConstantObject,
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HierarchyArrayObject,
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HierarchyObject,
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ModifiableObject,
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NonHierarchyIndexableObject,
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SimHandle,
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)
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from itertools import groupby, product
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import common
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from common import GPIO_MODE
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from common import MASK_GPIO_CTRL
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from common import Macros
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def gpio_mode(gpios_values:list):
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gpios=[]
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for array in gpios_values:
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gpio_value = GPIO_MODE(array[1]).name
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for gpio in array[0]:
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gpios.append((gpio,gpio_value))
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cocotb.log.info(f'[caravel][gpio_mode] gpios {gpios}')
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return gpios
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Carvel_Coverage = coverage_section (
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CoverPoint("top.caravel.gpio", vname="gpios mode", xf = lambda gpio ,gpio_mode: (gpio,gpio_mode) ,
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bins = list(product(range(38),[e.name for e in GPIO_MODE])))
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)
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class Caravel_env:
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def __init__(self,dut:SimHandleBase):
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self.dut = dut
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self.clk = dut.clock_tb
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self.caravel_hdl = dut.uut
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self.hk_hdl = dut.uut.housekeeping
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"""start carvel by insert power then reset"""
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async def start_up(self):
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await self.power_up()
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await self.reset()
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await self.disable_bins()
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await self.disable_csb()
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common.fill_macros(self.dut.macros) # get macros value
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async def disable_bins(self):
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for i in range(38):
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common.drive_hdl(self.dut._id(f"bin{i}_en",False),(0,0),0)
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"""setup the vdd and vcc power bins"""
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async def power_up(self):
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cocotb.log.info(f' [caravel] start powering up')
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self.set_vdd(0)
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self.set_vcc(0)
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await ClockCycles(self.clk, 10)
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cocotb.log.info(f' [caravel] power up -> connect vdd' )
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self.set_vdd(1)
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# await ClockCycles(self.clk, 10)
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cocotb.log.info(f' [caravel] power up -> connect vcc' )
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self.set_vcc(1)
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await ClockCycles(self.clk, 10)
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""""reset caravel"""
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async def reset(self):
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cocotb.log.info(f' [caravel] start resetting')
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self.dut.resetb_tb.value = 0
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await ClockCycles(self.clk, 20)
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self.dut.resetb_tb.value = 1
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await ClockCycles(self.clk, 1)
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cocotb.log.info(f' [caravel] finish resetting')
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def set_vdd(self,value:bool):
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self.dut.vddio_tb.value = value
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self.dut.vssio_tb.value = 0
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self.dut.vddio_2_tb.value = value
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self.dut.vssio_2_tb.value = 0
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self.dut.vdda_tb.value = value
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self.dut.vssa_tb.value = 0
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self.dut.vdda1_tb.value = value
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self.dut.vssa1_tb.value = 0
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self.dut.vdda1_2_tb.value = value
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self.dut.vssa1_2_tb.value = 0
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self.dut.vdda2_tb.value = value
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self.dut.vssa2_tb.value = 0
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def set_vcc(self , value:bool):
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self.dut.vccd_tb.value = value
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self.dut.vssd_tb.value = 0
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self.dut.vccd1_tb.value = value
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self.dut.vssd1_tb.value = 0
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self.dut.vccd2_tb.value = value
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self.dut.vssd2_tb.value = 0
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"""drive csb signal bin E8 mprj[3]"""
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async def drive_csb(self,bit):
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self.drive_gpio_in((3,3),bit)
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self.drive_gpio_in((2,2),0)
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await ClockCycles(self.clk, 1)
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"""set the spi vsb signal high to disable housekeeping spi transmission bin E8 mprj[3]"""
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async def disable_csb(self ):
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cocotb.log.info(f' [caravel] disable housekeeping spi transmission')
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await self.drive_csb(1)
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"""set the spi vsb signal high impedance """
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async def release_csb(self ):
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cocotb.log.info(f' [caravel] release housekeeping spi transmission')
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await self.drive_csb('z')
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"""set the spi vsb signal low to enable housekeeping spi transmission bin E8 mprj[3]"""
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async def enable_csb(self ):
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cocotb.log.info(f' [caravel] enable housekeeping spi transmission')
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await self.drive_csb(0)
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"""return the value of mprj in bits used tp monitor the output gpios value"""
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def monitor_gpio(self,bits:tuple):
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mprj = self.dut.mprj_io_tb.value
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size =mprj.n_bits -1 #size of bins array
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mprj_out= self.dut.mprj_io_tb.value[size - bits[0]:size - bits[1]]
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if(mprj_out.is_resolvable):
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cocotb.log.debug(f' [caravel] Monitor : mprj[{bits[0]}:{bits[1]}] = {hex(mprj_out)}')
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else:
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cocotb.log.debug(f' [caravel] Monitor : mprj[{bits[0]}:{bits[1]}] = {mprj_out}')
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return mprj_out
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"""return the value of management gpio"""
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def monitor_mgmt_gpio(self):
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data = self.dut.gpio_tb.value
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cocotb.log.debug(f' [caravel] Monitor mgmt gpio = {data}')
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return data
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"""change the configration of the gpios by overwrite their defaults value then reset
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need to take at least 1 cycle for reset """
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### dont use back door accessing
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async def configure_gpio_defaults(self,gpios_values: list):
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gpio_defaults = self.caravel_hdl.gpio_defaults.value
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cocotb.log.info(f' [caravel] start cofigure gpio gpios ')
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size = gpio_defaults.n_bits -1 #number of bins in gpio_defaults
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# list example [[(gpios),value],[(gpios),value],[(gpios),value]]
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for array in gpios_values:
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gpio_value = array[1]
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for gpio in array[0]:
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self.cov_configure_gpios(gpio,gpio_value.name)
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gpio_defaults[size - (gpio*13 + 12): size -gpio*13] = gpio_value.value
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#cocotb.log.info(f' [caravel] gpio_defaults[{size - (gpio*13 + 12)}:{size -gpio*13}] = {gpio_value.value} ')
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self.caravel_hdl.gpio_defaults.value = gpio_defaults
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#reset
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self.caravel_hdl.gpio_resetn_1_shifted.value = 0
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self.caravel_hdl.gpio_resetn_2_shifted.value = 0
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await ClockCycles(self.clk, 1)
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self.caravel_hdl.gpio_resetn_1_shifted.value = 1
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self.caravel_hdl.gpio_resetn_2_shifted.value = 1
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cocotb.log.info(f' [caravel] finish configuring gpios, the curret gpios value: ')
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self.print_gpios_ctrl_val()
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"""change the configration of the gpios by overwrite the register value
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in control registers and housekeeping regs, don't consume simulation cycles"""
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### dont use back door accessing
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def configure_gpios_regs(self,gpios_values: list):
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cocotb.log.info(f' [caravel] start cofigure gpio gpios ')
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control_modules = self.control_blocks_paths()
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# list example [[(gpios),value],[(gpios),value],[(gpios),value]]
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for array in gpios_values:
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gpio_value = array[1]
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for gpio in array[0]:
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self.cov_configure_gpios(gpio,gpio_value.name)
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self.gpio_control_reg_write(control_modules[gpio],gpio_value.value) # for control blocks regs
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self.caravel_hdl.housekeeping.gpio_configure[gpio].value = gpio_value.value # for house keeping regs
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cocotb.log.info(f' [caravel] finish configuring gpios, the curret gpios value: ')
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self.print_gpios_ctrl_val()
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self.print_gpios_HW_val()
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"""dummy function for coverage sampling"""
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@Carvel_Coverage
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def cov_configure_gpios(self,gpio,gpio_mode):
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cocotb.log.debug(f' [caravel] gpio [{gpio}] = {gpio_mode} ')
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pass
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def print_gpios_default_val(self,print=1):
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gpio_defaults = self.caravel_hdl.gpio_defaults.value
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size = gpio_defaults.n_bits -1 #number of bins in gpio_defaults
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gpios = []
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for gpio in range(Macros['MPRJ_IO_PADS']):
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gpio_value = gpio_defaults[size - (gpio*13 + 12): size -gpio*13]
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gpio_enum = GPIO_MODE(gpio_value.integer)
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gpios.append((gpio,gpio_enum))
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group_bins = groupby(gpios,key=lambda x: x[1])
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for key,value in group_bins:
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gpios=[]
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for gpio in list(value):
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gpios.append(gpio[0])
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if (print):
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cocotb.log.info(f' [caravel] gpios[{gpios}] are {key} ')
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return gpios
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"""print the values return in the gpio of control block mode in GPIO Mode format"""
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def print_gpios_ctrl_val(self, print=1):
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control_modules = self.control_blocks_paths()
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gpios = []
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for i , gpio in enumerate(control_modules):
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gpios.append((i,self.gpio_control_reg_read(gpio)))
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group_bins = groupby(gpios,key=lambda x: x[1])
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for key,value in group_bins:
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gpios=[]
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for gpio in list(value):
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gpios.append(gpio[0])
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if (print):
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cocotb.log.info(f' [caravel] gpios[{gpios}] are {key} ')
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return gpios
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def _check_gpio_ctrl_eq_HW(self):
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assert self.print_gpios_ctrl_val(1) == self.print_gpios_HW_val(1), f'there is an issue while configuration the control block register value isn\'t the same as the house keeping gpio register'
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"""print the values return in the gpio of housekeeping block mode in GPIO Mode format"""
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def print_gpios_HW_val(self,print=1):
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gpios = []
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for pin in range(Macros['MPRJ_IO_PADS']):
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gpios.append((pin,GPIO_MODE(self.caravel_hdl.housekeeping.gpio_configure[pin].value)))
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group_bins = groupby(gpios,key=lambda x: x[1])
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for key,value in group_bins:
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gpios=[]
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for gpio in list(value):
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gpios.append(gpio[0])
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if (print):
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cocotb.log.info(f' [caravel] gpios[{gpios}] are {key} ')
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return gpios
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"""return the paths of the control blocks"""
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def control_blocks_paths(self)-> list:
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car = self.caravel_hdl
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control_modules =[car._id("gpio_control_bidir_1[0]",False),car._id("gpio_control_bidir_1[1]",False)]
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#add gpio_control_in_1a (GPIO 2 to 7)
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for i in range(6):
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control_modules.append(car._id(f'gpio_control_in_1a[{i}]',False))
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#add gpio_control_in_1 (GPIO 8 to 18)
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for i in range(Macros['MPRJ_IO_PADS_1']-9+1):
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control_modules.append(car._id(f'gpio_control_in_1[{i}]',False))
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#add gpio_control_in_2 (GPIO 19 to 34)
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for i in range(Macros['MPRJ_IO_PADS_2']-4+1):
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control_modules.append(car._id(f'gpio_control_in_2[{i}]',False))
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# Last three GPIOs (spi_sdo, flash_io2, and flash_io3) gpio_control_bidir_2
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for i in range(3):
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control_modules.append(car._id(f'gpio_control_bidir_2[{i}]',False))
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return control_modules
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"""read the control register and return a GPIO Mode it takes the path to the control reg"""
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def gpio_control_reg_read(self,path:SimHandleBase) -> GPIO_MODE:
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gpio_mgmt_en = path.mgmt_ena.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_MGMT_EN.value
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gpio_out_dis = path.gpio_outenb.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_OUT_DIS.value
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gpio_holdover = path.gpio_holdover.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_OVERRIDE.value
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gpio_in_dis = path.gpio_inenb.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_INP_DIS.value
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gpio_mode_sel = path.gpio_ib_mode_sel.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_MOD_SEL.value
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gpio_anlg_en = path.gpio_ana_en.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_ANLG_EN.value
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gpio_anlg_sel = path.gpio_ana_sel.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_ANLG_SEL.value
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gpio_anlg_pol = path.gpio_ana_pol.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_ANLG_POL.value
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gpio_slow_sel = path.gpio_slow_sel.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_SLOW.value
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gpio_vtrip_sel = path.gpio_vtrip_sel.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_TRIP.value
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gpio_dgtl_mode = path.gpio_dm.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_DGTL_MODE.value
|
||||
control_reg = (gpio_mgmt_en | gpio_out_dis | gpio_holdover| gpio_in_dis | gpio_mode_sel | gpio_anlg_en
|
||||
|gpio_anlg_sel|gpio_anlg_pol|gpio_slow_sel|gpio_vtrip_sel|gpio_dgtl_mode)
|
||||
return(GPIO_MODE(control_reg))
|
||||
|
||||
"""read the control register and return a GPIO Mode it takes the path to the control reg"""
|
||||
def gpio_control_reg_write(self,path:SimHandleBase,data) :
|
||||
bits =common.int_to_bin_list(data,14)
|
||||
path.mgmt_ena.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_MGMT_EN.value]
|
||||
path.gpio_outenb.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_OUT_DIS.value]
|
||||
path.gpio_holdover.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_OVERRIDE.value]
|
||||
path.gpio_inenb.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_INP_DIS.value]
|
||||
path.gpio_ib_mode_sel.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_MOD_SEL.value]
|
||||
path.gpio_ana_en.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_ANLG_EN.value]
|
||||
path.gpio_ana_sel.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_ANLG_SEL.value]
|
||||
path.gpio_ana_pol.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_ANLG_POL.value]
|
||||
path.gpio_slow_sel.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_SLOW.value]
|
||||
path.gpio_vtrip_sel.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_TRIP.value]
|
||||
gpio_dm =bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_DGTL_MODE.value:MASK_GPIO_CTRL.MASK_GPIO_CTRL_DGTL_MODE.value+3]
|
||||
gpio_dm =sum(d * 2**i for i, d in enumerate(gpio_dm)) # convert list to binary int
|
||||
path.gpio_dm.value = gpio_dm
|
||||
|
||||
"""drive the value of mprj bits with spicific data from input pad at the top"""
|
||||
def release_gpio(self):
|
||||
io = self.caravel_hdl.padframe.mprj_pads.io
|
||||
mprj , n_bits = common.signal_valueZ_size(io)
|
||||
io.value = mprj
|
||||
cocotb.log.info(f' [caravel] drive_gpio_in pad mprj with {mprj}')
|
||||
|
||||
"""drive the value of mprj bits with spicific data from input pad at the top"""
|
||||
def drive_gpio_in(self,bits,data):
|
||||
# io = self.caravel_hdl.padframe.mprj_pads.io
|
||||
# mprj , n_bits = common.signal_value_size(io)
|
||||
# cocotb.log.debug(f' [caravel] before mprj with {mprj} and data = {data} bit [{n_bits-1-bits[0]}]:[{n_bits-1-bits[1]}]')
|
||||
# mprj[n_bits-1-bits[0]:n_bits-1-bits[1]] = data
|
||||
# io.value = mprj
|
||||
# cocotb.log.info(f' [caravel] drive_gpio_in pad mprj with {mprj}')
|
||||
data_bits = []
|
||||
is_list = isinstance(bits, (list,tuple))
|
||||
if is_list :
|
||||
cocotb.log.info(f'[caravel] [drive_gpio_in] start bits[1] = {bits[1]} bits[0]= {bits[0]}')
|
||||
data_bits = BinaryValue(value = data, n_bits =bits[0]-bits[1]+1 ,bigEndian=(bits[0]<bits[1]))
|
||||
for i,bits2 in enumerate(range(bits[1],bits[0]+1)):
|
||||
self.dut._id(f"bin{bits2}",False).value = data_bits[i]
|
||||
self.dut._id(f"bin{bits2}_en",False).value = 1
|
||||
cocotb.log.info(f'[caravel] [drive_gpio_in] drive bin{bits2} with {data_bits[i]} and bin{bits2}_en with 1')
|
||||
else:
|
||||
self.dut._id(f'bin{bits}',False).value = data
|
||||
self.dut._id(f'bin{bits}_en',False).value = 1
|
||||
cocotb.log.info(f'[caravel] [drive_gpio_in] drive bin{bits} with {data} and bin{bits}_en with 1')
|
||||
|
||||
"""drive the value of gpio management"""
|
||||
def drive_mgmt_gpio(self,data):
|
||||
mgmt_io = self.dut.gpio_tb
|
||||
mgmt_io.value = data
|
||||
cocotb.log.info(f' [caravel] drive_mgmt_gpio through management area mprj with {data}')
|
||||
|
||||
"""update the value of mprj bits with spicific data then after certain number of cycle drive z to free the signal"""
|
||||
async def drive_gpio_in_with_cycles(self,bits,data,num_cycles):
|
||||
self.drive_gpio_in(bits,data)
|
||||
cocotb.log.info(f' [caravel] wait {num_cycles} cycles')
|
||||
await cocotb.start(self.wait_then_undrive(bits,num_cycles))
|
||||
cocotb.log.info(f' [caravel] finish drive_gpio_with_in_cycles ')
|
||||
|
||||
"""drive the value of mprj bits with spicific data from management area then after certain number of cycle drive z to free the signal"""
|
||||
async def drive_mgmt_gpio_with_cycles(self,bits,data,num_cycles):
|
||||
self.drive_mgmt_gpio(bits,data)
|
||||
cocotb.log.info(f' [caravel] wait {num_cycles} cycles')
|
||||
await cocotb.start(self.wait_then_undrive(bits,num_cycles))
|
||||
cocotb.log.info(f' [caravel] finish drive_gpio_with_in_cycles ')
|
||||
|
||||
async def wait_then_undrive(self,bits,num_cycles):
|
||||
await ClockCycles(self.clk, num_cycles)
|
||||
n_bits = bits[0]-bits[1]+1
|
||||
self.drive_gpio_in(bits, (n_bits)* 'z')
|
||||
cocotb.log.info(f' [caravel] finish wait_then_drive ')
|
||||
|
||||
async def hk_write_byte(self, data):
|
||||
self.path = self.dut.mprj_io_tb
|
||||
data_bit = BinaryValue(value = data , n_bits = 8,bigEndian=False)
|
||||
for i in range(7,-1,-1):
|
||||
await FallingEdge(self.clk)
|
||||
#common.drive_hdl(self.path,[(4,4),(2,2)],[0,int(data_bit[i])]) # 2 = SDI 4 = SCK
|
||||
self.drive_gpio_in((2,2),int(data_bit[i]))
|
||||
self.drive_gpio_in((4,4),0)
|
||||
|
||||
await RisingEdge(self.clk)
|
||||
self.drive_gpio_in((4,4),1)
|
||||
await FallingEdge(self.clk)
|
||||
|
||||
""" read byte using housekeeping spi
|
||||
when writing to SCK we can't use mprj[4] as there is a limitation in cocotb for accessing pack array #2587
|
||||
so use back door access to write the clock then read the output from the SDO mprj[1] value"""
|
||||
async def hk_read_byte(self,last_read= False):
|
||||
read_data =''
|
||||
for i in range(8,0,-1):
|
||||
self.drive_gpio_in((4,4),1)# SCK
|
||||
await FallingEdge(self.clk)
|
||||
self.drive_gpio_in((4,4),0)# SCK
|
||||
await RisingEdge(self.clk)
|
||||
read_data= f'{read_data}{self.dut.mprj_io_tb.value[37-1]}'
|
||||
await FallingEdge(self.clk)
|
||||
self.drive_gpio_in((4,4),0) # SCK
|
||||
# if (last_read):
|
||||
# common.drive_hdl(self.dut.bin4_en,(0,0),'z') #4 = SCK
|
||||
# common.drive_hdl(self.path,[(1,1)],'z')
|
||||
|
||||
return int(read_data,2)
|
||||
|
||||
"""write to the house keeping registers by back door no need for commands and waiting for the data to show on mprj"""
|
||||
async def hk_write_backdoor(self,addr, data):
|
||||
await RisingEdge(self.dut.wb_clk_i)
|
||||
self.hk_hdl.wb_stb_i.value = 1
|
||||
self.hk_hdl.wb_cyc_i.value = 1
|
||||
self.hk_hdl.wb_sel_i.value = 0xF
|
||||
self.hk_hdl.wb_we_i.value = 1
|
||||
self.hk_hdl.wb_adr_i.value = addr
|
||||
self.hk_hdl.wb_dat_i.value = data
|
||||
cocotb.log.info(f'Monitor: Start Writing to {hex(addr)} -> {data}')
|
||||
await FallingEdge(self.dut.wb_ack_o) # wait for acknowledge
|
||||
self.hk_hdl.wb_stb_i.value = 0
|
||||
self.hk_hdl.wb_cyc_i.value = 0
|
||||
cocotb.log.info(f'Monitor: End writing {hex(addr)} -> {data}')
|
||||
|
||||
|
||||
"""read from the house keeping registers by back door no need for commands and waiting for the data to show on mprj"""
|
||||
async def hk_read_backdoor(self,addr):
|
||||
await RisingEdge(self.clk)
|
||||
self.hk_hdl.wb_stb_i.value = 1
|
||||
self.hk_hdl.wb_cyc_i.value = 1
|
||||
self.hk_hdl.wb_sel_i.value = 0
|
||||
self.hk_hdl.wb_we_i.value = 0
|
||||
self.hk_hdl.wb_adr_i.value = addr
|
||||
cocotb.log.info(f' [housekeeping] Monitor: Start reading from {hex(addr)}')
|
||||
await FallingEdge(self.hk_hdl.wb_ack_o)
|
||||
self.hk_hdl.wb_stb_i.value = 0
|
||||
self.hk_hdl.wb_cyc_i.value = 0
|
||||
cocotb.log.info(f' [housekeeping] Monitor: read from {hex(addr)} value {(self.hk_hdl.wb_dat_o.value)}')
|
||||
return self.hk_hdl.wb_dat_o.value
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,200 @@
|
|||
from cgitb import handler
|
||||
import random
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
|
||||
import cocotb.log
|
||||
import cocotb.simulator
|
||||
from cocotb_coverage.coverage import *
|
||||
from cocotb.binary import BinaryValue
|
||||
import caravel
|
||||
from logic_analyzer import LA
|
||||
from caravel import GPIO_MODE, Caravel_env
|
||||
from wb_models.housekeepingWB.housekeepingWB import HK_whiteBox
|
||||
import common
|
||||
import logging
|
||||
from cpu import RiskV
|
||||
from cocotb.log import SimTimeContextFilter
|
||||
from cocotb.log import SimLogFormatter
|
||||
from defsParser import Regs
|
||||
from tests.common_functions.Timeout import Timeout
|
||||
from cocotb.result import TestSuccess
|
||||
import inspect
|
||||
import os
|
||||
# tests
|
||||
from tests.bitbang.bitbang_tests import *
|
||||
from tests.bitbang.bitbang_tests_cpu import *
|
||||
from tests.housekeeping.housekeeping_regs.housekeeping_regs_tests import *
|
||||
from tests.temp_partial_test.partial import *
|
||||
from tests.hello_world.helloWorld import *
|
||||
from tests.cpu.cpu_stress import *
|
||||
from tests.mem.mem_stress import *
|
||||
from tests.irq.IRQ_external import *
|
||||
from tests.irq.IRQ_timer import *
|
||||
from tests.irq.IRQ_uart import *
|
||||
from tests.gpio.gpio_all_o import *
|
||||
from tests.mgmt_gpio.mgmt_gpio import *
|
||||
from tests.timer.timer import *
|
||||
from tests.uart.uart import *
|
||||
|
||||
|
||||
|
||||
|
||||
# archive tests
|
||||
@cocotb.test()
|
||||
async def cpu_drive(dut):
|
||||
TestName = inspect.stack()[0][3]
|
||||
if not os.path.exists(f'sim/{TestName}'):
|
||||
os.mkdir(f'sim/{TestName}') # create test folder
|
||||
cocotb.log.setLevel(logging.INFO)
|
||||
handler = logging.FileHandler(f"sim/{TestName}/{TestName}.log",mode='w')
|
||||
handler.addFilter(SimTimeContextFilter())
|
||||
handler.setFormatter(SimLogFormatter())
|
||||
cocotb.log.addHandler(handler)
|
||||
caravelEnv = caravel.Caravel_env(dut)
|
||||
Timeout(caravelEnv.clk,1000000,0.1)
|
||||
la = LA(dut)
|
||||
clock = Clock(caravelEnv.clk, 12.5, units="ns") # Create a 10ns period clock on port clk
|
||||
cpu = RiskV(dut)
|
||||
cpu.cpu_force_reset()
|
||||
|
||||
cocotb.start_soon(clock.start()) # Start the clock
|
||||
|
||||
await caravelEnv.start_up()
|
||||
hk = HK_whiteBox(dut)
|
||||
|
||||
reg = Regs()
|
||||
time_out_count =0
|
||||
|
||||
await ClockCycles(caravelEnv.clk, 100)
|
||||
address = reg.get_addr('reg_wb_enable')
|
||||
await cpu.drive_data2address(address,1)
|
||||
address = reg.get_addr('reg_debug_2')
|
||||
await cpu.drive_data2address(address,0xdFF0)
|
||||
await ClockCycles(caravelEnv.clk, 10)
|
||||
cpu.cpu_release_reset()
|
||||
await ClockCycles(caravelEnv.clk, 10)
|
||||
|
||||
raise TestSuccess(f" TEST {TestName} passed")
|
||||
|
||||
while True:
|
||||
await ClockCycles(caravelEnv.clk, 1)
|
||||
if (cpu.read_debug_reg1() == 0xFFF0):
|
||||
break
|
||||
cocotb.log.info(f"[TEST][cpu_drive] debug reg1 = 0xFFF0")
|
||||
await ClockCycles(caravelEnv.clk, 10)
|
||||
address = reg.get_addr('reg_debug_2')
|
||||
await cpu.drive_data2address(address,0xdFF0)
|
||||
await ClockCycles(caravelEnv.clk, 50)
|
||||
# address = reg.get_addr('reg_mprj_io_0')
|
||||
# await cpu.drive_data2address(address,0x0c03)
|
||||
cocotb.log.info(f"[TEST][cpu_drive] wait debug reg1 = 0xddd0")
|
||||
while True:
|
||||
await ClockCycles(caravelEnv.clk, 1)
|
||||
if (cpu.read_debug_reg1() == 0xddd0):
|
||||
break
|
||||
cocotb.log.info(f"[TEST][cpu_drive] debug reg1 = 0xddd0")
|
||||
|
||||
await ClockCycles(caravelEnv.clk, 10)
|
||||
|
||||
caravelEnv.print_gpios_HW_val()
|
||||
coverage_db.export_to_yaml(filename="coverage.yalm")
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
async def spi_drive(dut):
|
||||
cocotb.log.setLevel(logging.INFO)
|
||||
handler = logging.FileHandler(f"test.log",mode='w')
|
||||
handler.addFilter(SimTimeContextFilter())
|
||||
handler.setFormatter(SimLogFormatter())
|
||||
cocotb.log.addHandler(handler)
|
||||
caravelEnv = caravel.Caravel_env(dut)
|
||||
|
||||
|
||||
la = LA(dut)
|
||||
clock = Clock(caravelEnv.clk, 12.5, units="ns") # Create a 10ns period clock on port clk
|
||||
cocotb.start_soon(clock.start()) # Start the clock
|
||||
await caravelEnv.start_up()
|
||||
hk = HK_whiteBox(dut,True)
|
||||
|
||||
caravelEnv.enable_csb()
|
||||
await ClockCycles(caravelEnv.clk,1)
|
||||
# caravelEnv.configure_gpios_regs([[tuple(range(0,6)),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT]])
|
||||
await ClockCycles(caravelEnv.clk,1)
|
||||
await caravelEnv.hk_write_byte(0x40) # read command
|
||||
# await caravelEnv.hk_write_byte(0x80) # command write
|
||||
await caravelEnv.hk_write_byte(0x0) # address
|
||||
# await caravelEnv.hk_write_byte(0x03) # data
|
||||
# await caravelEnv.hk_write_byte(0xaa) # data
|
||||
# await caravelEnv.hk_write_byte(0xaa) # data
|
||||
# await caravelEnv.hk_write_byte(0xaa) # data
|
||||
# await caravelEnv.hk_write_byte(0xaa) # data
|
||||
# await caravelEnv.hk_write_byte(0xaa) # data
|
||||
# await caravelEnv.hk_write_byte(0xaa) # data
|
||||
# await caravelEnv.hk_write_byte(0xaa) # data
|
||||
# await caravelEnv.hk_write_byte(0xaa) # data
|
||||
# await caravelEnv.hk_write_byte(0xaa) # data
|
||||
# await caravelEnv.hk_write_byte(0xaa) # data
|
||||
# await caravelEnv.hk_write_byte(0xaa) # data
|
||||
# await caravelEnv.hk_write_byte(0xaa) # data
|
||||
# await caravelEnv.hk_write_byte(0xaa) # data
|
||||
# await caravelEnv.hk_write_byte(0xaa) # data
|
||||
# await caravelEnv.hk_write_byte(0xaa) # data
|
||||
|
||||
read_data = await caravelEnv.hk_read_byte() # read value
|
||||
print(read_data)
|
||||
read_data = await caravelEnv.hk_read_byte() # read value
|
||||
print(read_data)
|
||||
read_data = await caravelEnv.hk_read_byte() # read value
|
||||
print(read_data)
|
||||
read_data = await caravelEnv.hk_read_byte() # read value
|
||||
print(read_data)
|
||||
read_data = await caravelEnv.hk_read_byte() # read value
|
||||
print(read_data)
|
||||
read_data = await caravelEnv.hk_read_byte() # read value
|
||||
print(read_data)
|
||||
read_data = await caravelEnv.hk_read_byte() # read value
|
||||
print(read_data)
|
||||
read_data = await caravelEnv.hk_read_byte(True) # read value
|
||||
caravelEnv.disable_csb()
|
||||
await ClockCycles(caravelEnv.clk,1)
|
||||
caravelEnv.enable_csb()
|
||||
await ClockCycles(caravelEnv.clk,1)
|
||||
# caravelEnv.configure_gpios_regs([[tuple(range(0,6)),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT]])
|
||||
await ClockCycles(caravelEnv.clk,1)
|
||||
await caravelEnv.hk_write_byte(0x40) # read command
|
||||
# await caravelEnv.hk_write_byte(0x80) # command write
|
||||
await caravelEnv.hk_write_byte(0x8) # address
|
||||
# await caravelEnv.hk_write_byte(0x03) # data
|
||||
# await caravelEnv.hk_write_byte(0xaa) # data
|
||||
# await caravelEnv.hk_write_byte(0xaa) # data
|
||||
# await caravelEnv.hk_write_byte(0xaa) # data
|
||||
# await caravelEnv.hk_write_byte(0xaa) # data
|
||||
# await caravelEnv.hk_write_byte(0xaa) # data
|
||||
# await caravelEnv.hk_write_byte(0xaa) # data
|
||||
# await caravelEnv.hk_write_byte(0xaa) # data
|
||||
# await caravelEnv.hk_write_byte(0xaa) # data
|
||||
# await caravelEnv.hk_write_byte(0xaa) # data
|
||||
# await caravelEnv.hk_write_byte(0xaa) # data
|
||||
# await caravelEnv.hk_write_byte(0xaa) # data
|
||||
# await caravelEnv.hk_write_byte(0xaa) # data
|
||||
# await caravelEnv.hk_write_byte(0xaa) # data
|
||||
# await caravelEnv.hk_write_byte(0xaa) # data
|
||||
# await caravelEnv.hk_write_byte(0xaa) # data
|
||||
|
||||
read_data = await caravelEnv.hk_read_byte() # read value
|
||||
read_data = await caravelEnv.hk_read_byte() # read value
|
||||
read_data = await caravelEnv.hk_read_byte() # read value
|
||||
read_data = await caravelEnv.hk_read_byte() # read value
|
||||
read_data = await caravelEnv.hk_read_byte() # read value
|
||||
read_data = await caravelEnv.hk_read_byte() # read value
|
||||
read_data = await caravelEnv.hk_read_byte() # read value
|
||||
read_data = await caravelEnv.hk_read_byte() # read value
|
||||
|
||||
# caravelEnv.drive_gpio_in([5,5],1)
|
||||
await ClockCycles(caravelEnv.clk,40)
|
||||
coverage_db.export_to_yaml(filename="coverage.yml")
|
||||
coverage_db.export_to_xml(filename="coverage.xml")
|
||||
return
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,275 @@
|
|||
`ifdef VCS
|
||||
`ifndef GL
|
||||
`include "caravel_mgmt_soc_litex/verilog/includes/rtl_caravel_vcs.v"
|
||||
`else
|
||||
`include "caravel_mgmt_soc_litex/verilog/includes/gl_caravel_vcs.v"
|
||||
`endif
|
||||
//`include "verilog/includes/user_project_vcs.v"
|
||||
`endif
|
||||
module caravel_top ;
|
||||
|
||||
// parameter FILENAME = {"hex_files/",`TESTNAME,".hex"};
|
||||
parameter FILENAME={"hex_files/",`TESTNAME,".hex"};
|
||||
initial begin
|
||||
`ifdef VCS
|
||||
`ifdef ENABLE_SDF
|
||||
$vcdplusfile({`MAIN_PATH,"/sim/",`TAG,"/",`FTESTNAME,"/",`TESTNAME , `SDF_POSTFIX, ".vpd"});
|
||||
`else
|
||||
$vcdplusfile({`MAIN_PATH,"/sim/",`TAG,"/",`FTESTNAME,"/",`TESTNAME ,".vpd"});
|
||||
`endif
|
||||
$vcdpluson();
|
||||
`else
|
||||
$dumpfile ({"sim/",`TAG,"/",`SIM,"-",`TESTNAME,"/",`SIM,"-",`TESTNAME,".vcd"});
|
||||
$dumpvars (0, caravel_top);
|
||||
`endif
|
||||
end
|
||||
|
||||
wire vddio_tb; // Common 3.3V padframe/ESD power
|
||||
wire vddio_2_tb; // Common 3.3V padframe/ESD power
|
||||
wire vssio_tb; // Common padframe/ESD ground
|
||||
wire vssio_2_tb; // Common padframe/ESD ground
|
||||
wire vdda_tb; // Management 3.3V power
|
||||
wire vssa_tb; // Common analog ground
|
||||
wire vccd_tb; // Management/Common 1.8V power
|
||||
wire vssd_tb; // Common digital ground
|
||||
wire vdda1_tb; // User area 1 3.3V power
|
||||
wire vdda1_2_tb; // User area 1 3.3V power
|
||||
wire vdda2_tb; // User area 2 3.3V power
|
||||
wire vssa1_tb; // User area 1 analog ground
|
||||
wire vssa1_2_tb; // User area 1 analog ground
|
||||
wire vssa2_tb; // User area 2 analog ground
|
||||
wire vccd1_tb; // User area 1 1.8V power
|
||||
wire vccd2_tb; // User area 2 1.8V power
|
||||
wire vssd1_tb; // User area 1 digital ground
|
||||
wire vssd2_tb; // User area 2 digital ground
|
||||
|
||||
wire gpio_tb; // Used for external LDO control
|
||||
wire [38-1:0] mprj_io_tb;
|
||||
reg clock_tb; // CMOS core clock input; not a crystal
|
||||
wire resetb_tb; // Reset input (sense inverted)
|
||||
|
||||
// Note that only two flash data pins are dedicated to the
|
||||
// management SoC wrapper. The management SoC exports the
|
||||
// quad SPI mode status to make use of the top two mprj_io
|
||||
// pins for io2 and io3.
|
||||
|
||||
wire flash_csb_tb;
|
||||
wire flash_clk_tb;
|
||||
wire flash_io0_tb;
|
||||
wire flash_io1_tb;
|
||||
|
||||
|
||||
|
||||
caravel uut (
|
||||
.vddio (vddio_tb),
|
||||
.vddio_2 (vddio_2_tb),
|
||||
.vssio (vssio_tb),
|
||||
.vssio_2 (vssio_2_tb),
|
||||
.vdda (vdda_tb),
|
||||
.vssa (vssa_tb),
|
||||
.vccd (vccd_tb),
|
||||
.vssd (vssd_tb),
|
||||
.vdda1 (vdda1_tb),
|
||||
.vdda1_2 (vdda1_2_tb),
|
||||
.vdda2 (vdda2_tb),
|
||||
.vssa1 (vssa1_tb),
|
||||
.vssa1_2 (vssa1_2_tb),
|
||||
.vssa2 (vssa2_tb),
|
||||
.vccd1 (vccd1_tb),
|
||||
.vccd2 (vccd2_tb),
|
||||
.vssd1 (vssd1_tb),
|
||||
.vssd2 (vssd2_tb),
|
||||
.clock (clock_tb),
|
||||
.gpio (gpio_tb),
|
||||
.mprj_io (mprj_io_tb),
|
||||
.flash_csb(flash_csb_tb),
|
||||
.flash_clk(flash_clk_tb),
|
||||
.flash_io0(flash_io0_tb),
|
||||
.flash_io1(flash_io1_tb),
|
||||
.resetb (resetb_tb)
|
||||
);
|
||||
|
||||
spiflash #(
|
||||
FILENAME
|
||||
) spiflash (
|
||||
.csb(flash_csb_tb),
|
||||
.clk(flash_clk_tb),
|
||||
.io0(flash_io0_tb),
|
||||
.io1(flash_io1_tb),
|
||||
.io2(), // not used
|
||||
.io3() // not used
|
||||
);
|
||||
|
||||
mac macros();
|
||||
|
||||
|
||||
// make speical variables for the mprj input to assign the input without writing to the output gpios
|
||||
// cocotb limitation #2587
|
||||
wire bin0;
|
||||
wire bin0_en;
|
||||
wire bin1;
|
||||
wire bin1_en;
|
||||
wire bin2;
|
||||
wire bin2_en;
|
||||
wire bin3;
|
||||
wire bin3_en;
|
||||
wire bin4;
|
||||
wire bin4_en;
|
||||
wire bin5;
|
||||
wire bin5_en;
|
||||
wire bin6;
|
||||
wire bin6_en;
|
||||
wire bin7;
|
||||
wire bin7_en;
|
||||
wire bin8;
|
||||
wire bin8_en;
|
||||
wire bin9;
|
||||
wire bin9_en;
|
||||
wire bin10;
|
||||
wire bin10_en;
|
||||
wire bin11;
|
||||
wire bin11_en;
|
||||
wire bin12;
|
||||
wire bin12_en;
|
||||
wire bin13;
|
||||
wire bin13_en;
|
||||
wire bin14;
|
||||
wire bin14_en;
|
||||
wire bin15;
|
||||
wire bin15_en;
|
||||
wire bin16;
|
||||
wire bin16_en;
|
||||
wire bin17;
|
||||
wire bin17_en;
|
||||
wire bin18;
|
||||
wire bin18_en;
|
||||
wire bin19;
|
||||
wire bin19_en;
|
||||
wire bin20;
|
||||
wire bin20_en;
|
||||
wire bin21;
|
||||
wire bin21_en;
|
||||
wire bin22;
|
||||
wire bin22_en;
|
||||
wire bin23;
|
||||
wire bin23_en;
|
||||
wire bin24;
|
||||
wire bin24_en;
|
||||
wire bin25;
|
||||
wire bin25_en;
|
||||
wire bin26;
|
||||
wire bin26_en;
|
||||
wire bin27;
|
||||
wire bin27_en;
|
||||
wire bin28;
|
||||
wire bin28_en;
|
||||
wire bin29;
|
||||
wire bin29_en;
|
||||
wire bin30;
|
||||
wire bin30_en;
|
||||
wire bin31;
|
||||
wire bin31_en;
|
||||
wire bin32;
|
||||
wire bin32_en;
|
||||
wire bin33;
|
||||
wire bin33_en;
|
||||
wire bin34;
|
||||
wire bin34_en;
|
||||
wire bin35;
|
||||
wire bin35_en;
|
||||
wire bin36;
|
||||
wire bin36_en;
|
||||
wire bin37;
|
||||
wire bin37_en;
|
||||
|
||||
|
||||
assign mprj_io_tb[0] = (bin0_en) ? bin0 : 1'bz;
|
||||
assign mprj_io_tb[1] = (bin1_en) ? bin1 : 1'bz;
|
||||
assign mprj_io_tb[2] = (bin2_en) ? bin2 : 1'bz;
|
||||
assign mprj_io_tb[3] = (bin3_en) ? bin3 : 1'bz;
|
||||
assign mprj_io_tb[4] = (bin4_en) ? bin4 : 1'bz;
|
||||
|
||||
assign mprj_io_tb[5] = (bin5_en) ? bin5 : 1'bz;
|
||||
assign mprj_io_tb[6] = (bin6_en) ? bin6 : 1'bz;
|
||||
assign mprj_io_tb[7] = (bin7_en) ? bin7 : 1'bz;
|
||||
assign mprj_io_tb[8] = (bin8_en) ? bin8 : 1'bz;
|
||||
assign mprj_io_tb[9] = (bin9_en) ? bin9 : 1'bz;
|
||||
|
||||
assign mprj_io_tb[10] = (bin10_en) ? bin10 : 1'bz;
|
||||
assign mprj_io_tb[11] = (bin11_en) ? bin11 : 1'bz;
|
||||
assign mprj_io_tb[12] = (bin12_en) ? bin12 : 1'bz;
|
||||
assign mprj_io_tb[13] = (bin13_en) ? bin13 : 1'bz;
|
||||
assign mprj_io_tb[14] = (bin14_en) ? bin14 : 1'bz;
|
||||
|
||||
assign mprj_io_tb[15] = (bin15_en) ? bin15 : 1'bz;
|
||||
assign mprj_io_tb[16] = (bin16_en) ? bin16 : 1'bz;
|
||||
assign mprj_io_tb[17] = (bin17_en) ? bin17 : 1'bz;
|
||||
assign mprj_io_tb[18] = (bin18_en) ? bin18 : 1'bz;
|
||||
assign mprj_io_tb[19] = (bin19_en) ? bin19 : 1'bz;
|
||||
|
||||
assign mprj_io_tb[20] = (bin20_en) ? bin20 : 1'bz;
|
||||
assign mprj_io_tb[21] = (bin21_en) ? bin21 : 1'bz;
|
||||
assign mprj_io_tb[22] = (bin22_en) ? bin22 : 1'bz;
|
||||
assign mprj_io_tb[23] = (bin23_en) ? bin23 : 1'bz;
|
||||
assign mprj_io_tb[24] = (bin24_en) ? bin24 : 1'bz;
|
||||
|
||||
assign mprj_io_tb[25] = (bin25_en) ? bin25 : 1'bz;
|
||||
assign mprj_io_tb[26] = (bin26_en) ? bin26 : 1'bz;
|
||||
assign mprj_io_tb[27] = (bin27_en) ? bin27 : 1'bz;
|
||||
assign mprj_io_tb[28] = (bin28_en) ? bin28 : 1'bz;
|
||||
assign mprj_io_tb[29] = (bin29_en) ? bin29 : 1'bz;
|
||||
|
||||
assign mprj_io_tb[30] = (bin30_en) ? bin30 : 1'bz;
|
||||
assign mprj_io_tb[31] = (bin31_en) ? bin31 : 1'bz;
|
||||
assign mprj_io_tb[32] = (bin32_en) ? bin32 : 1'bz;
|
||||
assign mprj_io_tb[33] = (bin33_en) ? bin33 : 1'bz;
|
||||
assign mprj_io_tb[34] = (bin34_en) ? bin34 : 1'bz;
|
||||
|
||||
assign mprj_io_tb[35] = (bin35_en) ? bin35 : 1'bz;
|
||||
assign mprj_io_tb[36] = (bin36_en) ? bin36 : 1'bz;
|
||||
assign mprj_io_tb[37] = (bin37_en) ? bin37 : 1'bz;
|
||||
|
||||
endmodule
|
||||
|
||||
// module that has all needed macros by cocotb
|
||||
module mac;
|
||||
|
||||
reg [7:0] MPRJ_IO_PADS_1 = `ifdef MPRJ_IO_PADS_1 `MPRJ_IO_PADS_1 `else 0 `endif; /* number of user GPIO pads on user1 side */
|
||||
reg [7:0] MPRJ_IO_PADS_2 = `ifdef MPRJ_IO_PADS_2 `MPRJ_IO_PADS_2 `else 0 `endif; /* number of user GPIO pads on user2 side */
|
||||
reg [7:0] MPRJ_IO_PADS = `ifdef MPRJ_IO_PADS `MPRJ_IO_PADS `else 0 `endif;
|
||||
reg [7:0] MPRJ_PWR_PADS_1 =`ifdef MPRJ_PWR_PADS_1 `MPRJ_PWR_PADS_1 `else 0 `endif; /* vdda1, vccd1 enable/disable control */
|
||||
reg [7:0] MPRJ_PWR_PADS_2 = `ifdef MPRJ_PWR_PADS_2 `MPRJ_PWR_PADS_2 `else 0 `endif; /* vdda2, vccd2 enable/disable control */
|
||||
reg [7:0] MPRJ_PWR_PADS =`ifdef MPRJ_PWR_PADS `MPRJ_PWR_PADS `else 0 `endif;
|
||||
// Analog pads are only used by the "caravan" module and associated
|
||||
// modules such as user_analog_project_wrapper and chip_io_alt.
|
||||
reg [7:0] ANALOG_PADS_1 = `ifdef ANALOG_PADS_1 `ANALOG_PADS_1 `else 0 `endif;
|
||||
reg [7:0] ANALOG_PADS_2 = `ifdef ANALOG_PADS_2 `ANALOG_PADS_2 `else 0 `endif;
|
||||
reg [7:0] ANALOG_PADS = `ifdef ANALOG_PADS `ANALOG_PADS `else 0 `endif;
|
||||
|
||||
// Type and size of soc_mem
|
||||
reg USE_CUSTOM_DFFRAM = `ifdef USE_CUSTOM_DFFRAM 1 `else 0 `endif;
|
||||
// don't change the following without double checking addr widths
|
||||
reg [7:0] MEM_WORDS = `ifdef MEM_WORDS `MEM_WORDS `else 0 `endif;
|
||||
// Number of columns in the custom memory; takes one of three values:
|
||||
// 1 column : 1 KB, 2 column: 2 KB, 4 column: 4KB
|
||||
reg [7:0] DFFRAM_WSIZE = `ifdef DFFRAM_WSIZE `DFFRAM_WSIZE `else 0 `endif;
|
||||
reg [7:0] DFFRAM_USE_LATCH = `ifdef DFFRAM_USE_LATCH `DFFRAM_USE_LATCH `else 0 `endif;
|
||||
|
||||
// not really parameterized but just to easily keep track of the number
|
||||
// of ram_block across different modules
|
||||
reg [7:0] RAM_BLOCKS = `ifdef RAM_BLOCKS `RAM_BLOCKS `else 0 `endif;
|
||||
|
||||
// Clock divisor default value
|
||||
reg [7:0] CLK_DIV = `ifdef CLK_DIV `CLK_DIV `else 0 `endif;
|
||||
|
||||
// GPIO control default mode and enable for most I/Os
|
||||
// Most I/Os set to be user bidirectional pins on power-up.
|
||||
reg [7:0] MGMT_INIT = `ifdef MGMT_INIT `MGMT_INIT `else 0 `endif;
|
||||
reg [7:0] OENB_INIT = `ifdef OENB_INIT `OENB_INIT `else 0 `endif;
|
||||
reg [7:0] DM_INIT = `ifdef DM_INIT `DM_INIT `else 0 `endif;
|
||||
|
||||
// GL
|
||||
|
||||
reg GL = `ifdef GL 1 `else 0 `endif;
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,79 @@
|
|||
from cocotb.handle import SimHandleBase
|
||||
from cocotb.binary import BinaryValue
|
||||
from enum import Enum
|
||||
import cocotb
|
||||
"""return the value and the size of the signal"""
|
||||
def signal_value_size(path:SimHandleBase):
|
||||
value = path.value
|
||||
size = value.n_bits
|
||||
return value, size
|
||||
|
||||
|
||||
"""
|
||||
Create a binaryValue object with all Z that helps when drive to drive only the bits needed
|
||||
return value with all z and the size
|
||||
"""
|
||||
def signal_valueZ_size(path:SimHandleBase):
|
||||
value = path.value
|
||||
size = value.n_bits
|
||||
value = BinaryValue(value = int(size) * 'z',n_bits=size)
|
||||
return value, size
|
||||
|
||||
def int_to_bin_list(number:bin,number_of_bits)-> list:
|
||||
data = bin(number)
|
||||
data = data[2:].zfill(number_of_bits)[::-1]
|
||||
bits = [int(bit) for bit in data]
|
||||
return bits
|
||||
|
||||
def drive_hdl(path,bits,data):
|
||||
hdl , n_bits = signal_value_size(path)
|
||||
is_list_of_lists = all(isinstance(x, list) for x in bits)
|
||||
is_list_of_tuples = all(isinstance(x, tuple) for x in bits)
|
||||
if is_list_of_lists | is_list_of_tuples:
|
||||
for i,bits2 in enumerate(bits):
|
||||
hdl[n_bits-1-bits2[0]:n_bits-1-bits2[1]] = data[i]
|
||||
else:
|
||||
hdl[n_bits-1-bits[0]:n_bits-1-bits[1]] = data
|
||||
path.value = hdl
|
||||
cocotb.log.debug(f' [common] drive { path._path } with {hdl}')
|
||||
|
||||
"""Enum for GPIO modes valus used to configured the pins"""
|
||||
class GPIO_MODE(Enum):
|
||||
GPIO_MODE_MGMT_STD_INPUT_NOPULL = 0x0403
|
||||
GPIO_MODE_MGMT_STD_INPUT_PULLDOWN = 0x0803
|
||||
GPIO_MODE_MGMT_STD_INPUT_PULLUP = 0x0c03
|
||||
GPIO_MODE_MGMT_STD_OUTPUT = 0x1809
|
||||
GPIO_MODE_MGMT_STD_INPUT = 0x1803 # TODO: ask if this legal the default value for first 2 bin is like that
|
||||
GPIO_MODE_MGMT_STD_BIDIRECTIONAL = 0x1801
|
||||
GPIO_MODE_MGMT_STD_ANALOG = 0x000b
|
||||
GPIO_MODE_USER_STD_INPUT_NOPULL = 0x0402
|
||||
GPIO_MODE_USER_STD_INPUT_PULLDOWN = 0x0802
|
||||
GPIO_MODE_USER_STD_INPUT_PULLUP = 0x0c02
|
||||
GPIO_MODE_USER_STD_OUTPUT = 0x1808
|
||||
GPIO_MODE_USER_STD_BIDIRECTIONAL = 0x1800
|
||||
GPIO_MODE_USER_STD_OUT_MONITORED = 0x1802
|
||||
GPIO_MODE_USER_STD_ANALOG = 0x000a
|
||||
|
||||
class MASK_GPIO_CTRL(Enum):
|
||||
MASK_GPIO_CTRL_MGMT_EN = 0
|
||||
MASK_GPIO_CTRL_OUT_DIS = 1
|
||||
MASK_GPIO_CTRL_OVERRIDE = 2
|
||||
MASK_GPIO_CTRL_INP_DIS = 3
|
||||
MASK_GPIO_CTRL_MOD_SEL = 4
|
||||
MASK_GPIO_CTRL_ANLG_EN = 5
|
||||
MASK_GPIO_CTRL_ANLG_SEL = 6
|
||||
MASK_GPIO_CTRL_ANLG_POL = 7
|
||||
MASK_GPIO_CTRL_SLOW = 8
|
||||
MASK_GPIO_CTRL_TRIP = 9
|
||||
MASK_GPIO_CTRL_DGTL_MODE = 10
|
||||
|
||||
Macros= {}
|
||||
|
||||
def fill_macros(macros_hdl):
|
||||
Macros['MPRJ_IO_PADS_1'] = macros_hdl.MPRJ_IO_PADS_1.value.integer
|
||||
Macros['MPRJ_IO_PADS_2'] = macros_hdl.MPRJ_IO_PADS_2.value.integer
|
||||
Macros['MPRJ_IO_PADS'] = macros_hdl.MPRJ_IO_PADS.value.integer
|
||||
Macros['GL'] = macros_hdl.GL.value.integer
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,226 @@
|
|||
from operator import add
|
||||
import random
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
|
||||
import cocotb.log
|
||||
import cocotb.simulator
|
||||
from cocotb.handle import SimHandleBase
|
||||
from cocotb.handle import Force
|
||||
from cocotb_coverage.coverage import *
|
||||
from cocotb.binary import BinaryValue
|
||||
import enum
|
||||
from cocotb.handle import (
|
||||
ConstantObject,
|
||||
HierarchyArrayObject,
|
||||
HierarchyObject,
|
||||
ModifiableObject,
|
||||
NonHierarchyIndexableObject,
|
||||
SimHandle,
|
||||
)
|
||||
|
||||
from itertools import groupby, product
|
||||
|
||||
import common
|
||||
from common import GPIO_MODE
|
||||
from common import MASK_GPIO_CTRL
|
||||
from common import Macros
|
||||
|
||||
class RiskV:
|
||||
def __init__(self,dut:SimHandleBase):
|
||||
self.dut = dut
|
||||
self.clk = dut.clock_tb
|
||||
if not Macros['GL']:
|
||||
self.cpu_hdl = dut.uut.soc.core.VexRiscv
|
||||
else:
|
||||
self.cpu_hdl = dut.uut.soc.core
|
||||
self.debug_hdl = dut.uut.mprj.debug
|
||||
self.force_reset = 0
|
||||
cocotb.scheduler.add(self.force_reset_fun())
|
||||
|
||||
|
||||
""" """
|
||||
async def drive_data_with_address(self,address,data,SEL=0xF):
|
||||
self.cpu_hdl.dBusWishbone_CYC.value = 1
|
||||
self.cpu_hdl.iBusWishbone_CYC.value = 0
|
||||
self.cpu_hdl.dBusWishbone_STB.value = 1
|
||||
self.cpu_hdl.dBusWishbone_WE.value = 1
|
||||
self.cpu_hdl.dBusWishbone_SEL.value = SEL
|
||||
self.cpu_hdl.dBusWishbone_ADR.value = address >> 2
|
||||
self.cpu_hdl.dBusWishbone_DAT_MOSI.value = data
|
||||
await RisingEdge(self.cpu_hdl.dBusWishbone_ACK)
|
||||
await ClockCycles(self.clk, 1)
|
||||
self.cpu_hdl.dBusWishbone_CYC.value = BinaryValue(value = 'z')
|
||||
self.cpu_hdl.iBusWishbone_CYC.value = BinaryValue(value = 'z')
|
||||
self.cpu_hdl.dBusWishbone_STB.value = BinaryValue(value = 'z')
|
||||
self.cpu_hdl.dBusWishbone_WE.value = BinaryValue(value = 'z')
|
||||
self.cpu_hdl.dBusWishbone_SEL.value = BinaryValue(value = 'zzzz')
|
||||
self.cpu_hdl.dBusWishbone_ADR.value = common.signal_valueZ_size(self.cpu_hdl.dBusWishbone_ADR)[0]
|
||||
self.cpu_hdl.dBusWishbone_DAT_MOSI.value = common.signal_valueZ_size(self.cpu_hdl.dBusWishbone_DAT_MOSI)[0]
|
||||
|
||||
""" """
|
||||
async def drive_data2address(self,address,data,SEL=0xF):
|
||||
cocotb.log.info(f"[RiskV][drive_data2address] start driving address {hex(address)} with {hex(data)}")
|
||||
# print(dir(self.cpu_hdl))
|
||||
dBusWishbone_CYC = self.cpu_hdl.dBusWishbone_CYC.value
|
||||
if not Macros['GL']:
|
||||
iBusWishbone_CYC = self.cpu_hdl.iBusWishbone_CYC.value
|
||||
dBusWishbone_STB = self.cpu_hdl.dBusWishbone_STB.value
|
||||
dBusWishbone_WE = self.cpu_hdl.dBusWishbone_WE.value
|
||||
if not Macros['GL']:
|
||||
dBusWishbone_SEL = self.cpu_hdl.dBusWishbone_SEL.value
|
||||
else:
|
||||
dBusWishbone_SEL0 = self.cpu_hdl.net2121.value
|
||||
dBusWishbone_SEL1 = self.cpu_hdl.net1979.value
|
||||
dBusWishbone_SEL2 = self.cpu_hdl.net848.value
|
||||
dBusWishbone_SEL3 = self.cpu_hdl.net1956.value
|
||||
if not Macros['GL']:
|
||||
dBusWishbone_ADR = self.cpu_hdl.dBusWishbone_ADR.value
|
||||
dBusWishbone_DAT_MOSI = self.cpu_hdl.dBusWishbone_DAT_MOSI.value
|
||||
self.cpu_hdl.dBusWishbone_CYC.value = 1
|
||||
|
||||
if not Macros['GL']:
|
||||
self.cpu_hdl.iBusWishbone_CYC.value = 0
|
||||
self.cpu_hdl.dBusWishbone_STB.value = 1
|
||||
self.cpu_hdl.dBusWishbone_WE.value = 1
|
||||
if not Macros['GL']:
|
||||
self.cpu_hdl.dBusWishbone_SEL.value = SEL
|
||||
else:
|
||||
self.cpu_hdl.net2121.value = (SEL >>0 ) &1
|
||||
self.cpu_hdl.net1979.value = (SEL >>1 ) &1
|
||||
self.cpu_hdl.net848.value = (SEL >>2 ) &1
|
||||
self.cpu_hdl.net1956.value = (SEL >>3 ) &1
|
||||
|
||||
if not Macros['GL']:
|
||||
self.cpu_hdl.dBusWishbone_ADR.value = address >> 2
|
||||
else:
|
||||
address_temp = address >> 2
|
||||
for i in range(30):
|
||||
self.cpu_hdl._id(f'dBusWishbone_ADR[{i}]',False).value = (address_temp >> i) & 1
|
||||
if not Macros['GL']:
|
||||
self.cpu_hdl.dBusWishbone_DAT_MOSI.value = data
|
||||
else:
|
||||
for i in range(32):
|
||||
self.cpu_hdl._id(f'dBusWishbone_DAT_MOSI[{i}]',False).value = (data >> i) & 1
|
||||
|
||||
if not Macros['GL']:
|
||||
await RisingEdge(self.cpu_hdl.dBusWishbone_ACK)
|
||||
else:
|
||||
# await RisingEdge(self.cpu_hdl._id("_07019_",False) & (self.cpu_hdl._id("grant[0]",False)))
|
||||
await RisingEdge(self.cpu_hdl._id("_07019_",False) )
|
||||
|
||||
await ClockCycles(self.clk, 1)
|
||||
self.cpu_hdl.dBusWishbone_CYC.value = dBusWishbone_CYC
|
||||
if not Macros['GL']:
|
||||
self.cpu_hdl.dBusWishbone_ADR.value = dBusWishbone_ADR
|
||||
self.cpu_hdl.dBusWishbone_DAT_MOSI.value = dBusWishbone_DAT_MOSI
|
||||
self.cpu_hdl.iBusWishbone_CYC.value = iBusWishbone_CYC
|
||||
self.cpu_hdl.dBusWishbone_STB.value = dBusWishbone_STB
|
||||
self.cpu_hdl.dBusWishbone_WE.value = dBusWishbone_WE
|
||||
self.cpu_hdl.dBusWishbone_SEL.value = dBusWishbone_SEL
|
||||
|
||||
await ClockCycles(self.clk, 1)
|
||||
cocotb.log.info(f"[RiskV][drive_data2address] finish driving address {hex(address)} with {hex(data)}")
|
||||
|
||||
""" """
|
||||
async def read_address(self,address,SEL=0xF):
|
||||
cocotb.log.info(f"[RiskV][read_address] start reading address {hex(address)}")
|
||||
# print(dir(self.cpu_hdl))
|
||||
dBusWishbone_CYC = self.cpu_hdl.dBusWishbone_CYC.value
|
||||
if not Macros['GL']:
|
||||
iBusWishbone_CYC = self.cpu_hdl.iBusWishbone_CYC.value
|
||||
dBusWishbone_STB = self.cpu_hdl.dBusWishbone_STB.value
|
||||
dBusWishbone_WE = self.cpu_hdl.dBusWishbone_WE.value
|
||||
if not Macros['GL']:
|
||||
dBusWishbone_SEL = self.cpu_hdl.dBusWishbone_SEL.value
|
||||
else:
|
||||
dBusWishbone_SEL0 = self.cpu_hdl.net2121.value
|
||||
dBusWishbone_SEL1 = self.cpu_hdl.net1979.value
|
||||
dBusWishbone_SEL2 = self.cpu_hdl.net848.value
|
||||
dBusWishbone_SEL3 = self.cpu_hdl.net1956.value
|
||||
if not Macros['GL']:
|
||||
dBusWishbone_ADR = self.cpu_hdl.dBusWishbone_ADR.value
|
||||
dBusWishbone_DAT_MOSI = self.cpu_hdl.dBusWishbone_DAT_MOSI.value
|
||||
self.cpu_hdl.dBusWishbone_CYC.value = 1
|
||||
|
||||
if not Macros['GL']:
|
||||
self.cpu_hdl.iBusWishbone_CYC.value = 0
|
||||
self.cpu_hdl.dBusWishbone_STB.value = 1
|
||||
self.cpu_hdl.dBusWishbone_WE.value = 0
|
||||
if not Macros['GL']:
|
||||
self.cpu_hdl.dBusWishbone_SEL.value = SEL
|
||||
else:
|
||||
self.cpu_hdl.net2121.value = (SEL >>0 ) &1
|
||||
self.cpu_hdl.net1979.value = (SEL >>1 ) &1
|
||||
self.cpu_hdl.net848.value = (SEL >>2 ) &1
|
||||
self.cpu_hdl.net1956.value = (SEL >>3 ) &1
|
||||
|
||||
if not Macros['GL']:
|
||||
self.cpu_hdl.dBusWishbone_ADR.value = address >> 2
|
||||
else:
|
||||
address_temp = address >> 2
|
||||
for i in range(30):
|
||||
self.cpu_hdl._id(f'dBusWishbone_ADR[{i}]',False).value = (address_temp >> i) & 1
|
||||
|
||||
|
||||
if not Macros['GL']:
|
||||
await RisingEdge(self.cpu_hdl.dBusWishbone_ACK)
|
||||
else:
|
||||
# await RisingEdge(self.cpu_hdl._id("_07019_",False) & (self.cpu_hdl._id("grant[0]",False)))
|
||||
await RisingEdge(self.cpu_hdl._id("_07019_",False) )
|
||||
|
||||
await ClockCycles(self.clk, 1)
|
||||
self.cpu_hdl.dBusWishbone_CYC.value = dBusWishbone_CYC
|
||||
if not Macros['GL']:
|
||||
self.cpu_hdl.dBusWishbone_ADR.value = dBusWishbone_ADR
|
||||
self.cpu_hdl.dBusWishbone_DAT_MOSI.value = dBusWishbone_DAT_MOSI
|
||||
self.cpu_hdl.iBusWishbone_CYC.value = iBusWishbone_CYC
|
||||
self.cpu_hdl.dBusWishbone_STB.value = dBusWishbone_STB
|
||||
self.cpu_hdl.dBusWishbone_WE.value = dBusWishbone_WE
|
||||
self.cpu_hdl.dBusWishbone_SEL.value = dBusWishbone_SEL
|
||||
data = self.cpu_hdl.dBusWishbone_DAT_MISO.value
|
||||
await ClockCycles(self.clk, 1)
|
||||
cocotb.log.info(f"[RiskV][read_address] finish reading address {hex(address)} data = {data}")
|
||||
|
||||
# return data
|
||||
return int(str(bin(data.integer)[2:]).zfill(32),2)
|
||||
# return int(str(bin(data.integer)[2:]).zfill(32)[::-1],2)
|
||||
|
||||
|
||||
def read_debug_reg1(self):
|
||||
return self.debug_hdl.debug_reg_1.value.integer
|
||||
def read_debug_reg2(self):
|
||||
return self.debug_hdl.debug_reg_2.value.integer
|
||||
|
||||
async def force_reset_fun(self):
|
||||
first_time_force = True
|
||||
first_time_release = True
|
||||
while True:
|
||||
if self.force_reset:
|
||||
if first_time_force:
|
||||
cocotb.log.info(f"[RiskV][force_reset_fun] Force CPU reset")
|
||||
first_time_force = False
|
||||
first_time_release = True
|
||||
self.cpu_hdl.reset.value =1
|
||||
if not Macros['GL']:
|
||||
common.drive_hdl(self.cpu_hdl.reset,(0,0),1)
|
||||
else:
|
||||
common.drive_hdl(self.cpu_hdl.mgmtsoc_vexriscv_debug_reset,(0,0),1)
|
||||
else:
|
||||
if first_time_release:
|
||||
first_time_force = True
|
||||
first_time_release = False
|
||||
|
||||
if not Macros['GL']:
|
||||
common.drive_hdl(self.cpu_hdl.reset,(0,0),0)
|
||||
else:
|
||||
common.drive_hdl(self.cpu_hdl.mgmtsoc_vexriscv_debug_reset,(0,0),0)
|
||||
cocotb.log.info(f"[RiskV][force_reset_fun] release CPU reset")
|
||||
|
||||
await ClockCycles(self.clk, 1)
|
||||
def cpu_force_reset(self):
|
||||
self.force_reset = True
|
||||
|
||||
def cpu_release_reset(self):
|
||||
self.force_reset = False
|
||||
|
||||
|
|
@ -0,0 +1,87 @@
|
|||
import re
|
||||
import sys
|
||||
from tokenize import group
|
||||
from unittest.util import _MIN_COMMON_LEN
|
||||
import string
|
||||
import cocotb
|
||||
import os
|
||||
class Regs:
|
||||
def __init__(self):
|
||||
pass
|
||||
|
||||
def get_addr(self,reg):
|
||||
search1 = self.get_add_defs(reg)
|
||||
# if all(c in string.hexdigits for c in search1[2:]):
|
||||
return int(search1,16)
|
||||
# return hex(self.get_hexa(search1))
|
||||
|
||||
|
||||
"""get address from defs.h"""
|
||||
def get_add_defs(self,reg):
|
||||
pattern = re.compile(rf'#define {reg}\s*\(\*\(volatile uint32_t\*\)\s*(.*)\s*\)')
|
||||
with open(f'{os.getenv("FIRMWARE_PATH")}/defs.h') as f:
|
||||
for line in f:
|
||||
m= re.search(pattern,line)
|
||||
if m:
|
||||
break
|
||||
if m:
|
||||
if not all(c in string.hexdigits for c in m.group(1)):
|
||||
return hex(self.get_hexa(m.group(1)))
|
||||
else:
|
||||
return m.group(1)
|
||||
else:
|
||||
cocotb.log.info(f" [defsParser] can't find {reg} inside defs")
|
||||
sys.exit()
|
||||
|
||||
"""get address from defs.h"""
|
||||
def get_add_csr(self,reg):
|
||||
pattern1 = re.compile(rf'#define {reg}\s*\(\*\(volatile uint32_t\*\)\s*(.*)\s*\)')
|
||||
pattern2 = re.compile(rf'#define {reg}\s*(.*)')
|
||||
m = False
|
||||
with open(f'{os.getenv("FIRMWARE_PATH")}/../generated/csr.h') as f:
|
||||
for line in f:
|
||||
m1= re.search(pattern1,line)
|
||||
m2= re.search(pattern2,line)
|
||||
if m1:
|
||||
m = m1
|
||||
break
|
||||
if m2:
|
||||
m=m2
|
||||
break
|
||||
if m:
|
||||
matched_str= m.group(1)
|
||||
if matched_str[-1] == "L" and matched_str[-2].isnumeric:
|
||||
matched_str = matched_str[:-1]
|
||||
if not all(c in string.hexdigits for c in matched_str[2:]):
|
||||
matched_str= hex(self.get_hexa(matched_str))
|
||||
|
||||
return matched_str
|
||||
else:
|
||||
cocotb.log.info(f" [defsParser] can't find {reg} inside csr")
|
||||
sys.exit()
|
||||
|
||||
|
||||
def get_hexa(self,s:string):
|
||||
pattern2 = re.compile(r'\((.*)\s*\+\s*(.*)\)')
|
||||
search_match = re.search(pattern2,s)
|
||||
if search_match :
|
||||
matches = [search_match.group(1),search_match.group(2)]
|
||||
else:
|
||||
matches = [s]
|
||||
nothex = 1
|
||||
while nothex:
|
||||
nothex = 0
|
||||
for i,match in enumerate(matches):
|
||||
if not all(c in string.hexdigits for c in match[2:-1]):
|
||||
matches[i]=self.get_add_csr(match)
|
||||
nothex = 0
|
||||
else:
|
||||
if match[-1] == "L" and match[-2].isnumeric:
|
||||
matches[i]=matches[i][:-1]
|
||||
|
||||
if len(matches) ==2:
|
||||
return int(matches[0],16) + int(matches[1],16)
|
||||
else:
|
||||
return int(matches[0],16)
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,70 @@
|
|||
@00000000
|
||||
6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00
|
||||
13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00
|
||||
23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE
|
||||
23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE
|
||||
23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD
|
||||
23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD
|
||||
13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03
|
||||
03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02
|
||||
03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01
|
||||
03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00
|
||||
03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30
|
||||
17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6
|
||||
73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00
|
||||
13 06 46 38 63 0C B5 00 83 26 06 00 23 20 D5 00
|
||||
13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00
|
||||
93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00
|
||||
6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30
|
||||
EF 00 80 17 6F 00 00 00 13 01 01 FF 23 26 81 00
|
||||
13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01
|
||||
67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01
|
||||
13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00
|
||||
13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE
|
||||
83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01
|
||||
13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00
|
||||
23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC
|
||||
B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00
|
||||
B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00
|
||||
13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00
|
||||
03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF
|
||||
23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00
|
||||
13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00
|
||||
13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01
|
||||
67 80 00 00 13 01 01 FE 23 2E 81 00 13 04 01 02
|
||||
23 26 A4 FE 83 27 C4 FE 63 86 07 00 73 60 04 30
|
||||
6F 00 80 00 73 70 04 30 13 00 00 00 03 24 C1 01
|
||||
13 01 01 02 67 80 00 00 13 01 01 FE 23 2E 81 00
|
||||
13 04 01 02 F3 27 00 BC 23 26 F4 FE 83 27 C4 FE
|
||||
13 85 07 00 03 24 C1 01 13 01 01 02 67 80 00 00
|
||||
13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE
|
||||
83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01
|
||||
13 01 01 02 67 80 00 00 13 01 01 FE 23 2E 11 00
|
||||
23 2C 81 00 13 04 01 02 B7 47 00 F0 93 87 07 80
|
||||
13 07 10 00 23 A0 E7 00 B7 07 10 30 93 87 87 FF
|
||||
23 A0 07 00 B7 07 10 30 93 87 C7 FF 23 A0 07 00
|
||||
B7 07 00 26 93 87 07 04 13 07 30 40 23 A0 E7 00
|
||||
B7 07 00 26 13 07 10 00 23 A0 E7 00 13 00 00 00
|
||||
B7 07 00 26 03 A7 07 00 93 07 10 00 E3 0A F7 FE
|
||||
13 05 00 00 EF F0 DF F6 13 05 10 00 EF F0 9F F0
|
||||
EF F0 9F F3 93 07 05 00 93 E7 07 04 13 85 07 00
|
||||
EF F0 1F F5 B7 97 00 F0 93 87 47 81 13 07 10 00
|
||||
23 A0 E7 00 B7 07 10 30 93 87 C7 FF 13 07 A0 0A
|
||||
23 A0 E7 00 23 10 00 00 A3 07 04 FE 93 07 80 02
|
||||
23 20 F4 FE 23 24 04 FE 6F 00 80 03 03 57 00 00
|
||||
93 07 10 00 63 10 F7 02 B7 07 10 30 93 87 87 FF
|
||||
13 07 B0 01 23 A0 E7 00 93 07 10 00 A3 07 F4 FE
|
||||
6F 00 C0 01 83 27 84 FE 93 87 17 00 23 24 F4 FE
|
||||
03 27 84 FE 83 27 04 FE E3 42 F7 FC 83 47 F4 FE
|
||||
93 C7 17 00 93 F7 F7 0F 63 8A 07 00 B7 07 10 30
|
||||
93 87 87 FF 13 07 E0 01 23 A0 E7 00 B7 07 10 30
|
||||
93 87 C7 FF 13 07 B0 0B 23 A0 E7 00 23 10 00 00
|
||||
A3 07 04 FE 23 22 04 FE 6F 00 80 03 03 57 00 00
|
||||
93 07 10 00 63 10 F7 02 B7 07 10 30 93 87 87 FF
|
||||
13 07 E0 02 23 A0 E7 00 93 07 10 00 A3 07 F4 FE
|
||||
6F 00 C0 01 83 27 44 FE 93 87 17 00 23 22 F4 FE
|
||||
03 27 44 FE 83 27 04 FE E3 42 F7 FC 83 47 F4 FE
|
||||
93 C7 17 00 93 F7 F7 0F 63 8A 07 00 B7 07 10 30
|
||||
93 87 87 FF 13 07 B0 02 23 A0 E7 00 B7 07 10 30
|
||||
93 87 C7 FF 13 07 F0 0F 23 A0 E7 00 13 00 00 00
|
||||
83 20 C1 01 03 24 81 01 13 01 01 02 67 80 00 00
|
||||
|
|
@ -0,0 +1,71 @@
|
|||
@00000000
|
||||
6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00
|
||||
13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00
|
||||
23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE
|
||||
23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE
|
||||
23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD
|
||||
23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD
|
||||
13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03
|
||||
03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02
|
||||
03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01
|
||||
03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00
|
||||
03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30
|
||||
17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6
|
||||
73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00
|
||||
13 06 C6 38 63 0C B5 00 83 26 06 00 23 20 D5 00
|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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|
||||
23 A0 E7 00 B7 07 00 26 93 87 87 07 37 27 00 00
|
||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|||
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||||
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||||
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|
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|||
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||||
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||||
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||||
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|
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|||
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||||
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||||
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|
||||
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||||
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|||
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||||
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||||
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|||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
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|||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
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|
|||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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|
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|||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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|
||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
67 80 00 00
|
||||
|
|
@ -0,0 +1,168 @@
|
|||
@00000000
|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
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||||
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|||
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||||
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||||
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|
||||
EF F0 DF F1 23 26 04 FE 6F 00 00 01 83 27 C4 FE
|
||||
93 87 17 00 23 26 F4 FE 03 27 C4 FE 93 07 F0 09
|
||||
E3 D6 E7 FE 13 00 00 00 13 00 00 00 83 20 C1 01
|
||||
03 24 81 01 13 01 01 02 67 80 00 00
|
||||
@0000038C
|
||||
00 00 00 00 4D 6F 6E 69 74 6F 72 3A 20 54 65 73
|
||||
74 20 55 41 52 54 20 28 52 54 4C 29 20 70 61 73
|
||||
73 65 64 00
|
||||
|
|
@ -0,0 +1,84 @@
|
|||
import random
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
|
||||
import cocotb.log
|
||||
import cocotb.simulator
|
||||
from cocotb.handle import SimHandleBase
|
||||
from cocotb.handle import Force
|
||||
from cocotb_coverage.coverage import *
|
||||
from cocotb.binary import BinaryValue
|
||||
import enum
|
||||
from cocotb.handle import (
|
||||
ConstantObject,
|
||||
HierarchyArrayObject,
|
||||
HierarchyObject,
|
||||
ModifiableObject,
|
||||
NonHierarchyIndexableObject,
|
||||
SimHandle,
|
||||
)
|
||||
|
||||
from itertools import groupby, product
|
||||
|
||||
import common
|
||||
from common import GPIO_MODE
|
||||
from common import MASK_GPIO_CTRL
|
||||
from common import Macros
|
||||
|
||||
class LA:
|
||||
def __init__(self,dut:SimHandleBase):
|
||||
self.dut = dut
|
||||
self.clk = dut.clock_tb
|
||||
self.core_hdl = dut.uut.soc.core
|
||||
|
||||
|
||||
""" Configure the value of LA probes [0:127]
|
||||
writing 1 to any bit means bit acts as outputs from the cpu
|
||||
writing 0 to any bit means bit acts as inputs to the cpu """
|
||||
async def configure_la_en(self, bits,data):
|
||||
self.__drive_la_iena(bits,data)
|
||||
self.__drive_la_oenb(bits,data)
|
||||
await ClockCycles(self.clk, 1)
|
||||
|
||||
|
||||
|
||||
def __drive_la_iena(self, bits,data):
|
||||
iena , n_bits = common.signal_value_size(self.core_hdl.la_ien_storage)
|
||||
cocotb.log.debug(f' [LA] before change iena with {iena} and data = {data} bit [{n_bits-1-bits[0]}]:[{n_bits-1-bits[1]}]')
|
||||
iena[n_bits-1-bits[0]:n_bits-1-bits[1]] = data
|
||||
self.core_hdl.la_ien_storage.value = iena
|
||||
cocotb.log.info(f' [LA] drive reg_la_iena with {hex(iena)}')
|
||||
|
||||
def __drive_la_oenb(self, bits,data):
|
||||
oenb , n_bits = common.signal_value_size(self.core_hdl.la_oe_storage)
|
||||
cocotb.log.debug(f' [LA] before change oenb with {oenb} and data = {data} bit [{n_bits-1-bits[0]}]:[{n_bits-1-bits[1]}]')
|
||||
oenb[n_bits-1-bits[0]:n_bits-1-bits[1]] = data
|
||||
self.core_hdl.la_oe_storage.value = oenb
|
||||
cocotb.log.info(f' [LA] drive reg_la_oenb with {hex(oenb)}')
|
||||
|
||||
""" update the value of LA data input from cpu to user project """
|
||||
def drive_la_data_to_user(self,bits,data):
|
||||
la , n_bits = common.signal_value_size(self.core_hdl.la_out_storage)
|
||||
cocotb.log.debug(f' [LA] before la data update with LA ={la} and data = {data} bit [{n_bits-1-bits[0]}]:[{n_bits-1-bits[1]}]')
|
||||
la[n_bits-1-bits[0]:n_bits-1-bits[1]] = data
|
||||
self.core_hdl.la_out_storage.value = la
|
||||
cocotb.log.info(f' [LA] drive_la_data_to_user: drive data {hex(la)} to user project')
|
||||
|
||||
"""return the value of LA data output from user project tp cpu"""
|
||||
def check_la_user_out(self):
|
||||
LA_out = self.core_hdl.la_input.value
|
||||
if(LA_out.is_resolvable):
|
||||
cocotb.log.info(f' [LA] Monitor : reg_la_data_out from user = {hex(LA_out)}')
|
||||
else:
|
||||
cocotb.log.info(f' [LA] Monitor : reg_la_data_out from user = {LA_out}')
|
||||
return LA_out
|
||||
|
||||
|
||||
"""return the value of LA data output from user project tp cpu"""
|
||||
def check_la_ctrl_reg(self):
|
||||
LA_out = self.dut.uut.la_oenb_mprj.value
|
||||
if(LA_out.is_resolvable):
|
||||
cocotb.log.info(f' [LA] Monitor : reg_la_data_out from user = {hex(LA_out)}')
|
||||
else:
|
||||
cocotb.log.info(f' [LA] Monitor : reg_la_data_out from user = {LA_out}')
|
||||
return LA_out
|
||||
|
|
@ -0,0 +1 @@
|
|||
acc+=rw,wn:*
|
||||
|
|
@ -0,0 +1,303 @@
|
|||
#!/usr/bin/python3
|
||||
# -*- coding: utf-8 -*-
|
||||
import collections
|
||||
import json
|
||||
import sys
|
||||
import os
|
||||
from pathlib import Path
|
||||
import json
|
||||
from fnmatch import fnmatch
|
||||
from datetime import datetime
|
||||
import random
|
||||
from pathlib import Path
|
||||
|
||||
def go_up(path, n):
|
||||
for i in range(n):
|
||||
path = os.path.dirname(path)
|
||||
return path
|
||||
# search pattern in file
|
||||
def search_str(file_path, word):
|
||||
with open(file_path, 'r') as file:
|
||||
# read all content of a file
|
||||
content = file.read()
|
||||
# check if string present in a file
|
||||
if word in content:
|
||||
return "passed"
|
||||
else:
|
||||
return "failed"
|
||||
|
||||
|
||||
class RunTest:
|
||||
def __init__(self,test_name,sim) -> None:
|
||||
self.cocotb_path = os.getcwd()
|
||||
self.test_name = test_name
|
||||
self.sim_type = sim
|
||||
self.create_log_file()
|
||||
self.hex_generate()
|
||||
self.runTest()
|
||||
|
||||
# create and open full terminal log to be able to use it before run the test
|
||||
def create_log_file(self):
|
||||
self.cd_cocotb()
|
||||
os.chdir(f"sim/{os.getenv('RUNTAG')}")
|
||||
test_dir = f"{self.sim_type}-{self.test_name}"
|
||||
os.makedirs(f"{test_dir}",exist_ok=True)
|
||||
self.cd_cocotb()
|
||||
self.sim_path = f"sim/{os.getenv('RUNTAG')}/{test_dir}/"
|
||||
terminal_log=f"{self.sim_path}/fullTerminal.log"
|
||||
test_log=f"{self.sim_path}/{self.test_name}.log"
|
||||
self.full_terminal = open(test_log, "w")
|
||||
|
||||
# iverilog function
|
||||
# def runTest(self):
|
||||
# print(f"Start running test: {self.sim_type}-{self.test_name}")
|
||||
# os.system(f"TestName={self.test_name} SIM={self.sim_type} make cocotb >> {self.full_terminal.name} ")
|
||||
# self.passed = search_str(self.full_terminal.name,"Test passed with (0)criticals (0)errors")
|
||||
# Path(f'{self.sim_path}/{self.passed}').touch()
|
||||
|
||||
# vcs function
|
||||
def runTest(self):
|
||||
print(f"Start running test: {self.sim_type}-{self.test_name}")
|
||||
dirs = f'+incdir+\\\"{go_up(self.cocotb_path,4)}\\\" '
|
||||
macros = f'+define+FUNCTIONAL +define+USE_POWER_PINS +define+UNIT_DELAY=#1 +define+MAIN_PATH=\\\"{self.cocotb_path}\\\" +define+VCS'
|
||||
# shutil.copyfile(f'{self.test_full_dir}/{self.test_name}.hex',f'{self.sim_path}/{self.test_name}.hex')
|
||||
# if os.path.exists(f'{self.test_full_dir}/test_data'):
|
||||
# shutil.copyfile(f'{self.test_full_dir}/test_data',f'{self.sim_path}/test_data')
|
||||
if (self.sim_type=="GL_SDF"):
|
||||
macros = f'{macros} +define+ENABLE_SDF +define+SIM=GL_SDF +define+GL +define+SDF_POSTFIX=\\\"-{self.corner}\\\"'
|
||||
os.makedirs(f"annotation_logs",exist_ok=True)
|
||||
elif(self.sim_type=="GL"):
|
||||
macros = f'{macros} +define+GL +define+SIM=GL'
|
||||
elif (self.sim_type=="RTL"):
|
||||
macros = f'{macros} +define+SIM=\\\"RTL\\\"'
|
||||
else:
|
||||
print(f"Fatal: incorrect simulation type {self.sim_type}")
|
||||
|
||||
os.environ["TESTCASE"] = f"{self.test_name}"
|
||||
os.environ["MODULE"] = f"caravel_tests"
|
||||
os.environ["SIM"] = self.sim_type
|
||||
|
||||
os.system(f"vlogan -full64 -sverilog +error+25 caravel_top.sv {dirs} {macros} +define+TESTNAME=\\\"{self.test_name}\\\" +define+FTESTNAME=\\\"{self.sim_type}-{self.test_name}\\\" +define+TAG=\\\"{os.getenv('RUNTAG')}\\\" -l {self.sim_path}/analysis.log -o {self.sim_path} ")
|
||||
os.system(f"vcs -cm line -R -diag=sdf:verbose +sdfverbose +neg_tchk -debug_access -full64 -l {self.sim_path}/test.log caravel_top -Mdir={self.sim_path}/csrc -o {self.sim_path}/simv +vpi -P pli.tab -load $(cocotb-config --lib-name-path vpi vcs)")
|
||||
self.passed = search_str(self.full_terminal.name,"Test passed with (0)criticals (0)errors")
|
||||
Path(f'{self.sim_path}/{self.passed}').touch()
|
||||
|
||||
def find(self,name, path):
|
||||
for root, dirs, files in os.walk(path):
|
||||
if name in files:
|
||||
return os.path.join(root, name)
|
||||
print(f"Test {name} doesn't exist or don't have a C file ")
|
||||
|
||||
def test_path(self):
|
||||
test_name = self.test_name
|
||||
test_name += ".c"
|
||||
tests_path = os.path.abspath(f"{self.cocotb_path}/tests")
|
||||
test_file = self.find(test_name,tests_path)
|
||||
test_path = os.path.dirname(test_file)
|
||||
return (test_path)
|
||||
|
||||
def hex_generate(self):
|
||||
#open docker
|
||||
test_path =self.test_path()
|
||||
self.cd_make()
|
||||
elf_out = f"{self.cocotb_path}/hex_files/{self.test_name}.elf"
|
||||
c_file = f"{test_path}/{self.test_name}.c"
|
||||
hex_file = f"{self.cocotb_path}/hex_files/{self.test_name}.hex"
|
||||
GCC_PATH = "/foss/tools/riscv-gnu-toolchain-rv32i/217e7f3debe424d61374d31e33a091a630535937/bin/"
|
||||
GCC_PREFIX = "riscv32-unknown-linux-gnu"
|
||||
SOURCE_FILES = f"{os.getenv('FIRMWARE_PATH')}/crt0_vex.S {os.getenv('FIRMWARE_PATH')}/isr.c"
|
||||
LINKER_SCRIPT = f"{os.getenv('FIRMWARE_PATH')}/sections.lds"
|
||||
CPUFLAGS = f"-march=rv32i -mabi=ilp32 -D__vexriscv__ "
|
||||
verilog_path = f"{os.getenv('VERILOG_PATH')}"
|
||||
test_dir = f"{os.getenv('VERILOG_PATH')}/dv/tests-caravel/mem" # linker script include // TODO: to fix this in the future from the mgmt repo
|
||||
print(test_dir)
|
||||
elf_command = (f"{GCC_PATH}/{GCC_PREFIX}-gcc -g -I{verilog_path}/dv/firmware -I{verilog_path}/dv/generated -I{verilog_path}/dv/ "
|
||||
f"-I{verilog_path}/common {CPUFLAGS} -Wl,-Bstatic,-T,{LINKER_SCRIPT},"
|
||||
f"--strip-debug -ffreestanding -nostdlib -o {elf_out} {SOURCE_FILES} {c_file}")
|
||||
hex_command = f"{GCC_PATH}/{GCC_PREFIX}-objcopy -O verilog {elf_out} {hex_file} "
|
||||
sed_command = f"sed -ie 's/@10/@00/g' {hex_file}"
|
||||
os.system(f"docker run -it -v /home:/home efabless/dv:latest sh -c 'cd {test_dir} && {elf_command} && {hex_command} && {sed_command} '")
|
||||
self.full_terminal.write(os.path.expandvars(elf_command)+"\n"+"\n")
|
||||
self.full_terminal.write(os.path.expandvars(hex_command)+"\n"+"\n")
|
||||
self.full_terminal.write(os.path.expandvars(sed_command)+"\n"+"\n")
|
||||
self.cd_cocotb()
|
||||
self.full_terminal.close()
|
||||
|
||||
|
||||
def cd_make(self):
|
||||
os.chdir(f"{os.getenv('VERILOG_PATH')}/dv/make")
|
||||
|
||||
def cd_cocotb(self):
|
||||
os.chdir(self.cocotb_path)
|
||||
|
||||
class RunRegression:
|
||||
def __init__(self,regression,test,type_arg,testlist) -> None:
|
||||
self.regression_arg = regression
|
||||
self.test_arg = test
|
||||
self.testlist_arg = testlist
|
||||
if type_arg is None:
|
||||
type_arg = "RTL"
|
||||
self.type_arg = type_arg
|
||||
self.write_command_log()
|
||||
with open('tests.json') as f:
|
||||
self.tests_json = json.load(f)
|
||||
self.tests_json = self.tests_json["Tests"]
|
||||
self.get_tests()
|
||||
self.run_regression()
|
||||
|
||||
def get_tests(self):
|
||||
self.tests = collections.defaultdict(lambda : collections.defaultdict(dict)) #key is testname and value is list of sim types
|
||||
self.unknown_tests = 0
|
||||
self.passed_tests = 0
|
||||
self.failed_tests = 0
|
||||
# regression
|
||||
if self.regression_arg is not None:
|
||||
sim_types = ("RTL","GL","GL_SDF")
|
||||
for test,test_elements in self.tests_json.items():
|
||||
if fnmatch(test,"_*"):
|
||||
continue
|
||||
for sim_type in sim_types:
|
||||
if self.regression_arg in test_elements[sim_type]:
|
||||
self.add_new_test(test_name=test,sim_type = sim_type)
|
||||
if (len(self.tests)==0):
|
||||
print(f"fatal:{self.regression_arg} is not a valid regression name please input a valid regression \ncheck tests.json for more info")
|
||||
sys.exit()
|
||||
#test
|
||||
if self.test_arg is not None:
|
||||
if isinstance(self.test_arg,list):
|
||||
for test in self.test_arg:
|
||||
if test in self.tests_json:
|
||||
if isinstance(self.type_arg,list):
|
||||
for sim_type in self.type_arg:
|
||||
self.add_new_test(test_name=test,sim_type = sim_type)
|
||||
else:
|
||||
self.add_new_test(test_name=test,sim_type = self.type_arg)
|
||||
|
||||
else:
|
||||
if self.test_arg in self.tests_json:
|
||||
if isinstance(self.type_arg,list):
|
||||
for sim_type in self.type_arg:
|
||||
self.add_new_test(test_name=self.test_arg,sim_type = sim_type)
|
||||
else:
|
||||
self.add_new_test(test_name=self.test_arg,sim_type = self.type_arg)
|
||||
# testlist TODO: add logic for test list
|
||||
if self.testlist_arg is not None:
|
||||
print(f'fatal: code for test list isnt added yet')
|
||||
sys.exit()
|
||||
|
||||
|
||||
self.update_reg_log()
|
||||
|
||||
def add_new_test(self,test_name,sim_type):
|
||||
self.tests[test_name][sim_type]["status"]= "pending"
|
||||
self.tests[test_name][sim_type]["starttime"]= "-"
|
||||
self.tests[test_name][sim_type]["endtime"]= "-"
|
||||
self.tests[test_name][sim_type]["duration"] = "-"
|
||||
self.tests[test_name][sim_type]["pass"]= "-"
|
||||
self.unknown_tests +=1
|
||||
|
||||
def run_regression(self):
|
||||
for test,sim_types in self.tests.items():
|
||||
for sim_type,status in sim_types.items(): # TODO: add multithreading or multiprocessing here
|
||||
start_time = datetime.now()
|
||||
self.tests[test][sim_type]["starttime"] = datetime.now().strftime("%H:%M:%S(%a)")
|
||||
self.tests[test][sim_type]["duration"] = "-"
|
||||
self.tests[test][sim_type]["status"] = "running"
|
||||
self.update_reg_log()
|
||||
test_run = RunTest(test,sim_type)
|
||||
self.tests[test][sim_type]["status"] = "done"
|
||||
self.tests[test][sim_type]["endtime"] = datetime.now().strftime("%H:%M:%S(%a)")
|
||||
self.tests[test][sim_type]["duration"] = ("%.10s" % (datetime.now() - start_time))
|
||||
self.tests[test][sim_type]["pass"]= test_run.passed
|
||||
if test_run.passed == "passed":
|
||||
self.passed_tests +=1
|
||||
elif test_run.passed == "failed":
|
||||
self.failed_tests +=1
|
||||
self.unknown_tests -=1
|
||||
self.update_reg_log()
|
||||
#TODO: add send mail here
|
||||
|
||||
|
||||
def update_reg_log(self):
|
||||
file_name=f"sim/{os.getenv('RUNTAG')}/runs.log"
|
||||
f = open(file_name, "w")
|
||||
f.write(f"{'Test':<25} {'status':<10} {'start':<15} {'end':<15} {'duration':<13} {'p/f':<5}\n")
|
||||
for test,sim_types in self.tests.items():
|
||||
for sim_type,status in sim_types.items():
|
||||
new_test_name= f"{sim_type}-{test}"
|
||||
f.write(f"{new_test_name:<25} {status['status']:<10} {status['starttime']:<15} {status['endtime']:<15} {status['duration']:<13} {status['pass']:<5}\n")
|
||||
f.write(f"\n\nTotal: ({self.passed_tests})passed ({self.failed_tests})failed ({self.unknown_tests})unknown ")
|
||||
f.close()
|
||||
|
||||
def write_command_log(self):
|
||||
file_name=f"sim/{os.getenv('RUNTAG')}/command.log"
|
||||
f = open(file_name, "w")
|
||||
f.write(f"{' '.join(sys.argv)}")
|
||||
f.close()
|
||||
|
||||
class main():
|
||||
def __init__(self,args) -> None:
|
||||
self.regression = args.regression
|
||||
self.test = args.test
|
||||
self.testlist = args.testlist
|
||||
self.type = args.sim
|
||||
self.tag = args.tag
|
||||
self.maxerr = args.maxerr
|
||||
self.check_valid_args()
|
||||
self.set_tag()
|
||||
self.def_env_vars()
|
||||
RunRegression(self.regression,self.test,self.type,self.testlist)
|
||||
|
||||
def check_valid_args(self):
|
||||
if all(v is None for v in [self.regression, self.test, self.testlist]):
|
||||
print ("Fatal: Should provide at least one of the following options regression, test or testlist for more info use --help")
|
||||
sys.exit()
|
||||
if not set(self.type).issubset(["RTL","GL","GL_SDF"]):
|
||||
print (f"Fatal: {self.type} isnt a correct type for -sim it should be one or combination of the following RTL, GL or GL_SDF")
|
||||
sys.exit()
|
||||
def set_tag(self):
|
||||
self.TAG = None # tag will be set in the main phase and other functions will use it
|
||||
if self.tag is not None:
|
||||
self.TAG = self.tag
|
||||
elif self.regression is not None:
|
||||
self.TAG = f'{self.regression}_{datetime.now().strftime("%H_%M_%S_%d_%m")}'
|
||||
else:
|
||||
self.TAG = f'run{random.randint(0,1000)}_{datetime.now().strftime("%H_%M_%S_%d_%m")}'
|
||||
Path(f"sim/{self.TAG}").mkdir(parents=True, exist_ok=True)
|
||||
print(f"Run tag: {self.TAG}")
|
||||
|
||||
def def_env_vars(self):
|
||||
cocotb_path = os.getcwd()
|
||||
repo_path = go_up(cocotb_path,4)
|
||||
os.environ["CARAVEL_ROOT"] = f"{repo_path}/caravel"
|
||||
os.environ["CARAVEL_VERILOG_PATH"] = f"{repo_path}/caravel/verilog"
|
||||
os.environ["MCW_ROOT"] = f"{repo_path}/caravel_mgmt_soc_litex/"
|
||||
os.environ["VERILOG_PATH"] = f"{os.getenv('MCW_ROOT')}/verilog"
|
||||
os.environ["CARAVEL_PATH"] = f"{os.getenv('CARAVEL_VERILOG_PATH')}"
|
||||
os.environ["USER_PROJECT_VERILOG"] = f"{repo_path}/verilog/"
|
||||
os.environ["GCC_PATH"] = "/ciic/tools/rv32/bin"
|
||||
os.environ["FIRMWARE_PATH"] = f"{os.getenv('MCW_ROOT')}/verilog/dv/firmware"
|
||||
os.environ["RUNTAG"] = f"{self.TAG}"
|
||||
print(self.maxerr)
|
||||
os.environ["ERRORMAX"] = f"{self.maxerr}"
|
||||
|
||||
|
||||
|
||||
import argparse
|
||||
parser = argparse.ArgumentParser(description='Run cocotb tests')
|
||||
parser.add_argument('-regression','-r', help='name of regression can found in tests.json')
|
||||
parser.add_argument('-test','-t', nargs='+' ,help='name of test if no --sim provided RTL will be run <takes list as input>')
|
||||
parser.add_argument('-sim', nargs='+' ,help='Simulation type to be run RTL,GL&GL_SDF provided only when run -test <takes list as input>')
|
||||
parser.add_argument('-testlist','-tl', help='path of testlist to be run ')
|
||||
parser.add_argument('-tag', help='provide tag of the run default would be regression name and if no regression is provided would be run_<random float>_<timestamp>_')
|
||||
parser.add_argument('-maxerr', help='max number of errors for every test before simulation breaks default = 3')
|
||||
args = parser.parse_args()
|
||||
if args.sim == None:
|
||||
args.sim= ["RTL"]
|
||||
print(f"regression:{args.regression}, test:{args.test}, testlist:{args.testlist} sim: {args.sim}")
|
||||
main(args)
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,160 @@
|
|||
{
|
||||
"Tests": {
|
||||
"_comment0" :"level is priorty of the test low is better, SW spcify if the test uses SW, RTL regressions run this test in RTL ",
|
||||
"_comment1" :"GL regressions run this test in gatelevel, GL_SDF regression run this test with SDF included"
|
||||
|
||||
,"bitbang_no_cpu_all_o" :{"level":0,
|
||||
"SW":false,
|
||||
"RTL":["setup","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":[],
|
||||
"GL_SDF":[],
|
||||
"description":"test disable CPU and control the wishbone to configure gpio[4:37] as mgmt output using bitbang and check them"}
|
||||
,"bitbang_cpu_all_o" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["setup","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["push_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["weekly","tape_out"],
|
||||
"description":"configure all gpios as mgmt output using bitbang and check them"}
|
||||
,"gpio_all_o" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["setup","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["push_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["weekly","tape_out"],
|
||||
"description":"configure all gpios as mgmt output using automatic approach firmware and check them"}
|
||||
,"gpio_all_i" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["setup","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["push_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["weekly","tape_out"],
|
||||
"description":"configure all gpios as mgmt output using automatic approach firmware and check them"}
|
||||
,"bitbang_cpu_all_10" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["setup","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["push_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["weekly","tape_out"],
|
||||
"description":"shift all the register with 10"}
|
||||
,"bitbang_cpu_all_01" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["setup","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["push_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["weekly","tape_out"],
|
||||
"description":"shift all the register with 01"}
|
||||
,"bitbang_cpu_all_1100" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["setup","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["push_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["weekly","tape_out"],
|
||||
"description":"shift all the register with 1100"}
|
||||
,"bitbang_cpu_all_0011" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["setup","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["push_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["weekly","tape_out"],
|
||||
"description":"shift all the register with 0011"}
|
||||
,"bitbang_no_cpu_all_i" :{"level":0,
|
||||
"SW":false,
|
||||
"RTL":["setup","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":[],
|
||||
"GL_SDF":[],
|
||||
"description":"test disable CPU and control the wishbone to configure gpio[0:31] as mgmt input using bitbang and check them"}
|
||||
,"bitbang_cpu_all_i" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["setup","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["push_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["weekly","tape_out"],
|
||||
"description":" configure gpio[0:37] as mgmt input using bitbang and check them"}
|
||||
|
||||
,"bitbang_spi" :{"level":0,
|
||||
"RTL":["setup","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["push_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["weekly","tape_out"],
|
||||
"SW":false,
|
||||
"description":"Same as bitbang_no_cpu_all but configure the gpio using the SPI not the firmware"}
|
||||
|
||||
,"hk_regs_wr_wb" :{"level":0,
|
||||
"SW":false,
|
||||
"RTL":["setup","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["push_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["weekly","tape_out"],
|
||||
"description":"write then read (the written value) from random housekeeping registers through the firmware but without using CPU, the SPI and system regs can't be read using firmware so the test only GPIO regs inside housekeeping "}
|
||||
,"hk_regs_wr_spi" :{"level":0,
|
||||
"SW":false,
|
||||
"RTL":["setup","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["push_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["weekly","tape_out"],
|
||||
"description":"write then read(the written value) from random housekeeping registers through the SPI housekeeping"}
|
||||
,"hk_regs_rst_spi" :{"level":0,
|
||||
"SW":false,
|
||||
"RTL":["setup","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["push_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["weekly","tape_out"],
|
||||
"description":"check reset value of house keeping registers by reading them trough the spi housekeeping"}
|
||||
,"helloWorld" :{"level":3,
|
||||
"SW":false,
|
||||
"RTL":[],
|
||||
"GL":[],
|
||||
"GL_SDF":[],
|
||||
"description":"hello world test"}
|
||||
|
||||
,"cpu_stress" :{"level":2,
|
||||
"SW":true,
|
||||
"RTL":["nightly","weekly","tape_out"],
|
||||
"GL":["nightly","weekly","tape_out"],
|
||||
"GL_SDF":["weekly","tape_out"],
|
||||
"description":"stress the cpu with heavy processing"}
|
||||
,"mem_stress" :{"level":2,
|
||||
"SW":true,
|
||||
"RTL":["nightly","weekly","tape_out"],
|
||||
"GL":["nightly","weekly","tape_out"],
|
||||
"GL_SDF":["weekly","tape_out"],
|
||||
"description":"Memory stress tests write and read from 800 bytes 200 words and 400 half words"}
|
||||
,"IRQ_external" :{"level":2,
|
||||
"SW":true,
|
||||
"RTL":["setup","nightly","weekly","tape_out"],
|
||||
"GL":["nightly","weekly","tape_out"],
|
||||
"GL_SDF":["weekly","tape_out"],
|
||||
"description":"test external interrupt by mprj 7"}
|
||||
,"IRQ_timer" :{"level":2,
|
||||
"SW":true,
|
||||
"RTL":["setup","nightly","weekly","tape_out"],
|
||||
"GL":["nightly","weekly","tape_out"],
|
||||
"GL_SDF":["weekly","tape_out"],
|
||||
"description":"test timer0 interrupt"}
|
||||
,"IRQ_uart" :{"level":2,
|
||||
"SW":true,
|
||||
"RTL":["setup","nightly","weekly","tape_out"],
|
||||
"GL":["nightly","weekly","tape_out"],
|
||||
"GL_SDF":["weekly","tape_out"],
|
||||
"description":"test timer0 interrupt"}
|
||||
,"mgmt_gpio_out" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["setup","nightly","weekly","tape_out"],
|
||||
"GL":["nightly","weekly","tape_out"],
|
||||
"GL_SDF":["weekly","tape_out"],
|
||||
"description":"tests blinking of mgmt gpio bit as an output"}
|
||||
,"mgmt_gpio_in" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["setup","nightly","weekly","tape_out"],
|
||||
"GL":["nightly","weekly","tape_out"],
|
||||
"GL_SDF":["weekly","tape_out"],
|
||||
"description":"tests blinking of mgmt gpio bit as an output"}
|
||||
,"timer0_oneshot" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["setup","nightly","weekly","tape_out"],
|
||||
"GL":["nightly","weekly","tape_out"],
|
||||
"GL_SDF":["weekly","tape_out"],
|
||||
"description":"check timer0 oneshot mode"}
|
||||
,"timer0_periodic" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["setup","nightly","weekly","tape_out"],
|
||||
"GL":["nightly","weekly","tape_out"],
|
||||
"GL_SDF":["weekly","tape_out"],
|
||||
"description":"check timer0 periodic mode"}
|
||||
,"uart_tx" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["setup","nightly","weekly","tape_out"],
|
||||
"GL":["nightly","weekly","tape_out"],
|
||||
"GL_SDF":["weekly","tape_out"],
|
||||
"description":"test uart transmit"}
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,62 @@
|
|||
#include <defs.h>
|
||||
#include <stub.c>
|
||||
#include "bitbang_functions.c"
|
||||
|
||||
void main(){
|
||||
unsigned int i, j, k;
|
||||
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
|
||||
reg_debug_1 = 0x0;
|
||||
reg_debug_2 = 0x0;
|
||||
|
||||
reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_7 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_5 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_4 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_3 = 0x1803 ;
|
||||
reg_mprj_io_2 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
|
||||
// bitbang
|
||||
for(int i =0;i<19*13;i++){
|
||||
clock00();
|
||||
clock00();
|
||||
clock11();
|
||||
clock11();
|
||||
}
|
||||
reg_debug_1 = 0xFF; // finish configuration
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,60 @@
|
|||
#include <defs.h>
|
||||
#include <stub.c>
|
||||
#include "bitbang_functions.c"
|
||||
|
||||
void main(){
|
||||
unsigned int i, j, k;
|
||||
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
|
||||
reg_debug_1 = 0x0;
|
||||
reg_debug_2 = 0x0;
|
||||
|
||||
reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_7 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_5 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_4 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_3 = 0x1803 ;
|
||||
reg_mprj_io_2 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
|
||||
// bitbang
|
||||
for(int i =0;i<19*13;i++){
|
||||
clock00();
|
||||
clock11();
|
||||
}
|
||||
reg_debug_1 = 0xFF; // finish configuration
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,60 @@
|
|||
#include <defs.h>
|
||||
#include <stub.c>
|
||||
#include "bitbang_functions.c"
|
||||
|
||||
void main(){
|
||||
unsigned int i, j, k;
|
||||
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
|
||||
reg_debug_1 = 0x0;
|
||||
reg_debug_2 = 0x0;
|
||||
|
||||
reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_7 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_5 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_4 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_3 = 0x1803 ;
|
||||
reg_mprj_io_2 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
|
||||
// bitbang
|
||||
for(int i =0;i<19*13;i++){
|
||||
clock11();
|
||||
clock00();
|
||||
}
|
||||
reg_debug_1 = 0xFF; // finish configuration
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,62 @@
|
|||
#include <defs.h>
|
||||
#include <stub.c>
|
||||
#include "bitbang_functions.c"
|
||||
|
||||
void main(){
|
||||
unsigned int i, j, k;
|
||||
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
|
||||
reg_debug_1 = 0x0;
|
||||
reg_debug_2 = 0x0;
|
||||
|
||||
reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_7 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_5 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_4 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_3 = 0x1803 ;
|
||||
reg_mprj_io_2 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
|
||||
// bitbang
|
||||
for(int i =0;i<19*13;i++){
|
||||
clock11();
|
||||
clock11();
|
||||
clock00();
|
||||
clock00();
|
||||
}
|
||||
reg_debug_1 = 0xFF; // finish configuration
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,83 @@
|
|||
#include <defs.h>
|
||||
#include <stub.c>
|
||||
#include "bitbang_functions.c"
|
||||
|
||||
void main(){
|
||||
unsigned int i, j, k;
|
||||
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
|
||||
reg_debug_1 = 0x0;
|
||||
reg_debug_2 = 0x0;
|
||||
|
||||
reg_mprj_io_37 = 0x1803;
|
||||
reg_mprj_io_36 = 0x1803;
|
||||
reg_mprj_io_35 = 0x1803;
|
||||
reg_mprj_io_34 = 0x1803;
|
||||
reg_mprj_io_33 = 0x1803;
|
||||
reg_mprj_io_32 = 0x1803;
|
||||
reg_mprj_io_31 = 0x1803;
|
||||
reg_mprj_io_30 = 0x1803;
|
||||
reg_mprj_io_29 = 0x1803;
|
||||
reg_mprj_io_28 = 0x1803;
|
||||
reg_mprj_io_27 = 0x1803;
|
||||
reg_mprj_io_26 = 0x1803;
|
||||
reg_mprj_io_25 = 0x1803;
|
||||
reg_mprj_io_24 = 0x1803;
|
||||
reg_mprj_io_23 = 0x1803;
|
||||
reg_mprj_io_22 = 0x1803;
|
||||
reg_mprj_io_21 = 0x1803;
|
||||
reg_mprj_io_20 = 0x1803;
|
||||
reg_mprj_io_19 = 0x1803;
|
||||
reg_mprj_io_18 = 0x1803;
|
||||
reg_mprj_io_17 = 0x1803;
|
||||
reg_mprj_io_16 = 0x1803;
|
||||
reg_mprj_io_15 = 0x1803;
|
||||
reg_mprj_io_14 = 0x1803;
|
||||
reg_mprj_io_13 = 0x1803;
|
||||
reg_mprj_io_12 = 0x1803;
|
||||
reg_mprj_io_11 = 0x1803;
|
||||
reg_mprj_io_10 = 0x1803;
|
||||
reg_mprj_io_9 = 0x1803;
|
||||
reg_mprj_io_8 = 0x1803;
|
||||
reg_mprj_io_7 = 0x1803;
|
||||
reg_mprj_io_6 = 0x1803;
|
||||
reg_mprj_io_5 = 0x1803;
|
||||
reg_mprj_io_4 = 0x1803;
|
||||
reg_mprj_io_3 = 0x1803;
|
||||
reg_mprj_io_2 = 0x1803;
|
||||
reg_mprj_io_1 = 0x1803;
|
||||
reg_mprj_io_0 = 0x1803;
|
||||
reg_mprj_io_0 = 0x1803;
|
||||
|
||||
// bitbang
|
||||
//Configure all as input except reg_mprj_io_3
|
||||
clock_in_right_i_left_i_standard(0); // 18 and 19
|
||||
clock_in_right_i_left_i_standard(0); // 17 and 20
|
||||
clock_in_right_i_left_i_standard(0); // 16 and 21
|
||||
clock_in_right_i_left_i_standard(0); // 15 and 22
|
||||
clock_in_right_i_left_i_standard(0); // 14 and 23
|
||||
clock_in_right_i_left_i_standard(0); // 13 and 24
|
||||
clock_in_right_i_left_i_standard(0); // 12 and 25
|
||||
clock_in_right_i_left_i_standard(0); // 11 and 26
|
||||
clock_in_right_i_left_i_standard(0); // 10 and 27
|
||||
clock_in_right_i_left_i_standard(0); // 9 and 28
|
||||
clock_in_right_i_left_i_standard(0); // 8 and 29
|
||||
clock_in_right_i_left_i_standard(0); // 7 and 30
|
||||
clock_in_right_i_left_i_standard(0); // 6 and 31
|
||||
clock_in_right_i_left_i_standard(0); // 5 and 32
|
||||
clock_in_right_i_left_i_standard(0); // 4 and 33
|
||||
clock_in_right_i_left_i_standard(0); // 3 and 34
|
||||
clock_in_right_i_left_i_standard(0); // 2 and 35
|
||||
clock_in_right_i_left_i_standard(0); // 1 and 36
|
||||
clock_in_right_i_left_i_standard(0); // 0 and 37
|
||||
load(); // load
|
||||
reg_debug_1 = 0XAA; // configuration done wait environment to send 0x8F66FD7B to reg_mprj_datal
|
||||
while (reg_mprj_datal != 0x8F66FD7B);
|
||||
reg_debug_1 = 0XBB; // configuration done wait environment to send 0xFFA88C5A to reg_mprj_datal
|
||||
while (reg_mprj_datal != 0xFFA88C5A);
|
||||
reg_debug_1 = 0XCC; // configuration done wait environment to send 0xC9536346 to reg_mprj_datal
|
||||
while (reg_mprj_datal != 0xC9536346);
|
||||
|
||||
reg_debug_2 = 0xFF;
|
||||
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,99 @@
|
|||
#include <defs.h>
|
||||
#include <stub.c>
|
||||
#include "bitbang_functions.c"
|
||||
|
||||
void main(){
|
||||
unsigned int i, j, k;
|
||||
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
|
||||
reg_debug_1 = 0x0;
|
||||
reg_debug_2 = 0x0;
|
||||
|
||||
reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_7 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_5 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_4 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_3 = 0x1803 ;
|
||||
reg_mprj_io_2 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
|
||||
// bitbang
|
||||
// Configure all as output except reg_mprj_io_3
|
||||
clock_in_right_o_left_o_standard(0); // 18 and 19
|
||||
clock_in_right_o_left_o_standard(0); // 17 and 20
|
||||
clock_in_right_o_left_o_standard(0); // 16 and 21
|
||||
clock_in_right_o_left_o_standard(0); // 15 and 22
|
||||
clock_in_right_o_left_o_standard(0); // 14 and 23
|
||||
clock_in_right_o_left_o_standard(0); // 13 and 24
|
||||
clock_in_right_o_left_o_standard(0); // 12 and 25
|
||||
clock_in_right_o_left_o_standard(0); // 11 and 26
|
||||
clock_in_right_o_left_o_standard(0); // 10 and 27
|
||||
clock_in_right_o_left_o_standard(0); // 9 and 28
|
||||
clock_in_right_o_left_o_standard(0); // 8 and 29
|
||||
clock_in_right_o_left_o_standard(0); // 7 and 30
|
||||
clock_in_right_o_left_o_standard(0); // 6 and 31
|
||||
clock_in_right_o_left_o_standard(0); // 5 and 32
|
||||
clock_in_right_o_left_o_standard(0); // 4 and 33
|
||||
clock_in_right_o_left_i_standard(0); // 3 and 34
|
||||
clock_in_right_o_left_o_standard(0); // 2 and 35
|
||||
clock_in_right_o_left_o_standard(0); // 1 and 36
|
||||
clock_in_right_o_left_o_standard(0); // 0 and 37
|
||||
load();
|
||||
reg_debug_1 = 0xFF; // finish configuration
|
||||
reg_mprj_datal = 0x0;
|
||||
reg_mprj_datah = 0x0;
|
||||
i = 0x20;
|
||||
for (j = 0; j < 5; j++) {
|
||||
reg_mprj_datah = i;
|
||||
reg_debug_2 = 37-j;
|
||||
reg_mprj_datah = 0x00000000;
|
||||
reg_debug_2 = 0;
|
||||
i >>=1;
|
||||
i |= 0x20;
|
||||
}
|
||||
i = 0x80000000;
|
||||
for (j = 0; j < 32; j++) {
|
||||
reg_mprj_datah = 0x3f;
|
||||
reg_mprj_datal = i;
|
||||
reg_debug_2 = 32-j;
|
||||
reg_mprj_datah = 0x00;
|
||||
reg_mprj_datal = 0x00000000;
|
||||
reg_debug_2 = 0;
|
||||
i >>=1;
|
||||
i |= 0x80000000;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,325 @@
|
|||
|
||||
|
||||
void clock11()
|
||||
{
|
||||
reg_mprj_xfer = 0x66; reg_mprj_xfer = 0x76;
|
||||
}
|
||||
|
||||
void clock00()
|
||||
{
|
||||
reg_mprj_xfer = 0x06; reg_mprj_xfer = 0x16;
|
||||
}
|
||||
|
||||
// --------------------------------------------------------
|
||||
|
||||
void clock10()
|
||||
{
|
||||
reg_mprj_xfer = 0x46; reg_mprj_xfer = 0x56;
|
||||
}
|
||||
|
||||
void clock01()
|
||||
{
|
||||
reg_mprj_xfer = 0x26; reg_mprj_xfer = 0x36;
|
||||
}
|
||||
|
||||
// --------------------------------------------------------
|
||||
// Load registers
|
||||
// --------------------------------------------------------
|
||||
|
||||
void load()
|
||||
{
|
||||
reg_mprj_xfer = 0x06;
|
||||
reg_mprj_xfer = 0x0e; reg_mprj_xfer = 0x06; // Apply load
|
||||
}
|
||||
|
||||
// --------------------------------------------------------
|
||||
// Enable bit-bang mode and clear registers
|
||||
// --------------------------------------------------------
|
||||
|
||||
void clear_registers()
|
||||
{
|
||||
reg_mprj_xfer = 0x06; // Enable bit-bang mode
|
||||
reg_mprj_xfer = 0x04; reg_mprj_xfer = 0x06; // Pulse reset
|
||||
}
|
||||
|
||||
// --------------------------------------------------------
|
||||
// Clock in an input + output configuration. The value
|
||||
// passed in "ddhold" is the number of data-dependent hold
|
||||
// violations up to this point.
|
||||
// --------------------------------------------------------
|
||||
|
||||
/* Clock in data on the left side. Assume standard hold
|
||||
* violation, so clock in12 times and assume that the
|
||||
* next data to be clocked will start with "1", enforced
|
||||
* by the code.
|
||||
*
|
||||
* Left side = GPIOs 37 to19
|
||||
*/
|
||||
|
||||
void clock_in_left_short(uint32_t ddhold)
|
||||
{
|
||||
uint32_t count;
|
||||
uint32_t holds = ddhold;
|
||||
|
||||
clock10();
|
||||
clock10();
|
||||
|
||||
for (count = 0; count < 9; count++) {
|
||||
if (holds != 0) {
|
||||
clock10();
|
||||
holds--;
|
||||
}
|
||||
else
|
||||
clock00();
|
||||
}
|
||||
|
||||
clock00();
|
||||
}
|
||||
|
||||
/* Clock in data on the right side. Assume standard hold
|
||||
* violation, so clock in12 times and assume that the
|
||||
* next data to be clocked will start with "1", enforced
|
||||
* by the code.
|
||||
*
|
||||
* Right side = GPIOs 0 to18
|
||||
*/
|
||||
|
||||
void clock_in_right_short(uint32_t ddhold)
|
||||
{
|
||||
uint32_t count;
|
||||
uint32_t holds = ddhold;
|
||||
|
||||
clock01();
|
||||
clock01();
|
||||
|
||||
for (count = 0; count < 9; count++) {
|
||||
if (holds != 0) {
|
||||
clock01();
|
||||
holds--;
|
||||
}
|
||||
else
|
||||
clock00();
|
||||
}
|
||||
|
||||
clock00();
|
||||
}
|
||||
|
||||
/* Clock in data on the left side. Clock the normal13 times,
|
||||
* which is correct for no hold violation or for a data-
|
||||
* dependent hold violation (for the latter, ddhold must be
|
||||
* incremented before calling the subroutine).
|
||||
*
|
||||
* Left side = GPIOs 37 to19
|
||||
*/
|
||||
|
||||
void clock_in_left_standard(uint32_t ddhold){
|
||||
uint32_t count;
|
||||
uint32_t holds = ddhold;
|
||||
|
||||
clock10();
|
||||
clock10();
|
||||
|
||||
for (count = 0; count < 7; count++) {
|
||||
if (holds != 0) {
|
||||
clock10();
|
||||
holds--;
|
||||
}
|
||||
else
|
||||
clock00();
|
||||
}
|
||||
|
||||
clock10();
|
||||
clock00();
|
||||
clock00();
|
||||
clock10();
|
||||
}
|
||||
void clock_in_right_o_left_o_standard(uint32_t ddhold){
|
||||
uint32_t count;
|
||||
uint32_t holds = ddhold;
|
||||
|
||||
clock11();
|
||||
clock11();
|
||||
|
||||
for (count = 0; count < 7; count++) {
|
||||
if (holds != 0) {
|
||||
clock11();
|
||||
holds--;
|
||||
}
|
||||
else
|
||||
clock00();
|
||||
}
|
||||
|
||||
clock11();
|
||||
clock00();
|
||||
clock00();
|
||||
clock11();
|
||||
}
|
||||
|
||||
void clock_in_right_o_left_i_standard(uint32_t ddhold){
|
||||
uint32_t count;
|
||||
uint32_t holds = ddhold;
|
||||
|
||||
clock11();
|
||||
clock11();
|
||||
|
||||
for (count = 0; count < 7; count++) {
|
||||
if (holds != 0) {
|
||||
clock11();
|
||||
holds--;
|
||||
}
|
||||
else
|
||||
clock00();
|
||||
}
|
||||
|
||||
clock10();
|
||||
clock00();
|
||||
clock01();
|
||||
clock11();
|
||||
}
|
||||
|
||||
void clock_in_right_i_left_o_standard(uint32_t ddhold){
|
||||
uint32_t count;
|
||||
uint32_t holds = ddhold;
|
||||
|
||||
clock11();
|
||||
clock11();
|
||||
|
||||
for (count = 0; count < 7; count++) {
|
||||
if (holds != 0) {
|
||||
clock11();
|
||||
holds--;
|
||||
}
|
||||
else
|
||||
clock00();
|
||||
}
|
||||
|
||||
clock01();
|
||||
clock00();
|
||||
clock10();
|
||||
clock11();
|
||||
}
|
||||
|
||||
void clock_in_right_i_left_i_standard(uint32_t ddhold){
|
||||
uint32_t count;
|
||||
uint32_t holds = ddhold;
|
||||
|
||||
clock11();
|
||||
clock11();
|
||||
|
||||
for (count = 0; count < 7; count++) {
|
||||
if (holds != 0) {
|
||||
clock11();
|
||||
holds--;
|
||||
}
|
||||
else
|
||||
clock00();
|
||||
}
|
||||
|
||||
clock00();
|
||||
clock00();
|
||||
clock11();
|
||||
clock11();
|
||||
}
|
||||
|
||||
/* Clock in data on the right side. Clock the normal13 times,
|
||||
* which is correct for no hold violation or for a data-
|
||||
* dependent hold violation (for the latter, ddhold must be
|
||||
* incremented before calling the subroutine).
|
||||
*
|
||||
* Right side = GPIOs 0 to18
|
||||
*/
|
||||
|
||||
void clock_in_right_standard(uint32_t ddhold){
|
||||
uint32_t count;
|
||||
uint32_t holds = ddhold;
|
||||
|
||||
clock11();
|
||||
clock11();
|
||||
|
||||
for (count = 0; count < 7; count++) {
|
||||
if (holds != 0) {
|
||||
clock01();
|
||||
holds--;
|
||||
}
|
||||
else
|
||||
clock00();
|
||||
}
|
||||
|
||||
clock10();
|
||||
clock00();
|
||||
clock01();
|
||||
clock11();
|
||||
}
|
||||
|
||||
void clock_in_right_i_left_io_standard(uint32_t ddhold){
|
||||
uint32_t count;
|
||||
uint32_t holds = ddhold;
|
||||
|
||||
clock11();
|
||||
clock11();
|
||||
|
||||
for (count = 0; count < 7; count++) {
|
||||
if (holds != 0) {
|
||||
clock11();
|
||||
holds--;
|
||||
}
|
||||
else
|
||||
clock00();
|
||||
}
|
||||
|
||||
clock01();
|
||||
clock00();
|
||||
clock11();
|
||||
clock11();
|
||||
}
|
||||
// --------------------------------------------------------
|
||||
// Clock in data for GPIO 0 and 37 (fixed) and apply load.
|
||||
// --------------------------------------------------------
|
||||
|
||||
void clock_in_end(){
|
||||
// Right side: GPIO 0 configured disabled
|
||||
// Left side: GPIO 37 configured as input
|
||||
clock11();
|
||||
clock10();
|
||||
clock00();
|
||||
clock00();
|
||||
clock00();
|
||||
clock00();
|
||||
clock00();
|
||||
clock00();
|
||||
clock00();
|
||||
clock01();
|
||||
clock00();
|
||||
clock11();
|
||||
clock11();
|
||||
|
||||
load();
|
||||
}
|
||||
|
||||
// --------------------------------------------------------
|
||||
// Same as above, except that GPIO is configured as an
|
||||
// output for a quick sanity check.
|
||||
// --------------------------------------------------------
|
||||
|
||||
void clock_in_end_output()
|
||||
{
|
||||
// Right side: GPIO 0 configured disabled
|
||||
// Left side: GPIO 37 configured as output
|
||||
clock11();
|
||||
clock10();
|
||||
clock00();
|
||||
clock00();
|
||||
clock00();
|
||||
clock00();
|
||||
clock00();
|
||||
clock00();
|
||||
clock00();
|
||||
clock01();
|
||||
clock00();
|
||||
clock01();
|
||||
clock11();
|
||||
|
||||
load();
|
||||
|
||||
reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
}
|
||||
|
|
@ -0,0 +1,355 @@
|
|||
from defsParser import Regs
|
||||
|
||||
reg = Regs()
|
||||
|
||||
|
||||
"""
|
||||
reg_mprj_xfer contain
|
||||
bit 0 : busy
|
||||
bit 1 : bitbang enable
|
||||
bit 2 : bitbang reset active low
|
||||
bit 3 : bitbang load registers
|
||||
bit 4 : bitbang clock
|
||||
bit 5 : serial data 1
|
||||
bit 6 : serial data 2
|
||||
"""
|
||||
|
||||
"""shift the 2 registers with 2 ones"""
|
||||
async def clock11(cpu):
|
||||
reg_mprj_xfer_addr = reg.get_addr('reg_mprj_xfer')
|
||||
await cpu.drive_data2address(reg_mprj_xfer_addr,0x66) # 0110_0110
|
||||
await cpu.drive_data2address(reg_mprj_xfer_addr,0x76) # 0111_0110
|
||||
|
||||
"""shift the 2 registers with 2 zeros"""
|
||||
async def clock00(cpu):
|
||||
reg_mprj_xfer_addr = reg.get_addr('reg_mprj_xfer')
|
||||
await cpu.drive_data2address(reg_mprj_xfer_addr,0x06) # 0000_0110
|
||||
await cpu.drive_data2address(reg_mprj_xfer_addr,0x16) # 0001_0110
|
||||
|
||||
"""shift the 2 registers with 1 in the left side and zero in right side"""
|
||||
async def clock01(cpu):
|
||||
reg_mprj_xfer_addr = reg.get_addr('reg_mprj_xfer')
|
||||
await cpu.drive_data2address(reg_mprj_xfer_addr,0x26) # 0010_0110
|
||||
await cpu.drive_data2address(reg_mprj_xfer_addr,0x36) # 0011_0110
|
||||
|
||||
"""shift the 2 registers with 1 in the left side and zero in right side"""
|
||||
async def clock10(cpu):
|
||||
reg_mprj_xfer_addr = reg.get_addr('reg_mprj_xfer')
|
||||
await cpu.drive_data2address(reg_mprj_xfer_addr,0x46) # 0100_0110
|
||||
await cpu.drive_data2address(reg_mprj_xfer_addr,0x56) # 0101_0110
|
||||
|
||||
"""enable the serial loader bit to load registers"""
|
||||
async def load(cpu):
|
||||
reg_mprj_xfer_addr = reg.get_addr('reg_mprj_xfer')
|
||||
await cpu.drive_data2address(reg_mprj_xfer_addr,0x06) # enable bit bang
|
||||
await cpu.drive_data2address(reg_mprj_xfer_addr,0x0e) # enable loader
|
||||
await cpu.drive_data2address(reg_mprj_xfer_addr,0x06) # enable bit bang
|
||||
|
||||
"""Enable bit-bang mode and clear registers"""
|
||||
async def clear_registers(cpu):
|
||||
reg_mprj_xfer_addr = reg.get_addr('reg_mprj_xfer')
|
||||
await cpu.drive_data2address(reg_mprj_xfer_addr,0x06) # enable bit bang
|
||||
await cpu.drive_data2address(reg_mprj_xfer_addr,0x04) # reset
|
||||
await cpu.drive_data2address(reg_mprj_xfer_addr,0x06) # enable bit bang
|
||||
|
||||
"""
|
||||
--------------------------------------------------------
|
||||
Clock in an input + output configuration. The value
|
||||
passed in "ddhold" is the number of data-dependent hold
|
||||
violations up to this point.
|
||||
--------------------------------------------------------
|
||||
|
||||
* Clock in data on the left side. Assume standard hold
|
||||
* violation, so clock in 12 times and assume that the
|
||||
* next data to be clocked will start with "1", enforced
|
||||
* by the code.
|
||||
*
|
||||
* Left side = GPIOs 37 to 19
|
||||
|
||||
"""
|
||||
async def clock_in_left_short(cpu,ddhold):
|
||||
await clock10(cpu)
|
||||
await clock10(cpu)
|
||||
|
||||
for i in range(9):
|
||||
if ddhold != 0:
|
||||
await clock10(cpu)
|
||||
ddhold -=1
|
||||
else:
|
||||
await clock00(cpu)
|
||||
|
||||
await clock00(cpu)
|
||||
|
||||
async def clock_in_right_short(cpu,ddhold):
|
||||
await clock01(cpu)
|
||||
await clock01(cpu)
|
||||
|
||||
for i in range(9):
|
||||
if ddhold != 0:
|
||||
await clock01(cpu)
|
||||
ddhold -=1
|
||||
else:
|
||||
await clock00(cpu)
|
||||
|
||||
await clock00(cpu)
|
||||
|
||||
async def clock_in_left_standard(cpu,ddhold):
|
||||
await clock10(cpu)
|
||||
await clock10(cpu)
|
||||
|
||||
for i in range(7):
|
||||
if ddhold != 0:
|
||||
await clock10(cpu)
|
||||
ddhold -=1
|
||||
else:
|
||||
await clock00(cpu)
|
||||
|
||||
await clock10(cpu)
|
||||
await clock00(cpu)
|
||||
await clock00(cpu)
|
||||
await clock10(cpu)
|
||||
|
||||
"""right output left input"""
|
||||
async def clock_in_right_o_left_i_standard(cpu,ddhold):
|
||||
await clock11(cpu)
|
||||
await clock11(cpu)
|
||||
|
||||
for i in range(7):
|
||||
if ddhold != 0:
|
||||
await clock01(cpu)
|
||||
ddhold -=1
|
||||
else:
|
||||
await clock00(cpu)
|
||||
|
||||
await clock10(cpu)
|
||||
await clock00(cpu)
|
||||
await clock01(cpu)
|
||||
await clock11(cpu)
|
||||
|
||||
"""right input left output"""
|
||||
async def clock_in_right_i_left_o_standard(cpu,ddhold):
|
||||
await clock11(cpu)
|
||||
await clock11(cpu)
|
||||
|
||||
for i in range(7):
|
||||
if ddhold != 0:
|
||||
await clock10(cpu)
|
||||
ddhold -=1
|
||||
else:
|
||||
await clock00(cpu)
|
||||
|
||||
await clock01(cpu)
|
||||
await clock00(cpu)
|
||||
await clock10(cpu)
|
||||
await clock11(cpu)
|
||||
|
||||
"""right input left output"""
|
||||
async def clock_in_right_i_left_i_standard(cpu,ddhold):
|
||||
await clock11(cpu)
|
||||
await clock11(cpu)
|
||||
|
||||
for i in range(7):
|
||||
if ddhold != 0:
|
||||
await clock01(cpu)
|
||||
ddhold -=1
|
||||
else:
|
||||
await clock00(cpu)
|
||||
|
||||
await clock00(cpu)
|
||||
await clock00(cpu)
|
||||
await clock11(cpu)
|
||||
await clock11(cpu)
|
||||
|
||||
"""right output left output"""
|
||||
async def clock_in_right_o_left_o_standard(cpu,ddhold):
|
||||
await clock11(cpu)
|
||||
await clock11(cpu)
|
||||
|
||||
for i in range(7):
|
||||
if ddhold != 0:
|
||||
await clock01(cpu)
|
||||
ddhold -=1
|
||||
else:
|
||||
await clock00(cpu)
|
||||
|
||||
await clock11(cpu)
|
||||
await clock00(cpu)
|
||||
await clock00(cpu)
|
||||
await clock11(cpu)
|
||||
|
||||
async def clock_in_end_output(cpu):
|
||||
# Right side: GPIO 0 configured disabled
|
||||
# /Left side: GPIO 37 configured as output
|
||||
await clock11(cpu)
|
||||
await clock11(cpu)
|
||||
await clock00(cpu)
|
||||
await clock00(cpu)
|
||||
await clock00(cpu)
|
||||
await clock00(cpu)
|
||||
await clock00(cpu)
|
||||
await clock00(cpu)
|
||||
await clock00(cpu)
|
||||
await clock00(cpu)
|
||||
await clock00(cpu)
|
||||
await clock01(cpu)
|
||||
await clock11(cpu)
|
||||
await load(cpu)
|
||||
reg_mprj_io_37_addr = reg.get_addr('reg_mprj_io_37')
|
||||
await cpu.drive_data2address(reg_mprj_io_37_addr,0x1809)
|
||||
|
||||
|
||||
async def clock11_spi(caravelEnv):
|
||||
|
||||
await caravelEnv.enable_csb()
|
||||
await caravelEnv.hk_write_byte(0x80) # Write stream command
|
||||
await caravelEnv.hk_write_byte(0x13) # Address (register 19 = GPIO bit-bang control)
|
||||
await caravelEnv.hk_write_byte(0x66) # Data = 0x01 (enable bit-bang mode)
|
||||
await caravelEnv.disable_csb()
|
||||
|
||||
await caravelEnv.enable_csb()
|
||||
await caravelEnv.hk_write_byte(0x80) # Write stream command
|
||||
await caravelEnv.hk_write_byte(0x13) # Address (register 19 = GPIO bit-bang control)
|
||||
await caravelEnv.hk_write_byte(0x76) # 11
|
||||
await caravelEnv.disable_csb()
|
||||
|
||||
async def clock00_spi(caravelEnv):
|
||||
|
||||
await caravelEnv.enable_csb()
|
||||
await caravelEnv.hk_write_byte(0x80) # Write stream command
|
||||
await caravelEnv.hk_write_byte(0x13) # Address (register 19 = GPIO bit-bang control)
|
||||
await caravelEnv.hk_write_byte(0x06) # Data = 0x01 (enable bit-bang mode)
|
||||
await caravelEnv.disable_csb()
|
||||
|
||||
await caravelEnv.enable_csb()
|
||||
await caravelEnv.hk_write_byte(0x80) # Write stream command
|
||||
await caravelEnv.hk_write_byte(0x13) # Address (register 19 = GPIO bit-bang control)
|
||||
await caravelEnv.hk_write_byte(0x16) # 00
|
||||
await caravelEnv.disable_csb()
|
||||
|
||||
async def clock01_spi(caravelEnv):
|
||||
|
||||
await caravelEnv.enable_csb()
|
||||
await caravelEnv.hk_write_byte(0x80) # Write stream command
|
||||
await caravelEnv.hk_write_byte(0x13) # Address (register 19 = GPIO bit-bang control)
|
||||
await caravelEnv.hk_write_byte(0x26) # Data = 0x01 (enable bit-bang mode)
|
||||
await caravelEnv.disable_csb()
|
||||
|
||||
await caravelEnv.enable_csb()
|
||||
await caravelEnv.hk_write_byte(0x80) # Write stream command
|
||||
await caravelEnv.hk_write_byte(0x13) # Address (register 19 = GPIO bit-bang control)
|
||||
await caravelEnv.hk_write_byte(0x36) # 01
|
||||
await caravelEnv.disable_csb()
|
||||
|
||||
async def clock10_spi(caravelEnv):
|
||||
|
||||
await caravelEnv.enable_csb()
|
||||
await caravelEnv.hk_write_byte(0x80) # Write stream command
|
||||
await caravelEnv.hk_write_byte(0x13) # Address (register 19 = GPIO bit-bang control)
|
||||
await caravelEnv.hk_write_byte(0x46) # Data = 0x01 (enable bit-bang mode)
|
||||
await caravelEnv.disable_csb()
|
||||
|
||||
await caravelEnv.enable_csb()
|
||||
await caravelEnv.hk_write_byte(0x80) # Write stream command
|
||||
await caravelEnv.hk_write_byte(0x13) # Address (register 19 = GPIO bit-bang control)
|
||||
await caravelEnv.hk_write_byte(0x56) # 10
|
||||
await caravelEnv.disable_csb()
|
||||
|
||||
async def load_spi(caravelEnv):
|
||||
|
||||
await caravelEnv.enable_csb()
|
||||
await caravelEnv.hk_write_byte(0x80) # Write stream command
|
||||
await caravelEnv.hk_write_byte(0x13) # Address (register 19 = GPIO bit-bang control)
|
||||
await caravelEnv.hk_write_byte(0x0e) # load enable
|
||||
await caravelEnv.disable_csb()
|
||||
|
||||
await caravelEnv.enable_csb()
|
||||
await caravelEnv.hk_write_byte(0x80) # Write stream command
|
||||
await caravelEnv.hk_write_byte(0x13) # Address (register 19 = GPIO bit-bang control)
|
||||
await caravelEnv.hk_write_byte(0x16) # 00
|
||||
await caravelEnv.disable_csb()
|
||||
|
||||
"""right output left input"""
|
||||
async def clock_in_right_o_left_i_standard_spi(caravelEnv,ddhold):
|
||||
await clock11_spi(caravelEnv)
|
||||
await clock11_spi(caravelEnv)
|
||||
|
||||
for i in range(7):
|
||||
if ddhold != 0:
|
||||
await clock01_spi(caravelEnv)
|
||||
ddhold -=1
|
||||
else:
|
||||
await clock00_spi(caravelEnv)
|
||||
|
||||
await clock10_spi(caravelEnv)
|
||||
await clock00_spi(caravelEnv)
|
||||
await clock01_spi(caravelEnv)
|
||||
await clock11_spi(caravelEnv)
|
||||
|
||||
"""right input left output"""
|
||||
async def clock_in_right_i_left_o_standard_spi(caravelEnv,ddhold):
|
||||
await clock11_spi(caravelEnv)
|
||||
await clock11_spi(caravelEnv)
|
||||
|
||||
for i in range(7):
|
||||
if ddhold != 0:
|
||||
await clock10_spi(caravelEnv)
|
||||
ddhold -=1
|
||||
else:
|
||||
await clock00_spi(caravelEnv)
|
||||
|
||||
await clock01_spi(caravelEnv)
|
||||
await clock00_spi(caravelEnv)
|
||||
await clock10_spi(caravelEnv)
|
||||
await clock11_spi(caravelEnv)
|
||||
|
||||
"""right input left output"""
|
||||
async def clock_in_right_i_left_i_standard_spi(caravelEnv,ddhold):
|
||||
await clock11_spi(caravelEnv)
|
||||
await clock11_spi(caravelEnv)
|
||||
|
||||
for i in range(7):
|
||||
if ddhold != 0:
|
||||
await clock01_spi(caravelEnv)
|
||||
ddhold -=1
|
||||
else:
|
||||
await clock00_spi(caravelEnv)
|
||||
|
||||
await clock00_spi(caravelEnv)
|
||||
await clock00_spi(caravelEnv)
|
||||
await clock11_spi(caravelEnv)
|
||||
await clock11_spi(caravelEnv)
|
||||
|
||||
"""right output left output"""
|
||||
async def clock_in_right_o_left_o_standard_spi(caravelEnv,ddhold):
|
||||
await clock11_spi(caravelEnv)
|
||||
await clock11_spi(caravelEnv)
|
||||
|
||||
for i in range(7):
|
||||
if ddhold != 0:
|
||||
await clock01_spi(caravelEnv)
|
||||
ddhold -=1
|
||||
else:
|
||||
await clock00_spi(caravelEnv)
|
||||
|
||||
await clock11_spi(caravelEnv)
|
||||
await clock00_spi(caravelEnv)
|
||||
await clock00_spi(caravelEnv)
|
||||
await clock11_spi(caravelEnv)
|
||||
|
||||
async def clock_in_end_output_spi(caravelEnv):
|
||||
# Right side: GPIO 0 configured disabled
|
||||
# /Left side: GPIO 37 configured as output
|
||||
await clock11_spi(caravelEnv)
|
||||
await clock11_spi(caravelEnv)
|
||||
await clock00_spi(caravelEnv)
|
||||
await clock00_spi(caravelEnv)
|
||||
await clock00_spi(caravelEnv)
|
||||
await clock00_spi(caravelEnv)
|
||||
await clock00_spi(caravelEnv)
|
||||
await clock00_spi(caravelEnv)
|
||||
await clock00_spi(caravelEnv)
|
||||
await clock00_spi(caravelEnv)
|
||||
await clock00_spi(caravelEnv)
|
||||
await clock01_spi(caravelEnv)
|
||||
await clock11_spi(caravelEnv)
|
||||
await load_spi(caravelEnv)
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
#include <defs.h>
|
||||
#include <stub.c>
|
||||
|
||||
// Empty C code
|
||||
|
||||
void main()
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
#include <defs.h>
|
||||
#include <stub.c>
|
||||
|
||||
// Empty C code
|
||||
|
||||
void main()
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
#include <defs.h>
|
||||
#include <stub.c>
|
||||
|
||||
// Empty C code
|
||||
|
||||
void main()
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
#include <defs.h>
|
||||
#include <stub.c>
|
||||
|
||||
// Empty C code
|
||||
|
||||
void main()
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,375 @@
|
|||
import random
|
||||
import cocotb
|
||||
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
|
||||
import cocotb.log
|
||||
from cpu import RiskV
|
||||
from defsParser import Regs
|
||||
from cocotb.result import TestSuccess
|
||||
from tests.common_functions.test_functions import *
|
||||
from tests.bitbang.bitbang_functions import *
|
||||
from caravel import GPIO_MODE
|
||||
|
||||
reg = Regs()
|
||||
|
||||
@cocotb.test()
|
||||
@repot_test
|
||||
async def bitbang_no_cpu_all_o(dut):
|
||||
caravelEnv = await test_configure(dut,timeout_cycles=10000)
|
||||
cpu = RiskV(dut)
|
||||
cpu.cpu_force_reset()
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_37'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_36'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_35'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_34'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_33'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_32'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_31'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_30'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_29'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_28'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_27'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_26'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_25'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_24'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_23'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_22'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_21'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_20'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_19'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_18'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_17'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_16'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_15'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_14'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_13'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_12'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_11'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_10'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_9'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_8'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_7'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_6'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_5'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_4'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_3'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_2'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_1'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_0'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_0'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
|
||||
|
||||
#Configure all as output except reg_mprj_io_3
|
||||
await clear_registers(cpu)
|
||||
await clock_in_right_o_left_o_standard(cpu,0) # 18 and 19
|
||||
await clock_in_right_o_left_o_standard(cpu,0) # 17 and 20
|
||||
await clock_in_right_o_left_o_standard(cpu,0) # 16 and 21
|
||||
await clock_in_right_o_left_o_standard(cpu,0) # 15 and 22
|
||||
await clock_in_right_o_left_o_standard(cpu,0) # 14 and 23
|
||||
await clock_in_right_o_left_o_standard(cpu,0) # 13 and 24
|
||||
await clock_in_right_o_left_o_standard(cpu,0) # 12 and 25
|
||||
await clock_in_right_o_left_o_standard(cpu,0) # 11 and 26
|
||||
await clock_in_right_o_left_o_standard(cpu,0) # 10 and 27
|
||||
await clock_in_right_o_left_o_standard(cpu,0) # 9 and 28
|
||||
await clock_in_right_o_left_o_standard(cpu,0) # 8 and 29
|
||||
await clock_in_right_o_left_o_standard(cpu,0) # 7 and 30
|
||||
await clock_in_right_o_left_o_standard(cpu,0) # 6 and 31
|
||||
await clock_in_right_o_left_o_standard(cpu,0) # 5 and 32
|
||||
await clock_in_right_o_left_o_standard(cpu,0) # 4 and 33
|
||||
await clock_in_right_o_left_i_standard(cpu,0) # 3 and 34
|
||||
await clock_in_right_o_left_i_standard(cpu,0) # 2 and 35
|
||||
await clock_in_right_o_left_i_standard(cpu,0) # 1 and 36
|
||||
await clock_in_end_output(cpu) # 0 and 37 and load
|
||||
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_datal'),0x0)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0x0)
|
||||
|
||||
i= 0x20
|
||||
for j in range(5):
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),i)
|
||||
cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,4))} int {caravelEnv.monitor_gpio((37,4)).integer} i = {i}')
|
||||
if caravelEnv.monitor_gpio((37,4)).integer != i << 28:
|
||||
cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,4))} instead of {bin(i << 28)}')
|
||||
# for k in range(250):
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0)
|
||||
if caravelEnv.monitor_gpio((37,4)).integer != 0:
|
||||
cocotb.log.error(f'[TEST] Wrong gpio output {caravelEnv.monitor_gpio((37,4))} instead of {bin(0x00000)}')
|
||||
|
||||
i = i >> 1
|
||||
i |= 0x20
|
||||
await ClockCycles(caravelEnv.clk, 1)
|
||||
|
||||
i= 0x80000000
|
||||
for j in range(32):
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0x3f)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_datal'),i)
|
||||
if caravelEnv.monitor_gpio((37,32)).integer != 0x3f:
|
||||
cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,32))} instead of {bin(0x3f)}')
|
||||
if caravelEnv.monitor_gpio((31,4)).integer != i>>4 :
|
||||
cocotb.log.error(f'[TEST] Wrong gpio low bits output {caravelEnv.monitor_gpio((31,4))} instead of {i>>4}')
|
||||
cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,4))} type {int(caravelEnv.monitor_gpio((37,4)))} i = {i}')
|
||||
await ClockCycles(caravelEnv.clk, 1)
|
||||
|
||||
# await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0x0)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0x0)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_datal'),0x0)
|
||||
await ClockCycles(caravelEnv.clk, 1)
|
||||
|
||||
if caravelEnv.monitor_gpio((37,4)).integer != 0:
|
||||
cocotb.log.error(f'Wrong gpio output {caravelEnv.monitor_gpio((37,4))} instead of {bin(0x00000)}')
|
||||
|
||||
i = i >> 1
|
||||
i |= 0x80000000
|
||||
|
||||
|
||||
await ClockCycles(caravelEnv.clk, 1000)
|
||||
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
@repot_test
|
||||
async def bitbang_no_cpu_all_i(dut):
|
||||
caravelEnv = await test_configure(dut,timeout_cycles=10000)
|
||||
cpu = RiskV(dut)
|
||||
cpu.cpu_force_reset()
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_37'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_36'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_35'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_34'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_33'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_32'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_31'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_30'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_29'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_28'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_27'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_26'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_25'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_24'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_23'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_22'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_21'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_20'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_19'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_18'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_17'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_16'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_15'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_14'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_13'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_12'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_11'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_10'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_9'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_8'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_7'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_6'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_5'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_4'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_3'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_2'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_1'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_0'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
|
||||
|
||||
#Configure all as input except reg_mprj_io_3
|
||||
await clear_registers(cpu)
|
||||
await clock_in_right_i_left_i_standard(cpu,0) # 18 and 19
|
||||
await clock_in_right_i_left_i_standard(cpu,0) # 17 and 20
|
||||
await clock_in_right_i_left_i_standard(cpu,0) # 16 and 21
|
||||
await clock_in_right_i_left_i_standard(cpu,0) # 15 and 22
|
||||
await clock_in_right_i_left_i_standard(cpu,0) # 14 and 23
|
||||
await clock_in_right_i_left_i_standard(cpu,0) # 13 and 24
|
||||
await clock_in_right_i_left_i_standard(cpu,0) # 12 and 25
|
||||
await clock_in_right_i_left_i_standard(cpu,0) # 11 and 26
|
||||
await clock_in_right_i_left_i_standard(cpu,0) # 10 and 27
|
||||
await clock_in_right_i_left_i_standard(cpu,0) # 9 and 28
|
||||
await clock_in_right_i_left_i_standard(cpu,0) # 8 and 29
|
||||
await clock_in_right_i_left_i_standard(cpu,0) # 7 and 30
|
||||
await clock_in_right_i_left_i_standard(cpu,0) # 6 and 31
|
||||
await clock_in_right_i_left_i_standard(cpu,0) # 5 and 32
|
||||
await clock_in_right_i_left_i_standard(cpu,0) # 4 and 33
|
||||
await clock_in_right_i_left_i_standard(cpu,0) # 3 and 34
|
||||
await clock_in_right_i_left_i_standard(cpu,0) # 2 and 35
|
||||
await clock_in_right_i_left_i_standard(cpu,0) # 1 and 36
|
||||
await clock_in_right_i_left_i_standard(cpu,0) # 0 and 37
|
||||
await load(cpu) # load
|
||||
|
||||
caravelEnv.drive_gpio_in((31,0),0x8F66FD7B)
|
||||
await ClockCycles(caravelEnv.clk, 100)
|
||||
reg_mprj_datal = await cpu.read_address(reg.get_addr('reg_mprj_datal'))
|
||||
# value_masked = reg_mprj_datal & mask_input
|
||||
if reg_mprj_datal == 0x8F66FD7B:
|
||||
cocotb.log.info(f'[TEST] Passed with value 0x8F66FD7B')
|
||||
else:
|
||||
cocotb.log.error(f'[TEST] fail with value mprj = {bin(reg_mprj_datal)} instead of {bin(0x8F66FD7B)}')
|
||||
await ClockCycles(caravelEnv.clk, 100)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0x1B)
|
||||
x = caravelEnv.monitor_gpio((37,32))
|
||||
print(f"xxxxxxxx {x}")
|
||||
await ClockCycles(caravelEnv.clk, 100)
|
||||
|
||||
caravelEnv.drive_gpio_in((31,0),0xFFA88C5A)
|
||||
await ClockCycles(caravelEnv.clk, 100)
|
||||
reg_mprj_datal = await cpu.read_address(reg.get_addr('reg_mprj_datal'))
|
||||
# value_masked = reg_mprj_datal & mask_input
|
||||
if reg_mprj_datal == 0xFFA88C5A:
|
||||
cocotb.log.info(f'[TEST] Passed with value 0xFFA88C5A')
|
||||
else:
|
||||
cocotb.log.error(f'[TEST] fail with value mprj = {bin(reg_mprj_datal)} instead of {bin(0xFFA88C5A)}')
|
||||
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0x2B)
|
||||
await ClockCycles(caravelEnv.clk, 100)
|
||||
|
||||
caravelEnv.drive_gpio_in((31,0),0xC9536346)
|
||||
await ClockCycles(caravelEnv.clk, 100)
|
||||
reg_mprj_datal = await cpu.read_address(reg.get_addr('reg_mprj_datal'))
|
||||
# value_masked = reg_mprj_datal & mask_input
|
||||
if reg_mprj_datal == 0xC9536346:
|
||||
cocotb.log.info(f'[TEST] Passed with value 0xC9536346')
|
||||
else:
|
||||
cocotb.log.error(f'[TEST] fail with value mprj = {bin(reg_mprj_datal)} instead of {bin(0xC9536346)}')
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0x3B)
|
||||
await ClockCycles(caravelEnv.clk, 100)
|
||||
|
||||
|
||||
|
||||
|
||||
"""Testbench of GPIO configuration through bit-bang method using the StriVe housekeeping SPI."""
|
||||
@cocotb.test()
|
||||
@repot_test
|
||||
async def io_ports(dut):
|
||||
caravelEnv = await test_configure(dut)
|
||||
cpu = RiskV(dut)
|
||||
cpu.cpu_force_reset()
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_0'),GPIO_MODE.GPIO_MODE_USER_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_1'),GPIO_MODE.GPIO_MODE_USER_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_2'),GPIO_MODE.GPIO_MODE_USER_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_3'),GPIO_MODE.GPIO_MODE_USER_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_4'),GPIO_MODE.GPIO_MODE_USER_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_5'),GPIO_MODE.GPIO_MODE_USER_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_6'),GPIO_MODE.GPIO_MODE_USER_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_7'),GPIO_MODE.GPIO_MODE_USER_STD_OUTPUT.value)
|
||||
|
||||
# Apply configuration
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_xfer'),1)
|
||||
|
||||
while True:
|
||||
if await cpu.read_address(reg.get_addr('reg_mprj_xfer')) != 1 :
|
||||
break
|
||||
|
||||
"""Testbench of GPIO configuration through bit-bang method using the housekeeping SPI."""
|
||||
@cocotb.test()
|
||||
@repot_test
|
||||
async def bitbang_spi(dut):
|
||||
caravelEnv = await test_configure(dut)
|
||||
# Apply data 0x1809 (management standard output) to first block of
|
||||
# user 1 and user 2 (GPIO 0 and 37) bits 0, 1, 9, and 12 are "1" (data go in backwards)
|
||||
cpu = RiskV(dut)
|
||||
cpu.cpu_force_reset()
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_37'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_36'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_35'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_34'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_33'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_32'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_31'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_30'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_29'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_28'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_27'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_26'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_25'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_24'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_23'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_22'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_21'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_20'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_19'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_18'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_17'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_16'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_15'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_14'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_13'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_12'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_11'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_10'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_9'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_8'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_7'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_6'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_5'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_4'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_3'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_2'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_1'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_0'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_0'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
|
||||
|
||||
#Configure all as output except reg_mprj_io_3
|
||||
await clear_registers(cpu)
|
||||
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 18 and 19
|
||||
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 17 and 20
|
||||
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 16 and 21
|
||||
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 15 and 22
|
||||
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 14 and 23
|
||||
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 13 and 24
|
||||
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 12 and 25
|
||||
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 11 and 26
|
||||
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 10 and 27
|
||||
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 9 and 28
|
||||
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 8 and 29
|
||||
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 7 and 30
|
||||
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 6 and 31
|
||||
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 5 and 32
|
||||
await clock_in_right_o_left_i_standard_spi(caravelEnv,0) # 4 and 33
|
||||
await clock_in_right_o_left_i_standard_spi(caravelEnv,0) # 3 and 34
|
||||
await clock_in_right_o_left_i_standard_spi(caravelEnv,0) # 2 and 35
|
||||
await clock_in_right_o_left_i_standard_spi(caravelEnv,0) # 1 and 36
|
||||
await clock_in_end_output_spi(caravelEnv) # 0 and 37 and load
|
||||
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_datal'),0x0)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0x0)
|
||||
|
||||
i= 0x20
|
||||
for j in range(5):
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),i)
|
||||
cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,5))} int {caravelEnv.monitor_gpio((37,5)).integer} i = {i}')
|
||||
if caravelEnv.monitor_gpio((37,5)).integer != i << 27:
|
||||
cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,5))} instead of {bin(i << 27)}')
|
||||
# for k in range(250):
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0)
|
||||
if caravelEnv.monitor_gpio((37,5)).integer != 0:
|
||||
cocotb.log.error(f'[TEST] Wrong gpio output {caravelEnv.monitor_gpio((37,5))} instead of {bin(0x00000)}')
|
||||
|
||||
i = i >> 1
|
||||
i |= 0x20
|
||||
await ClockCycles(caravelEnv.clk, 1)
|
||||
|
||||
i= 0x80000000
|
||||
for j in range(32):
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0x3f)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_datal'),i)
|
||||
if caravelEnv.monitor_gpio((37,32)).integer != 0x3f:
|
||||
cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,32))} instead of {bin(0x3f)}')
|
||||
if caravelEnv.monitor_gpio((31,5)).integer != i>>5 :
|
||||
cocotb.log.error(f'[TEST] Wrong gpio low bits output {caravelEnv.monitor_gpio((31,5))} instead of {i>>5}')
|
||||
cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,5))} type {int(caravelEnv.monitor_gpio((37,5)))} i = {i}')
|
||||
await ClockCycles(caravelEnv.clk, 1)
|
||||
|
||||
# await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0x0)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0x0)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_datal'),0x0)
|
||||
await ClockCycles(caravelEnv.clk, 1)
|
||||
|
||||
if caravelEnv.monitor_gpio((37,5)).integer != 0:
|
||||
cocotb.log.error(f'Wrong gpio output {caravelEnv.monitor_gpio((37,4))} instead of {bin(0x00000)}')
|
||||
|
||||
i = i >> 1
|
||||
i |= 0x80000000
|
||||
|
||||
|
||||
await ClockCycles(caravelEnv.clk, 1000)
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,199 @@
|
|||
import random
|
||||
import cocotb
|
||||
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
|
||||
import cocotb.log
|
||||
from cpu import RiskV
|
||||
from defsParser import Regs
|
||||
from cocotb.result import TestSuccess
|
||||
from tests.common_functions.test_functions import *
|
||||
from tests.bitbang.bitbang_functions import *
|
||||
from caravel import GPIO_MODE
|
||||
|
||||
reg = Regs()
|
||||
|
||||
@cocotb.test()
|
||||
@repot_test
|
||||
async def bitbang_cpu_all_o(dut):
|
||||
caravelEnv = await test_configure(dut,timeout_cycles=10000000000)
|
||||
cpu = RiskV(dut)
|
||||
cpu.cpu_force_reset()
|
||||
cpu.cpu_release_reset()
|
||||
|
||||
await wait_reg1(cpu,caravelEnv,0xFF)
|
||||
cocotb.log.info("[TEST] finish configuring using bitbang")
|
||||
i= 0x20
|
||||
for j in range(5):
|
||||
await wait_reg2(cpu,caravelEnv,37-j)
|
||||
cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,4))} j = {j}')
|
||||
if caravelEnv.monitor_gpio((37,4)).integer != i << 28:
|
||||
cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,4))} instead of {bin(i << 28)}')
|
||||
await wait_reg2(cpu,caravelEnv,0)
|
||||
if caravelEnv.monitor_gpio((37,4)).integer != 0:
|
||||
cocotb.log.error(f'[TEST] Wrong gpio output {caravelEnv.monitor_gpio((37,4))} instead of {bin(0x00000)}')
|
||||
i = i >> 1
|
||||
i |= 0x20
|
||||
|
||||
i= 0x80000000
|
||||
for j in range(32):
|
||||
await wait_reg2(cpu,caravelEnv,32-j)
|
||||
cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,4))} j = {j}')
|
||||
if caravelEnv.monitor_gpio((37,32)).integer != 0x3f:
|
||||
cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,32))} instead of {bin(0x3f)} ')
|
||||
if caravelEnv.monitor_gpio((31,4)).integer != i>>4 :
|
||||
cocotb.log.error(f'[TEST] Wrong gpio low bits output {caravelEnv.monitor_gpio((31,4))} instead of {bin(i>>4)}')
|
||||
await wait_reg2(cpu,caravelEnv,0)
|
||||
if caravelEnv.monitor_gpio((37,4)).integer != 0:
|
||||
cocotb.log.error(f'Wrong gpio output {caravelEnv.monitor_gpio((37,4))} instead of {bin(0x00000)}')
|
||||
|
||||
i = i >> 1
|
||||
i |= 0x80000000
|
||||
|
||||
|
||||
await ClockCycles(caravelEnv.clk, 10)
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
@repot_test
|
||||
async def bitbang_cpu_all_10(dut):
|
||||
caravelEnv = await test_configure(dut,timeout_cycles=10000000000)
|
||||
cpu = RiskV(dut)
|
||||
cpu.cpu_force_reset()
|
||||
cpu.cpu_release_reset()
|
||||
uut = dut.uut
|
||||
await wait_reg1(cpu,caravelEnv,0xFF)
|
||||
gpios_l = ("gpio_control_bidir_1[0]","gpio_control_bidir_1[1]","gpio_control_in_1a[0]","gpio_control_in_1a[1]","gpio_control_in_1a[2]","gpio_control_in_1a[3]","gpio_control_in_1a[4]","gpio_control_in_1a[5]","gpio_control_in_1[0]","gpio_control_in_1[1]","gpio_control_in_1[2]","gpio_control_in_1[3]","gpio_control_in_1[4]","gpio_control_in_1[5]","gpio_control_in_1[6]","gpio_control_in_1[7]","gpio_control_in_1[8]","gpio_control_in_1[9]","gpio_control_in_1[10]")
|
||||
|
||||
gpios_h= ("gpio_control_in_2[0]","gpio_control_in_2[1]","gpio_control_in_2[2]","gpio_control_in_2[3]","gpio_control_in_2[4]","gpio_control_in_2[5]","gpio_control_in_2[6]","gpio_control_in_2[7]","gpio_control_in_2[8]","gpio_control_in_2[9]","gpio_control_in_2[10]","gpio_control_in_2[11]","gpio_control_in_2[12]","gpio_control_in_2[13]","gpio_control_in_2[14]","gpio_control_in_2[15]","gpio_control_bidir_2[0]","gpio_control_bidir_2[1]","gpio_control_bidir_2[2]")
|
||||
type = True # type of shifting 01 or 10
|
||||
for gpio in gpios_l:
|
||||
shift(uut._id(gpio,False),type)
|
||||
type = not type
|
||||
type = True # type of shifting 01 or 10
|
||||
for gpio in reversed(gpios_h):
|
||||
shift(uut._id(gpio,False),type)
|
||||
type = not type
|
||||
|
||||
|
||||
def shift(gpio,shift_type):
|
||||
if shift_type:
|
||||
bits = "0101010101010"
|
||||
else:
|
||||
bits = "1010101010101"
|
||||
fail = False
|
||||
cocotb.log.info(f"[TEST] gpio {gpio} shift {gpio._id(f'shift_register',False).value} expected {bits}")
|
||||
for i in range(13):
|
||||
if gpio._id(f"shift_register",False).value.binstr[i] != bits[i]:
|
||||
fail = True
|
||||
cocotb.log.error(f"[TEST] wrong shift register {i} in {gpio}")
|
||||
if not fail:
|
||||
cocotb.log.info(f"[TEST] gpio {gpio} passed")
|
||||
|
||||
@cocotb.test()
|
||||
@repot_test
|
||||
async def bitbang_cpu_all_01(dut):
|
||||
caravelEnv = await test_configure(dut,timeout_cycles=10000000000)
|
||||
cpu = RiskV(dut)
|
||||
cpu.cpu_force_reset()
|
||||
cpu.cpu_release_reset()
|
||||
uut = dut.uut
|
||||
await wait_reg1(cpu,caravelEnv,0xFF)
|
||||
gpios_l = ("gpio_control_bidir_1[0]","gpio_control_bidir_1[1]","gpio_control_in_1a[0]","gpio_control_in_1a[1]","gpio_control_in_1a[2]","gpio_control_in_1a[3]","gpio_control_in_1a[4]","gpio_control_in_1a[5]","gpio_control_in_1[0]","gpio_control_in_1[1]","gpio_control_in_1[2]","gpio_control_in_1[3]","gpio_control_in_1[4]","gpio_control_in_1[5]","gpio_control_in_1[6]","gpio_control_in_1[7]","gpio_control_in_1[8]","gpio_control_in_1[9]","gpio_control_in_1[10]")
|
||||
|
||||
gpios_h= ("gpio_control_in_2[0]","gpio_control_in_2[1]","gpio_control_in_2[2]","gpio_control_in_2[3]","gpio_control_in_2[4]","gpio_control_in_2[5]","gpio_control_in_2[6]","gpio_control_in_2[7]","gpio_control_in_2[8]","gpio_control_in_2[9]","gpio_control_in_2[10]","gpio_control_in_2[11]","gpio_control_in_2[12]","gpio_control_in_2[13]","gpio_control_in_2[14]","gpio_control_in_2[15]","gpio_control_bidir_2[0]","gpio_control_bidir_2[1]","gpio_control_bidir_2[2]")
|
||||
type = False # type of shifting 01 or 10
|
||||
for gpio in gpios_l:
|
||||
shift(uut._id(gpio,False),type)
|
||||
type = not type
|
||||
type = False # type of shifting 01 or 10
|
||||
for gpio in reversed(gpios_h):
|
||||
shift(uut._id(gpio,False),type)
|
||||
type = not type
|
||||
|
||||
@cocotb.test()
|
||||
@repot_test
|
||||
async def bitbang_cpu_all_0011(dut):
|
||||
caravelEnv = await test_configure(dut,timeout_cycles=10000000000)
|
||||
cpu = RiskV(dut)
|
||||
cpu.cpu_force_reset()
|
||||
cpu.cpu_release_reset()
|
||||
uut = dut.uut
|
||||
await wait_reg1(cpu,caravelEnv,0xFF)
|
||||
gpios_l = ("gpio_control_bidir_1[0]","gpio_control_bidir_1[1]","gpio_control_in_1a[0]","gpio_control_in_1a[1]","gpio_control_in_1a[2]","gpio_control_in_1a[3]","gpio_control_in_1a[4]","gpio_control_in_1a[5]","gpio_control_in_1[0]","gpio_control_in_1[1]","gpio_control_in_1[2]","gpio_control_in_1[3]","gpio_control_in_1[4]","gpio_control_in_1[5]","gpio_control_in_1[6]","gpio_control_in_1[7]","gpio_control_in_1[8]","gpio_control_in_1[9]","gpio_control_in_1[10]")
|
||||
|
||||
gpios_h= ("gpio_control_in_2[0]","gpio_control_in_2[1]","gpio_control_in_2[2]","gpio_control_in_2[3]","gpio_control_in_2[4]","gpio_control_in_2[5]","gpio_control_in_2[6]","gpio_control_in_2[7]","gpio_control_in_2[8]","gpio_control_in_2[9]","gpio_control_in_2[10]","gpio_control_in_2[11]","gpio_control_in_2[12]","gpio_control_in_2[13]","gpio_control_in_2[14]","gpio_control_in_2[15]","gpio_control_bidir_2[0]","gpio_control_bidir_2[1]","gpio_control_bidir_2[2]")
|
||||
type = 0 # type of shifting 01 or 10
|
||||
for gpio in gpios_l:
|
||||
shift_2(uut._id(gpio,False),type)
|
||||
type = (type + 1) %4
|
||||
type = 0 # type of shifting 01 or 10
|
||||
for gpio in reversed(gpios_h):
|
||||
shift_2(uut._id(gpio,False),type)
|
||||
type = (type + 1) %4
|
||||
|
||||
@cocotb.test()
|
||||
@repot_test
|
||||
async def bitbang_cpu_all_1100(dut):
|
||||
caravelEnv = await test_configure(dut,timeout_cycles=10000000000)
|
||||
cpu = RiskV(dut)
|
||||
cpu.cpu_force_reset()
|
||||
cpu.cpu_release_reset()
|
||||
uut = dut.uut
|
||||
await wait_reg1(cpu,caravelEnv,0xFF)
|
||||
gpios_l = ("gpio_control_bidir_1[0]","gpio_control_bidir_1[1]","gpio_control_in_1a[0]","gpio_control_in_1a[1]","gpio_control_in_1a[2]","gpio_control_in_1a[3]","gpio_control_in_1a[4]","gpio_control_in_1a[5]","gpio_control_in_1[0]","gpio_control_in_1[1]","gpio_control_in_1[2]","gpio_control_in_1[3]","gpio_control_in_1[4]","gpio_control_in_1[5]","gpio_control_in_1[6]","gpio_control_in_1[7]","gpio_control_in_1[8]","gpio_control_in_1[9]","gpio_control_in_1[10]")
|
||||
|
||||
gpios_h= ("gpio_control_in_2[0]","gpio_control_in_2[1]","gpio_control_in_2[2]","gpio_control_in_2[3]","gpio_control_in_2[4]","gpio_control_in_2[5]","gpio_control_in_2[6]","gpio_control_in_2[7]","gpio_control_in_2[8]","gpio_control_in_2[9]","gpio_control_in_2[10]","gpio_control_in_2[11]","gpio_control_in_2[12]","gpio_control_in_2[13]","gpio_control_in_2[14]","gpio_control_in_2[15]","gpio_control_bidir_2[0]","gpio_control_bidir_2[1]","gpio_control_bidir_2[2]")
|
||||
type = 2 # type of shifting 01 or 10
|
||||
for gpio in gpios_l:
|
||||
shift_2(uut._id(gpio,False),type)
|
||||
type = (type + 1) %4
|
||||
type = 2 # type of shifting 01 or 10
|
||||
for gpio in reversed(gpios_h):
|
||||
shift_2(uut._id(gpio,False),type)
|
||||
type = (type + 1) %4
|
||||
|
||||
def shift_2(gpio,shift_type):
|
||||
if shift_type == 0:
|
||||
bits = "1001100110011"
|
||||
elif shift_type == 1:
|
||||
bits = "1100110011001"
|
||||
elif shift_type == 2:
|
||||
bits = "0110011001100"
|
||||
elif shift_type == 3:
|
||||
bits = "0011001100110"
|
||||
fail = False
|
||||
cocotb.log.info(f"[TEST] gpio {gpio} shift {gpio._id(f'shift_register',False).value} expected {bits}")
|
||||
for i in range(13):
|
||||
if gpio._id(f"shift_register",False).value.binstr[i] != bits[i]:
|
||||
fail = True
|
||||
cocotb.log.error(f"[TEST] wrong shift register {i} in {gpio}")
|
||||
if not fail:
|
||||
cocotb.log.info(f"[TEST] gpio {gpio} passed")
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
@repot_test
|
||||
async def bitbang_cpu_all_i(dut):
|
||||
caravelEnv = await test_configure(dut,timeout_cycles=10000000000)
|
||||
cpu = RiskV(dut)
|
||||
cpu.cpu_force_reset()
|
||||
cpu.cpu_release_reset()
|
||||
uut = dut.uut
|
||||
await wait_reg1(cpu,caravelEnv,0xAA)
|
||||
cocotb.log.info(f"[TEST] configuration finished")
|
||||
data_in = 0x8F66FD7B
|
||||
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[0:32]")
|
||||
caravelEnv.drive_gpio_in((31,0),data_in)
|
||||
await wait_reg1(cpu,caravelEnv,0xBB)
|
||||
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[0:32]")
|
||||
data_in = 0xFFA88C5A
|
||||
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[0:32]")
|
||||
caravelEnv.drive_gpio_in((31,0),data_in)
|
||||
await wait_reg1(cpu,caravelEnv,0xCC)
|
||||
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[0:32]")
|
||||
data_in = 0xC9536346
|
||||
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[0:32]")
|
||||
caravelEnv.drive_gpio_in((31,0),data_in)
|
||||
|
||||
await wait_reg2(cpu,caravelEnv,0xFF)
|
||||
cocotb.log.info(f"[TEST] finish")
|
||||
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
|
||||
# from turtle import st
|
||||
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
|
||||
import cocotb.log
|
||||
from cocotb.result import SimTimeoutError
|
||||
import cocotb
|
||||
import time
|
||||
"""class to handle timeout inside the tests. after the provided number of cycles (cycle_num) are exceeded test would fail
|
||||
precision would determine when to log timeout warning for example if cycle_num=1000 and percision = 10% so after each 1000*10% = 100 cycle log would be printed
|
||||
"""
|
||||
class Timeout:
|
||||
def __init__(self,clk,cycle_num,precision=0.20):
|
||||
self.clk = clk
|
||||
self.cycle_num = cycle_num
|
||||
self.cycle_precision = precision * cycle_num
|
||||
cocotb.scheduler.add(self._timeout_check())
|
||||
|
||||
|
||||
async def _timeout_check(self):
|
||||
number_of_cycles = 0
|
||||
for i in range(0,self.cycle_num):
|
||||
await ClockCycles(self.clk,1)
|
||||
number_of_cycles +=1
|
||||
if number_of_cycles %self.cycle_precision ==0:
|
||||
cocotb.log.warning(f"simulation are only {self.cycle_num-number_of_cycles} cycles away from TIMEOUT ")
|
||||
|
||||
raise SimTimeoutError(f"simulation exceeds the max number of cycles {self.cycle_num}")
|
||||
|
||||
pass
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,95 @@
|
|||
|
||||
import random
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
import cocotb.log
|
||||
import caravel
|
||||
from logic_analyzer import LA
|
||||
from wb_models.housekeepingWB.housekeepingWB import HK_whiteBox
|
||||
import common
|
||||
import logging
|
||||
from cpu import RiskV
|
||||
from cocotb.log import SimTimeContextFilter
|
||||
from cocotb.log import SimLogFormatter
|
||||
from tests.common_functions.Timeout import Timeout
|
||||
import os
|
||||
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
|
||||
|
||||
"""configure the test log file location and log verbosity
|
||||
configure the test clock
|
||||
configure the test timeout
|
||||
configure whitbox models
|
||||
start up the test connecting power vdd to the design then reset and disable the CSB bit
|
||||
return the caravel environmnet with clock and start up
|
||||
"""
|
||||
async def test_configure(dut,timeout_cycles=1000000,clk=12.5,timeout_precision=0.2,num_error=3):
|
||||
caravelEnv = caravel.Caravel_env(dut)
|
||||
Timeout(caravelEnv.clk,timeout_cycles,timeout_precision)
|
||||
if os.getenv('ERRORMAX') != 'None':
|
||||
num_error = int(os.getenv('ERRORMAX'))
|
||||
cocotb.scheduler.add(max_num_error(num_error,caravelEnv.clk))
|
||||
clock = Clock(caravelEnv.clk, clk, units="ns") # Create a 10ns period clock on port clk
|
||||
cocotb.start_soon(clock.start()) # Start the clock
|
||||
await caravelEnv.start_up()
|
||||
await ClockCycles(caravelEnv.clk, 10)
|
||||
# HK_whiteBox(dut)
|
||||
return caravelEnv
|
||||
|
||||
class CallCounted:
|
||||
"""Decorator to determine number of calls for a method"""
|
||||
|
||||
def __init__(self,method):
|
||||
self.method=method
|
||||
self.counter=0
|
||||
|
||||
def __call__(self,*args,**kwargs):
|
||||
self.counter+=1
|
||||
return self.method(*args,**kwargs)
|
||||
|
||||
|
||||
def repot_test(func):
|
||||
async def wrapper_func(*args, **kwargs):
|
||||
## configure logging
|
||||
COCOTB_ANSI_OUTPUT=0
|
||||
|
||||
TestName = func.__name__
|
||||
cocotb.log.setLevel(logging.INFO)
|
||||
cocotb.log.error = CallCounted(cocotb.log.error)
|
||||
cocotb.log.critical = CallCounted(cocotb.log.critical)
|
||||
cocotb.log.warning = CallCounted(cocotb.log.warning)
|
||||
handler = logging.FileHandler(f"sim/{os.getenv('RUNTAG')}/{os.getenv('SIM')}-{TestName}/{TestName}.log",mode='w')
|
||||
handler.addFilter(SimTimeContextFilter())
|
||||
handler.setFormatter(SimLogFormatter())
|
||||
cocotb.log.addHandler(handler)
|
||||
## call test
|
||||
await func(*args, **kwargs)
|
||||
## report after finish simulation
|
||||
msg = f'with ({cocotb.log.critical.counter})criticals ({cocotb.log.error.counter})errors ({cocotb.log.warning.counter})warnings '
|
||||
if cocotb.log.error.counter > 0 or cocotb.log.critical.counter >0:
|
||||
raise cocotb.result.TestComplete(f'Test failed {msg}')
|
||||
else:
|
||||
raise cocotb.result.TestComplete(f'Test passed {msg}')
|
||||
return retval
|
||||
return wrapper_func
|
||||
|
||||
async def max_num_error(num_error,clk):
|
||||
while True:
|
||||
await ClockCycles(clk,1)
|
||||
if cocotb.log.error.counter + cocotb.log.critical.counter > num_error:
|
||||
msg = f'Test failed with max number of errors {num_error} ({cocotb.log.critical.counter})criticals ({cocotb.log.error.counter})errors ({cocotb.log.warning.counter})warnings '
|
||||
raise cocotb.result.TestFailure(msg)
|
||||
|
||||
|
||||
async def wait_reg1(cpu,caravelEnv,data):
|
||||
while (True):
|
||||
if cpu.read_debug_reg1() == data:
|
||||
return
|
||||
await ClockCycles(caravelEnv.clk,10)
|
||||
|
||||
|
||||
async def wait_reg2(cpu,caravelEnv,data):
|
||||
while (True):
|
||||
if cpu.read_debug_reg2() == data:
|
||||
return
|
||||
await ClockCycles(caravelEnv.clk,10)
|
||||
|
||||
|
|
@ -0,0 +1,156 @@
|
|||
#include <defs.h>
|
||||
|
||||
int A[]={1, 40, 2, 5, 22, 11, 90, 200, 10, 20, 25};
|
||||
|
||||
// int factorial(int n) {
|
||||
// int fac=1;
|
||||
// for(int i=1; i<=n;++i){
|
||||
// fac = fac * i;
|
||||
// }
|
||||
// return fac;
|
||||
// }
|
||||
|
||||
int fibbonacci(int n) {
|
||||
if(n == 0){
|
||||
return 0;
|
||||
} else if(n == 1) {
|
||||
return 1;
|
||||
} else {
|
||||
return (fibbonacci(n-1) + fibbonacci(n-2));
|
||||
}
|
||||
}
|
||||
|
||||
void recursiveInsertionSort(int arr[], int n){
|
||||
if (n <= 1)
|
||||
return;
|
||||
recursiveInsertionSort( arr, n-1 );
|
||||
int nth = arr[n-1];
|
||||
int j = n-2;
|
||||
while (j >= 0 && arr[j] > nth){
|
||||
arr[j+1] = arr[j];
|
||||
j--;
|
||||
}
|
||||
arr[j+1] = nth;
|
||||
}
|
||||
|
||||
|
||||
void quick_sort(int number[],int first,int last){
|
||||
int i, j, pivot, temp;
|
||||
|
||||
if(first<last){
|
||||
pivot=first;
|
||||
i=first;
|
||||
j=last;
|
||||
|
||||
while(i<j){
|
||||
while(number[i]<=number[pivot]&&i<last)
|
||||
i++;
|
||||
while(number[j]>number[pivot])
|
||||
j--;
|
||||
if(i<j){
|
||||
temp=number[i];
|
||||
number[i]=number[j];
|
||||
number[j]=temp;
|
||||
}
|
||||
}
|
||||
|
||||
temp=number[pivot];
|
||||
number[pivot]=number[j];
|
||||
number[j]=temp;
|
||||
quick_sort(number,first,j-1);
|
||||
quick_sort(number,j+1,last);
|
||||
|
||||
}
|
||||
}
|
||||
int f4(int a, int b, int c, int d){
|
||||
return a + b + c + d;
|
||||
}
|
||||
|
||||
int f5(int a, int b, int c, int d, int e){
|
||||
return e + f4(a, b, c, d);
|
||||
}
|
||||
|
||||
int f6(int a, int b, int c, int d, int e, int f){
|
||||
return f + f5(a, b, c, d, e);
|
||||
}
|
||||
|
||||
int f7(int a, int b, int c, int d, int e, int f, int g){
|
||||
return g + f6(a, b, c, d, e, f);
|
||||
}
|
||||
int f8(int a, int b, int c, int d, int e, int f, int g, int h){
|
||||
return h + f7(a, b, c, d, e, f, g);
|
||||
}
|
||||
/*
|
||||
Stress the cpu with heavy processing
|
||||
|
||||
*/
|
||||
void main()
|
||||
{
|
||||
int n;
|
||||
int B[10];
|
||||
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
|
||||
reg_debug_1 = 0x0;
|
||||
reg_debug_2 = 0x0;
|
||||
// start test
|
||||
// reg_mprj_datal = 0xAAAA0000;
|
||||
|
||||
// n =factorial(12);
|
||||
// if(n != 479001600)
|
||||
// reg_mprj_datal = 0xFFFF0000; //fail
|
||||
|
||||
// reg_mprj_datal = 0x11110000; //phase 1 pass
|
||||
|
||||
n = fibbonacci(10);
|
||||
if(n != 55)
|
||||
reg_debug_1 = 0x1E; // fail pahse 1
|
||||
else
|
||||
reg_debug_1 = 0x1B; // pass pahse 1
|
||||
|
||||
int sumA = 0;
|
||||
for(int i=0; i<10; i++){
|
||||
B[i] = A[i];
|
||||
sumA += A[i];
|
||||
}
|
||||
|
||||
if(sumA != 401)
|
||||
reg_debug_1 = 0x2E; // fail pahse 2
|
||||
else
|
||||
reg_debug_1 = 0x2B; // pass pahse 2
|
||||
|
||||
recursiveInsertionSort(B, 10);
|
||||
|
||||
int sumB = 0;
|
||||
for(int i=0; i<10; i++){
|
||||
sumB += B[i];
|
||||
}
|
||||
|
||||
if(sumA != sumB)
|
||||
reg_debug_1 = 0x3E;// fail pahse 3
|
||||
else
|
||||
reg_debug_1 = 0x3B; // pass pahse 3
|
||||
|
||||
for(int i=0; i<10; i++){
|
||||
B[i] = A[i];
|
||||
sumA += A[i];
|
||||
}
|
||||
quick_sort(B, 0, 9);
|
||||
|
||||
for(int i=0; i<10; i++){
|
||||
sumB += B[i];
|
||||
}
|
||||
|
||||
if(sumA != sumB)
|
||||
reg_debug_1 = 0x4E;// fail pahse 4
|
||||
else
|
||||
reg_debug_1 = 0x4B; // pass pahse 4
|
||||
|
||||
int sum = f8(10, 20, 30, 40, 50, 60, 70, 80);
|
||||
|
||||
if(sum != (10+20+30+40+50+60+70+80))
|
||||
reg_debug_1 = 0x5E; // fail pahse 5
|
||||
else
|
||||
reg_debug_1 = 0x5B; // pass pahse 5
|
||||
|
||||
// test finish
|
||||
reg_debug_2 = 0xFF;
|
||||
}
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
import random
|
||||
import cocotb
|
||||
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
|
||||
import cocotb.log
|
||||
from cpu import RiskV
|
||||
from defsParser import Regs
|
||||
from cocotb.result import TestSuccess
|
||||
from tests.common_functions.test_functions import *
|
||||
from tests.bitbang.bitbang_functions import *
|
||||
from caravel import GPIO_MODE
|
||||
|
||||
reg = Regs()
|
||||
"""stress the cpu with heavy processing"""
|
||||
@cocotb.test()
|
||||
@repot_test
|
||||
async def cpu_stress(dut):
|
||||
caravelEnv = await test_configure(dut,timeout_cycles=1492434)
|
||||
cpu = RiskV(dut)
|
||||
cpu.cpu_force_reset()
|
||||
cpu.cpu_release_reset()
|
||||
cocotb.log.info(f"[TEST] Start CPU stress test")
|
||||
pass_list = (0x1B,0x2B,0x3B,0x4B,0x5B)
|
||||
fail_list = (0x1E,0x2E,0x3E,0x4E,0x5E)
|
||||
phases_fails = 5
|
||||
phases_passes = 0
|
||||
reg1 =0 # buffer
|
||||
while True:
|
||||
if cpu.read_debug_reg2() == 0xFF: # test finish
|
||||
break
|
||||
if reg1 != cpu.read_debug_reg1():
|
||||
reg1 = cpu.read_debug_reg1()
|
||||
if reg1 in pass_list: # pass phase
|
||||
phases_passes +=1
|
||||
phases_fails -=1
|
||||
cocotb.log.info(f"[TEST] pass phase {hex(reg1)[2]}")
|
||||
elif reg1 in fail_list: # pass phase
|
||||
cocotb.log.error(f"[TEST] failed phase {hex(reg1)[2]}")
|
||||
await ClockCycles(caravelEnv.clk,1)
|
||||
|
||||
if phases_fails > 0:
|
||||
cocotb.log.error(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails")
|
||||
else:
|
||||
cocotb.log.info(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails")
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
#include <defs.h>
|
||||
#include <stub.c>
|
||||
#include "../bitbang/bitbang_functions.c"
|
||||
|
||||
void main(){
|
||||
unsigned int i, j, k;
|
||||
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
|
||||
reg_debug_1 = 0x0;
|
||||
reg_debug_2 = 0x0;
|
||||
|
||||
reg_mprj_io_37 = 0x1803;
|
||||
reg_mprj_io_36 = 0x1803;
|
||||
reg_mprj_io_35 = 0x1803;
|
||||
reg_mprj_io_34 = 0x1803;
|
||||
reg_mprj_io_33 = 0x1803;
|
||||
reg_mprj_io_32 = 0x1803;
|
||||
reg_mprj_io_31 = 0x1803;
|
||||
reg_mprj_io_30 = 0x1803;
|
||||
reg_mprj_io_29 = 0x1803;
|
||||
reg_mprj_io_28 = 0x1803;
|
||||
reg_mprj_io_27 = 0x1803;
|
||||
reg_mprj_io_26 = 0x1803;
|
||||
reg_mprj_io_25 = 0x1803;
|
||||
reg_mprj_io_24 = 0x1803;
|
||||
reg_mprj_io_23 = 0x1803;
|
||||
reg_mprj_io_22 = 0x1803;
|
||||
reg_mprj_io_21 = 0x1803;
|
||||
reg_mprj_io_20 = 0x1803;
|
||||
reg_mprj_io_19 = 0x1803;
|
||||
reg_mprj_io_18 = 0x1803;
|
||||
reg_mprj_io_17 = 0x1803;
|
||||
reg_mprj_io_16 = 0x1803;
|
||||
reg_mprj_io_15 = 0x1803;
|
||||
reg_mprj_io_14 = 0x1803;
|
||||
reg_mprj_io_13 = 0x1803;
|
||||
reg_mprj_io_12 = 0x1803;
|
||||
reg_mprj_io_11 = 0x1803;
|
||||
reg_mprj_io_10 = 0x1803;
|
||||
reg_mprj_io_9 = 0x1803;
|
||||
reg_mprj_io_8 = 0x1803;
|
||||
reg_mprj_io_7 = 0x1803;
|
||||
reg_mprj_io_6 = 0x1803;
|
||||
reg_mprj_io_5 = 0x1803;
|
||||
reg_mprj_io_4 = 0x1803;
|
||||
reg_mprj_io_3 = 0x1803;
|
||||
reg_mprj_io_2 = 0x1803;
|
||||
reg_mprj_io_1 = 0x1803;
|
||||
reg_mprj_io_0 = 0x1803;
|
||||
reg_mprj_io_0 = 0x1803;
|
||||
|
||||
reg_mprj_xfer = 1;
|
||||
while (reg_mprj_xfer == 1);
|
||||
|
||||
reg_debug_1 = 0XAA; // configuration done wait environment to send 0x8F66FD7B to reg_mprj_datal
|
||||
while (reg_mprj_datal != 0x8F66FD7B);
|
||||
reg_debug_1 = 0XBB; // configuration done wait environment to send 0xFFA88C5A to reg_mprj_datal
|
||||
while (reg_mprj_datal != 0xFFA88C5A);
|
||||
reg_debug_1 = 0XCC; // configuration done wait environment to send 0xC9536346 to reg_mprj_datal
|
||||
while (reg_mprj_datal != 0xC9536346);
|
||||
|
||||
reg_debug_2 = 0xFF;
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,79 @@
|
|||
#include <defs.h>
|
||||
#include <stub.c>
|
||||
#include "../bitbang/bitbang_functions.c"
|
||||
|
||||
void main(){
|
||||
unsigned int i, j, k;
|
||||
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
|
||||
reg_debug_1 = 0x0;
|
||||
reg_debug_2 = 0x0;
|
||||
|
||||
reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_7 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_5 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_4 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_3 = 0x1803 ;
|
||||
reg_mprj_io_2 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
|
||||
reg_mprj_xfer = 1;
|
||||
while (reg_mprj_xfer == 1);
|
||||
|
||||
reg_debug_1 = 0xFF; // finish configuration
|
||||
reg_mprj_datal = 0x0;
|
||||
reg_mprj_datah = 0x0;
|
||||
i = 0x20;
|
||||
for (j = 0; j < 5; j++) {
|
||||
reg_mprj_datah = i;
|
||||
reg_debug_2 = 37-j;
|
||||
reg_mprj_datah = 0x00000000;
|
||||
reg_debug_2 = 0;
|
||||
i >>=1;
|
||||
i |= 0x20;
|
||||
}
|
||||
i = 0x80000000;
|
||||
for (j = 0; j < 32; j++) {
|
||||
reg_mprj_datah = 0x3f;
|
||||
reg_mprj_datal = i;
|
||||
reg_debug_2 = 32-j;
|
||||
reg_mprj_datah = 0x00;
|
||||
reg_mprj_datal = 0x00000000;
|
||||
reg_debug_2 = 0;
|
||||
i >>=1;
|
||||
i |= 0x80000000;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,83 @@
|
|||
import random
|
||||
import cocotb
|
||||
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
|
||||
import cocotb.log
|
||||
from cpu import RiskV
|
||||
from defsParser import Regs
|
||||
from cocotb.result import TestSuccess
|
||||
from tests.common_functions.test_functions import *
|
||||
from tests.bitbang.bitbang_functions import *
|
||||
from caravel import GPIO_MODE
|
||||
|
||||
reg = Regs()
|
||||
|
||||
@cocotb.test()
|
||||
@repot_test
|
||||
async def gpio_all_o(dut):
|
||||
caravelEnv = await test_configure(dut,timeout_cycles=10000000000)
|
||||
cpu = RiskV(dut)
|
||||
cpu.cpu_force_reset()
|
||||
cpu.cpu_release_reset()
|
||||
|
||||
await wait_reg1(cpu,caravelEnv,0xFF)
|
||||
cocotb.log.info("[TEST] finish configuring using bitbang")
|
||||
i= 0x20
|
||||
for j in range(5):
|
||||
await wait_reg2(cpu,caravelEnv,37-j)
|
||||
cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,4))} j = {j}')
|
||||
if caravelEnv.monitor_gpio((37,4)).integer != i << 28:
|
||||
cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,4))} instead of {bin(i << 28)}')
|
||||
await wait_reg2(cpu,caravelEnv,0)
|
||||
if caravelEnv.monitor_gpio((37,4)).integer != 0:
|
||||
cocotb.log.error(f'[TEST] Wrong gpio output {caravelEnv.monitor_gpio((37,4))} instead of {bin(0x00000)}')
|
||||
i = i >> 1
|
||||
i |= 0x20
|
||||
|
||||
i= 0x80000000
|
||||
for j in range(32):
|
||||
await wait_reg2(cpu,caravelEnv,32-j)
|
||||
cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,4))} j = {j}')
|
||||
if caravelEnv.monitor_gpio((37,32)).integer != 0x3f:
|
||||
cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,32))} instead of {bin(0x3f)} ')
|
||||
if caravelEnv.monitor_gpio((31,4)).integer != i>>4 :
|
||||
cocotb.log.error(f'[TEST] Wrong gpio low bits output {caravelEnv.monitor_gpio((31,4))} instead of {bin(i>>4)}')
|
||||
await wait_reg2(cpu,caravelEnv,0)
|
||||
if caravelEnv.monitor_gpio((37,4)).integer != 0:
|
||||
cocotb.log.error(f'Wrong gpio output {caravelEnv.monitor_gpio((37,4))} instead of {bin(0x00000)}')
|
||||
|
||||
i = i >> 1
|
||||
i |= 0x80000000
|
||||
|
||||
|
||||
await ClockCycles(caravelEnv.clk, 10)
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
@repot_test
|
||||
async def gpio_all_i(dut):
|
||||
caravelEnv = await test_configure(dut,timeout_cycles=10000000000)
|
||||
cpu = RiskV(dut)
|
||||
cpu.cpu_force_reset()
|
||||
cpu.cpu_release_reset()
|
||||
uut = dut.uut
|
||||
await wait_reg1(cpu,caravelEnv,0xAA)
|
||||
cocotb.log.info(f"[TEST] configuration finished")
|
||||
data_in = 0x8F66FD7B
|
||||
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[0:32]")
|
||||
caravelEnv.drive_gpio_in((31,0),data_in)
|
||||
await wait_reg1(cpu,caravelEnv,0xBB)
|
||||
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[0:32]")
|
||||
data_in = 0xFFA88C5A
|
||||
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[0:32]")
|
||||
caravelEnv.drive_gpio_in((31,0),data_in)
|
||||
await wait_reg1(cpu,caravelEnv,0xCC)
|
||||
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[0:32]")
|
||||
data_in = 0xC9536346
|
||||
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[0:32]")
|
||||
caravelEnv.drive_gpio_in((31,0),data_in)
|
||||
|
||||
await wait_reg2(cpu,caravelEnv,0xFF)
|
||||
cocotb.log.info(f"[TEST] finish")
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
|
||||
int main(){
|
||||
// do nothing
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
import cocotb
|
||||
from tests.common_functions.test_functions import *
|
||||
|
||||
@cocotb.test()
|
||||
@repot_test
|
||||
|
||||
async def helloWorld(dut):
|
||||
caravelEnv = await test_configure(dut)
|
||||
cocotb.log.info("[Test] Hello world")
|
||||
caravelEnv.print_gpios_ctrl_val()
|
||||
caravelEnv.print_gpios_HW_val()
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
#include <defs.h>
|
||||
#include <stub.c>
|
||||
|
||||
// Empty C code
|
||||
|
||||
void main()
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
#include <defs.h>
|
||||
#include <stub.c>
|
||||
|
||||
// Empty C code
|
||||
|
||||
void main()
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
#include <defs.h>
|
||||
#include <stub.c>
|
||||
|
||||
// Empty C code
|
||||
|
||||
void main()
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,189 @@
|
|||
from json.encoder import INFINITY
|
||||
import random
|
||||
import cocotb
|
||||
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
|
||||
import cocotb.log
|
||||
from cpu import RiskV
|
||||
from defsParser import Regs
|
||||
from cocotb.result import TestSuccess
|
||||
from tests.common_functions.test_functions import *
|
||||
from tests.bitbang.bitbang_functions import *
|
||||
from caravel import GPIO_MODE
|
||||
import json
|
||||
|
||||
reg = Regs()
|
||||
|
||||
|
||||
'''randomly write then read housekeeping regs through wishbone'''
|
||||
@cocotb.test()
|
||||
@repot_test
|
||||
async def hk_regs_wr_wb(dut):
|
||||
caravelEnv = await test_configure(dut,timeout_cycles=100000,num_error=INFINITY)
|
||||
cpu = RiskV(dut)
|
||||
cpu.cpu_force_reset()
|
||||
with open('wb_models/housekeepingWB/HK_regs.json') as f:
|
||||
regs = json.load(f)
|
||||
await ClockCycles(caravelEnv.clk, 10)
|
||||
# write then read
|
||||
for i in range(random.randint(7, 20)):
|
||||
bits_num = 32
|
||||
mem = random.choice(['GPIO']) # can't access 'SPI' and 'sys' register from cpu / read or write
|
||||
key = random.choice(list(regs[mem].keys()))
|
||||
if key == 'base_addr':
|
||||
continue
|
||||
key_num = int(key,16) & 0xFC
|
||||
key = generate_key_from_num(key_num)
|
||||
address = (int(key,16) + regs[mem]['base_addr'][1])
|
||||
if address in [0x26000010,0x2600000c]: # skip testing reg_mprj_datal and reg_mprj_datah because when reading them it's getting the gpio input value
|
||||
continue
|
||||
data_in = random.getrandbits(bits_num)
|
||||
cocotb.log.info(f"[TEST] Writing {bin(data_in)} to {regs[mem][key][0][0]} address {hex(address)} through wishbone")
|
||||
await cpu.drive_data2address(address,data_in)
|
||||
#calculate the expected value for each bit
|
||||
data_exp = ''
|
||||
keys = [generate_key_from_num(key_num+3),generate_key_from_num(key_num+2),generate_key_from_num(key_num+1),generate_key_from_num(key_num)]
|
||||
for count , k in enumerate(keys):
|
||||
for i in range(int(bits_num/len(keys)) * (count),int(bits_num/len(keys)) * (count+1)):
|
||||
bit_exist = False
|
||||
if k in regs[mem].keys():
|
||||
for field in regs[mem][k]:
|
||||
field_shift = field[2]
|
||||
field_size = field[3]
|
||||
field_access = field[4]
|
||||
i_temp = (bits_num -1 -i) % (bits_num/4)
|
||||
if field_shift <= i_temp and i_temp <= (field_shift + field_size-1):
|
||||
if field_access == "RW":
|
||||
data_exp += bin(data_in)[2:].zfill(bits_num)[i]
|
||||
bit_exist = True
|
||||
break
|
||||
if not bit_exist:
|
||||
data_exp += '0'
|
||||
|
||||
cocotb.log.info(f"[TEST] expected data calculated = {data_exp}")
|
||||
data_out = await cpu.read_address(address)
|
||||
cocotb.log.info(f"[TEST] Read {bin(data_out)} from {regs[mem][key][0][0]} address {hex(address)} through wishbone")
|
||||
if data_out != int(data_exp,2): cocotb.log.error(f"[TEST] wrong read from {regs[mem][key][0][0]} address {hex(address)} retuned val= {bin(data_out)[2:].zfill(bits_num)} expected = {data_exp}")
|
||||
else: cocotb.log.debug(f"[TEST] read the right value {hex(data_out)} from {regs[mem][key][0][0]} address {address} ")
|
||||
|
||||
'''randomly write then read housekeeping regs through SPI'''
|
||||
@cocotb.test()
|
||||
@repot_test
|
||||
async def hk_regs_wr_spi(dut):
|
||||
caravelEnv = await test_configure(dut,timeout_cycles=100000,num_error=INFINITY)
|
||||
|
||||
with open('wb_models/housekeepingWB/HK_regs.json') as f:
|
||||
regs = json.load(f)
|
||||
# write then read single byte
|
||||
for i in range(random.randint(10, 40)):
|
||||
bits_num = 8 # byte testing
|
||||
mem = random.choice(['GPIO','SPI','sys'])
|
||||
key = random.choice(list(regs[mem].keys()))
|
||||
if key == 'base_addr':
|
||||
continue
|
||||
address = regs[mem][key][0][7]
|
||||
if address in [0x69,0x6A,0x6B,0x6C]: # skip testing reg_mprj_datal and reg_mprj_datah because when reading them it's getting the gpio input value
|
||||
continue
|
||||
data_in = random.getrandbits(bits_num)
|
||||
cocotb.log.info(f"[TEST] Writing {bin(data_in)} to reg [{regs[mem][key][0][0]}] address {hex(address)} through SPI")
|
||||
await write_reg_spi(caravelEnv,address=address,data=data_in)
|
||||
#calculate the expected value for each bit
|
||||
data_exp = ''
|
||||
for i in range(bits_num):
|
||||
bit_exist = False
|
||||
for field in regs[mem][key]:
|
||||
field_shift = field[2]
|
||||
field_size = field[3]
|
||||
field_access = field[4]
|
||||
reset_val = field[5]
|
||||
i_temp = bits_num -1 -i
|
||||
if field_shift <= i_temp and i_temp <= (field_shift + field_size-1):
|
||||
if field_access == "RW":
|
||||
data_exp += bin(data_in)[2:].zfill(bits_num)[i]
|
||||
bit_exist = True
|
||||
break
|
||||
else : # read only get the value from reset
|
||||
data_exp += bin(reset_val)[2:].zfill(bits_num)[i]
|
||||
if not bit_exist:
|
||||
data_exp += '0'
|
||||
|
||||
cocotb.log.info(f"[TEST] expected data calculated = {data_exp}")
|
||||
data_out = await read_reg_spi(caravelEnv,address=address)
|
||||
cocotb.log.info(f"[TEST] Read {bin(data_out)} from [{regs[mem][key][0][0]}] address {hex(address)} through SPI")
|
||||
if data_out != int(data_exp,2): cocotb.log.error(f"[TEST] wrong read from [{regs[mem][key][0][0]}] address {hex(address)} retuned val= {bin(data_out)[2:].zfill(bits_num)} expected = {data_exp}")
|
||||
else: cocotb.log.debug(f"[TEST] read the right value {hex(data_out)} from [{regs[mem][key][0][0]}] address {address} ")
|
||||
|
||||
'''check reset value of house keeping register'''
|
||||
@cocotb.test()
|
||||
@repot_test
|
||||
async def hk_regs_rst_spi(dut):
|
||||
caravelEnv = await test_configure(dut,timeout_cycles=100000,num_error=INFINITY)
|
||||
|
||||
with open('wb_models/housekeepingWB/HK_regs.json') as f:
|
||||
regs = json.load(f)
|
||||
# read
|
||||
bits_num = 8 # byte testing
|
||||
mems = ['GPIO','SPI','sys']
|
||||
|
||||
for mem in mems:
|
||||
keys = [k for k in regs[mem].keys()]
|
||||
for key in keys:
|
||||
if key == 'base_addr':
|
||||
continue
|
||||
address = regs[mem][key][0][7]
|
||||
if address in [0x69,0x6A,0x6B,0x6C,0x6D,0x1A]: # skip testing reg_mprj_datal, reg_mprj_datah and usr2_vdd_pwrgood because when reading them it's getting the gpio input value
|
||||
continue
|
||||
#calculate the expected value for each bit for reset value
|
||||
data_exp = ''
|
||||
# for i in range(bits_num):
|
||||
bit_exist = False
|
||||
for field in regs[mem][key]:
|
||||
field_shift = field[2]
|
||||
field_size = field[3]
|
||||
field_access = field[4]
|
||||
reset_val = field[5]
|
||||
i_temp = bits_num -1 #-i
|
||||
# if field_shift <= i_temp and i_temp <= (field_shift + field_size-1):
|
||||
data_exp = bin(reset_val)[2:].zfill(field_size) + data_exp
|
||||
print (f'reset = {bin(reset_val)[2:].zfill(bits_num)} data exp = {data_exp} i temp = {i_temp} shift {field_shift} size {field_size}')
|
||||
# bit_exist = True
|
||||
# break
|
||||
# if not bit_exist:
|
||||
# data_exp += '0'
|
||||
|
||||
cocotb.log.info(f"[TEST] expected reset value for [{regs[mem][key][0][0]}] is {data_exp}")
|
||||
data_out = await read_reg_spi(caravelEnv,address=address)
|
||||
cocotb.log.info(f"[TEST] Read {bin(data_out)} from [{regs[mem][key][0][0]}] address {hex(address)} through wishbone")
|
||||
if data_out != int(data_exp,2): cocotb.log.error(f"[TEST] wrong reset value read from [{regs[mem][key][0][0]}] address {address} retuned val= {bin(data_out)[2:].zfill(bits_num)} expected = {data_exp}")
|
||||
else: cocotb.log.info(f"[TEST] read the right reset value {hex(data_out)} from [{regs[mem][key][0][0]}] address {address} ")
|
||||
|
||||
|
||||
|
||||
|
||||
async def write_reg_spi(caravelEnv,address,data):
|
||||
await caravelEnv.enable_csb()
|
||||
await caravelEnv.hk_write_byte(0x80) # Write stream command
|
||||
await caravelEnv.hk_write_byte(address) # Address (register 19 = GPIO bit-bang control)
|
||||
await caravelEnv.hk_write_byte(data) # Data = 0x01 (enable bit-bang mode)
|
||||
await caravelEnv.disable_csb()
|
||||
|
||||
|
||||
async def read_reg_spi(caravelEnv,address):
|
||||
await caravelEnv.enable_csb()
|
||||
await caravelEnv.hk_write_byte(0x40) # read stream command
|
||||
await caravelEnv.hk_write_byte(address) # Address
|
||||
data = await caravelEnv.hk_read_byte() # Data = 0x01 (enable bit-bang mode)
|
||||
await caravelEnv.disable_csb()
|
||||
return data
|
||||
|
||||
|
||||
def generate_key_from_num(num):
|
||||
hex_string = hex(num)
|
||||
hex_list = [i for i in hex_string]
|
||||
if len(hex_list)==3:
|
||||
hex_list.insert(2,'0')
|
||||
hex_string = "".join(hex_list)
|
||||
return hex_string
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,103 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2020 Efabless Corporation
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <csr.h>
|
||||
#include <soc.h>
|
||||
#include <irq_vex.h>
|
||||
#include <uart.h>
|
||||
|
||||
#include <defs.h>
|
||||
|
||||
/*
|
||||
Testing timer interrupts
|
||||
Enable interrupt for IRQ external pin mprj_io[7] -> should be drived to 1 by the environment
|
||||
**NOTE** housekeeping SPI should used to update register irq_1_inputsrc to 1 see verilog code
|
||||
|
||||
@wait for environment to make mprj[7] high
|
||||
send packet size = 1
|
||||
|
||||
@received interrupt correctly test pass
|
||||
send packet size = 5
|
||||
|
||||
@ timeout test fail
|
||||
send packet size = 9
|
||||
|
||||
@ end test
|
||||
send packet size = 3
|
||||
send packet size = 3
|
||||
send packet size = 3
|
||||
|
||||
*/
|
||||
|
||||
extern uint16_t flag;
|
||||
|
||||
void main(){
|
||||
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
|
||||
reg_debug_1 = 0x0;
|
||||
reg_debug_2 = 0x0;
|
||||
|
||||
// setting bit 7 as input
|
||||
reg_mprj_io_7 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
|
||||
// automatic bitbang approach
|
||||
if(1){
|
||||
reg_mprj_xfer = 1;
|
||||
while (reg_mprj_xfer == 1);
|
||||
}
|
||||
irq_setmask(0);
|
||||
irq_setie(1);
|
||||
irq_setmask(irq_getmask() | (1 << USER_IRQ_4_INTERRUPT));
|
||||
reg_user4_irq_en =1;
|
||||
|
||||
// test interrrupt happen when mprj[7] is asserted
|
||||
reg_debug_2 = 0xAA; //wait for environment to make mprj[7] high
|
||||
flag = 0;
|
||||
// Loop, waiting for the interrupt to change reg_mprj_datah
|
||||
bool is_pass = false;
|
||||
int timeout = 40;
|
||||
|
||||
for (int i = 0; i < timeout; i++){
|
||||
if (flag == 1){
|
||||
reg_debug_1 = 0x1B; //test pass irq sent at mprj 7
|
||||
is_pass = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (!is_pass){
|
||||
reg_debug_1 = 0x1E; // timeout
|
||||
}
|
||||
|
||||
// test interrupt doesn't happened when mprj[7] is deasserted
|
||||
reg_debug_2 = 0xBB;
|
||||
flag = 0;
|
||||
// Loop, waiting for the interrupt to change reg_mprj_datah
|
||||
is_pass = false;
|
||||
|
||||
for (int i = 0; i < timeout; i++){
|
||||
if (flag == 1){
|
||||
reg_debug_1 = 0x2E; //test fail interrupt isn't suppose to happened
|
||||
is_pass = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (!is_pass){
|
||||
reg_debug_1 = 0x2B; // test pass
|
||||
}
|
||||
|
||||
// test finish
|
||||
reg_debug_2 = 0xFF;
|
||||
}
|
||||
|
|
@ -0,0 +1,75 @@
|
|||
import random
|
||||
import cocotb
|
||||
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
|
||||
import cocotb.log
|
||||
from cpu import RiskV
|
||||
from defsParser import Regs
|
||||
from cocotb.result import TestSuccess
|
||||
from tests.common_functions.test_functions import *
|
||||
from tests.bitbang.bitbang_functions import *
|
||||
from caravel import GPIO_MODE
|
||||
|
||||
async def write_reg_spi(caravelEnv,address,data):
|
||||
await caravelEnv.enable_csb()
|
||||
await caravelEnv.hk_write_byte(0x80) # Write stream command
|
||||
await caravelEnv.hk_write_byte(address) # Address (register 19 = GPIO bit-bang control)
|
||||
await caravelEnv.hk_write_byte(data) # Data = 0x01 (enable bit-bang mode)
|
||||
await caravelEnv.disable_csb()
|
||||
|
||||
reg = Regs()
|
||||
"""Testbench of GPIO configuration through bit-bang method using the StriVe housekeeping SPI."""
|
||||
@cocotb.test()
|
||||
@repot_test
|
||||
async def IRQ_external(dut):
|
||||
caravelEnv = await test_configure(dut,timeout_cycles=18613481)
|
||||
cpu = RiskV(dut)
|
||||
cpu.cpu_force_reset()
|
||||
cpu.cpu_release_reset()
|
||||
cocotb.log.info(f"[TEST] Start IRQ_external test")
|
||||
pass_list = (0x1B,0x2B)
|
||||
fail_list = (0x1E,0x2E)
|
||||
phases_fails = 2
|
||||
phases_passes = 0
|
||||
reg1 =0 # buffer
|
||||
reg2 = 0 #buffer
|
||||
await ClockCycles(caravelEnv.clk,10)
|
||||
|
||||
await write_reg_spi(caravelEnv,0x1c,1)
|
||||
await ClockCycles(caravelEnv.clk,10)
|
||||
cocotb.log.info(f"irq 1 = {dut.uut.housekeeping.irq_1_inputsrc.value}")
|
||||
|
||||
while True:
|
||||
if reg2 != cpu.read_debug_reg2():
|
||||
reg2 = cpu.read_debug_reg2()
|
||||
if reg2 == 0xFF: # test finish
|
||||
break
|
||||
if reg2 == 0xAA: # assert mprj 7
|
||||
caravelEnv.drive_gpio_in((7,7),0)
|
||||
await ClockCycles(caravelEnv.clk,10)
|
||||
caravelEnv.drive_gpio_in((7,7),1)
|
||||
|
||||
if reg2 == 0xBB: # deassert mprj 7
|
||||
caravelEnv.drive_gpio_in((7,7),0)
|
||||
|
||||
if reg1 != cpu.read_debug_reg1():
|
||||
reg1 = cpu.read_debug_reg1()
|
||||
if reg1 in pass_list: # pass phase
|
||||
phases_passes +=1
|
||||
phases_fails -=1
|
||||
if reg1 == 0x1B:
|
||||
cocotb.log.info(f"[TEST] Pass interrupt is detected when mprj 7 asserted")
|
||||
elif reg1 == 0x2B:
|
||||
cocotb.log.info(f"[TEST] Pass interrupt isn't detected when mprj 7 deasserted")
|
||||
elif reg1 in fail_list: # pass phase
|
||||
if reg1 == 0x1E:
|
||||
cocotb.log.info(f"[TEST] Failed interrupt isn't detected when mprj 7 asserted")
|
||||
elif reg1 == 0x2E:
|
||||
cocotb.log.error(f"[TEST] Failed interrupt is detected when mprj 7 deasserted")
|
||||
else:
|
||||
cocotb.log.error(f"[TEST] debug register 1 has illegal value")
|
||||
await ClockCycles(caravelEnv.clk,10)
|
||||
|
||||
if phases_fails != 0:
|
||||
cocotb.log.error(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails")
|
||||
else:
|
||||
cocotb.log.info(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails")
|
||||
|
|
@ -0,0 +1,88 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2020 Efabless Corporation
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <csr.h>
|
||||
#include <soc.h>
|
||||
#include <irq_vex.h>
|
||||
#include <uart.h>
|
||||
|
||||
#include <defs.h>
|
||||
|
||||
|
||||
extern uint16_t flag;
|
||||
|
||||
void main(){
|
||||
uint16_t data;
|
||||
int i;
|
||||
|
||||
|
||||
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
|
||||
reg_debug_1 = 0x0;
|
||||
reg_debug_2 = 0x0;
|
||||
|
||||
irq_setmask(0);
|
||||
irq_setie(1);
|
||||
|
||||
|
||||
irq_setmask(irq_getmask() | (1 << TIMER0_INTERRUPT));
|
||||
reg_debug_2 = 0xAA; //wait for timer to send irq
|
||||
|
||||
flag = 0;
|
||||
/* Configure timer for a single-shot countdown */
|
||||
reg_timer0_config = 0;
|
||||
reg_timer0_data = 30;
|
||||
reg_timer0_irq_en = 1;
|
||||
reg_timer0_config = 1;
|
||||
|
||||
// Loop, waiting for the interrupt to change reg_mprj_datah
|
||||
bool is_pass = false;
|
||||
int timeout = 40;
|
||||
|
||||
for (int i = 0; i < timeout; i++){
|
||||
if (flag == 1){
|
||||
reg_debug_1 = 0x1B; //test pass irq sent at timer0
|
||||
is_pass = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (!is_pass){
|
||||
reg_debug_1 = 0x1E; // timeout
|
||||
}
|
||||
flag = 0;
|
||||
// test interrupt doesn't happened when timer isnt used
|
||||
reg_debug_2 = 0xBB;
|
||||
reg_timer0_config = 0; // disable counter
|
||||
flag = 0;
|
||||
// Loop, waiting for the interrupt to change reg_mprj_datah
|
||||
is_pass = false;
|
||||
|
||||
for (int i = 0; i < timeout; i++){
|
||||
if (flag == 1){
|
||||
reg_debug_1 = 0x2E; //test fail interrupt isn't suppose to happened
|
||||
is_pass = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (!is_pass){
|
||||
reg_debug_1 = 0x2B; // test pass
|
||||
}
|
||||
|
||||
// test finish
|
||||
reg_debug_2 = 0xFF;
|
||||
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,51 @@
|
|||
import random
|
||||
import cocotb
|
||||
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
|
||||
import cocotb.log
|
||||
from cpu import RiskV
|
||||
from defsParser import Regs
|
||||
from cocotb.result import TestSuccess
|
||||
from tests.common_functions.test_functions import *
|
||||
from tests.bitbang.bitbang_functions import *
|
||||
from caravel import GPIO_MODE
|
||||
|
||||
reg = Regs()
|
||||
"""Testbench of GPIO configuration through bit-bang method using the StriVe housekeeping SPI."""
|
||||
@cocotb.test()
|
||||
@repot_test
|
||||
async def IRQ_timer(dut):
|
||||
caravelEnv = await test_configure(dut,timeout_cycles=18613481)
|
||||
cpu = RiskV(dut)
|
||||
cpu.cpu_force_reset()
|
||||
cpu.cpu_release_reset()
|
||||
cocotb.log.info(f"[TEST] Start IRQ_timer test")
|
||||
pass_list = (0x1B,0x2B)
|
||||
fail_list = (0x1E,0x2E)
|
||||
phases_fails = 2
|
||||
phases_passes = 0
|
||||
reg1 =0 # buffer
|
||||
while True:
|
||||
if cpu.read_debug_reg2() == 0xFF: # test finish
|
||||
break
|
||||
if reg1 != cpu.read_debug_reg1():
|
||||
reg1 = cpu.read_debug_reg1()
|
||||
if reg1 in pass_list: # pass phase
|
||||
phases_passes +=1
|
||||
phases_fails -=1
|
||||
if reg1 == 0x1B:
|
||||
cocotb.log.info(f"[TEST] Pass interrupt is detected when timer is used")
|
||||
elif reg1 == 0x2B:
|
||||
cocotb.log.info(f"[TEST] Pass interrupt isn't detected when timer isnt used")
|
||||
elif reg1 in fail_list: # pass phase
|
||||
if reg1 == 0x1E:
|
||||
cocotb.log.info(f"[TEST] Failed interrupt isn't detected when timer is used")
|
||||
elif reg1 == 0x2E:
|
||||
cocotb.log.error(f"[TEST] Failed interrupt is detected when timer isnt used")
|
||||
else:
|
||||
cocotb.log.error(f"[TEST] debug register 1 has illegal value")
|
||||
await ClockCycles(caravelEnv.clk,10)
|
||||
|
||||
if phases_fails != 0:
|
||||
cocotb.log.error(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails")
|
||||
else:
|
||||
cocotb.log.info(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails")
|
||||
|
|
@ -0,0 +1,89 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2020 Efabless Corporation
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#include <defs.h>
|
||||
|
||||
#include <csr.h>
|
||||
#include <soc.h>
|
||||
#include <irq_vex.h>
|
||||
#include <uart.h>
|
||||
#include <stub.c>
|
||||
|
||||
|
||||
|
||||
|
||||
extern uint16_t flag;
|
||||
|
||||
void main(){
|
||||
|
||||
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
|
||||
reg_debug_1 = 0x0;
|
||||
reg_debug_2 = 0x0;
|
||||
|
||||
reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_5 = 0x1803;
|
||||
|
||||
if(1){
|
||||
reg_mprj_xfer = 1;
|
||||
while (reg_mprj_xfer == 1);
|
||||
}
|
||||
reg_uart_enable = 1;
|
||||
reg_uart_irq_en =1;
|
||||
irq_setmask(0);
|
||||
irq_setie(1);
|
||||
|
||||
|
||||
irq_setmask(irq_getmask() | (1 << UART_INTERRUPT));
|
||||
flag = 0;
|
||||
|
||||
reg_debug_2 = 0xAA; //start sending data through the uart
|
||||
print("M");
|
||||
|
||||
// Loop, waiting for the interrupt to change reg_mprj_datah
|
||||
bool is_pass = false;
|
||||
int timeout = 100;
|
||||
|
||||
for (int i = 0; i < timeout; i++){
|
||||
if (flag == 1){
|
||||
reg_debug_1 = 0x1B; //test pass irq sent
|
||||
is_pass = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (!is_pass){
|
||||
reg_debug_1 = 0x1E; // timeout
|
||||
}
|
||||
// test interrupt doesn't happened nothing sent at uart
|
||||
reg_debug_2 = 0xBB;
|
||||
flag = 0;
|
||||
// Loop, waiting for the interrupt to change reg_mprj_datah
|
||||
is_pass = false;
|
||||
|
||||
for (int i = 0; i < timeout; i++){
|
||||
if (flag == 1){
|
||||
reg_debug_1 = 0x2E; //test fail interrupt isn't suppose to happened
|
||||
is_pass = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (!is_pass){
|
||||
reg_debug_1 = 0x2B; // test pass
|
||||
}
|
||||
// test finish
|
||||
reg_debug_2 = 0xFF;
|
||||
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,64 @@
|
|||
import random
|
||||
import cocotb
|
||||
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
|
||||
import cocotb.log
|
||||
from cpu import RiskV
|
||||
from defsParser import Regs
|
||||
from cocotb.result import TestSuccess
|
||||
from tests.common_functions.test_functions import *
|
||||
from tests.bitbang.bitbang_functions import *
|
||||
from caravel import GPIO_MODE
|
||||
|
||||
async def write_reg_spi(caravelEnv,address,data):
|
||||
await caravelEnv.enable_csb()
|
||||
await caravelEnv.hk_write_byte(0x80) # Write stream command
|
||||
await caravelEnv.hk_write_byte(address) # Address (register 19 = GPIO bit-bang control)
|
||||
await caravelEnv.hk_write_byte(data) # Data = 0x01 (enable bit-bang mode)
|
||||
await caravelEnv.disable_csb()
|
||||
|
||||
reg = Regs()
|
||||
"""Testbench of GPIO configuration through bit-bang method using the StriVe housekeeping SPI."""
|
||||
@cocotb.test()
|
||||
@repot_test
|
||||
async def IRQ_uart(dut):
|
||||
caravelEnv = await test_configure(dut,timeout_cycles=18613481)
|
||||
cpu = RiskV(dut)
|
||||
cpu.cpu_force_reset()
|
||||
cpu.cpu_release_reset()
|
||||
cocotb.log.info(f"[TEST] Start IRQ_uart test")
|
||||
pass_list = (0x1B,0x2B)
|
||||
fail_list = (0x1E,0x2E)
|
||||
phases_fails = 2
|
||||
phases_passes = 0
|
||||
reg1 =0 # buffer
|
||||
reg2 = 0 #buffer
|
||||
while True:
|
||||
if reg2 != cpu.read_debug_reg2():
|
||||
reg2 = cpu.read_debug_reg2()
|
||||
if reg2 == 0xFF: # test finish
|
||||
break
|
||||
if reg2 == 0xAA:
|
||||
cocotb.log.info(f"[TEST] start sending through uart")
|
||||
|
||||
if reg1 != cpu.read_debug_reg1():
|
||||
reg1 = cpu.read_debug_reg1()
|
||||
if reg1 in pass_list: # pass phase
|
||||
phases_passes +=1
|
||||
phases_fails -=1
|
||||
if reg1 == 0x1B:
|
||||
cocotb.log.info(f"[TEST] Pass interrupt is detected when uart is sending data")
|
||||
elif reg1 == 0x2B:
|
||||
cocotb.log.info(f"[TEST] Pass interrupt isn't detected when uart isnt sending data")
|
||||
elif reg1 in fail_list: # pass phase
|
||||
if reg1 == 0x1E:
|
||||
cocotb.log.info(f"[TEST] Failed interrupt isn't detected uart is sending data")
|
||||
elif reg1 == 0x2E:
|
||||
cocotb.log.error(f"[TEST] Failed interrupt is detected uart isnt sending data")
|
||||
else:
|
||||
cocotb.log.error(f"[TEST] debug register 1 has illegal value")
|
||||
await ClockCycles(caravelEnv.clk,10)
|
||||
|
||||
if phases_fails != 0:
|
||||
cocotb.log.error(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails")
|
||||
else:
|
||||
cocotb.log.info(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails")
|
||||
|
|
@ -0,0 +1,102 @@
|
|||
#include <defs.h>
|
||||
|
||||
/*
|
||||
@ start of test
|
||||
send packet with size = 1
|
||||
@ pass bytes
|
||||
send packet with size = 2
|
||||
@ pass int
|
||||
send packet with size = 3
|
||||
@ pass short
|
||||
send packet with size = 4
|
||||
@ error reading
|
||||
send packet with size = 9
|
||||
@ test finish
|
||||
send packet with size = 7
|
||||
send packet with size = 7
|
||||
send packet with size = 7
|
||||
|
||||
*/
|
||||
#define BYTE_SIZE 800
|
||||
#define SHORT_SIZE BYTE_SIZE/2
|
||||
#define INT_SIZE BYTE_SIZE/4
|
||||
void main()
|
||||
{
|
||||
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
|
||||
reg_debug_1 = 0x0;
|
||||
reg_debug_2 = 0x0;
|
||||
unsigned char dff_bytes[BYTE_SIZE];
|
||||
unsigned short *dff_shorts=(unsigned short *) dff_bytes;
|
||||
unsigned int *dff_ints=(unsigned int *) dff_bytes;
|
||||
unsigned char magic = 0x79;
|
||||
unsigned int magic_int = 0x79797979;
|
||||
unsigned short magic_short = 0x7979;
|
||||
unsigned char magic1;
|
||||
unsigned int magic1_int;
|
||||
unsigned short magic1_short;
|
||||
int i;
|
||||
magic1 = magic;
|
||||
for ( i=0; i<BYTE_SIZE; i++){
|
||||
dff_bytes[i] = (magic1*3+5)|magic;
|
||||
magic1 += 11;
|
||||
}
|
||||
magic1 = magic;
|
||||
bool is_fail = false;
|
||||
for ( i=0; i<BYTE_SIZE; i++){
|
||||
unsigned char t = (magic1*3+5)|magic;
|
||||
if (t != dff_bytes[i]){
|
||||
reg_debug_1 = 0x1E; // fail reading bytes expected value
|
||||
is_fail = true;
|
||||
break;
|
||||
}
|
||||
magic1 += 11;
|
||||
}
|
||||
if (!is_fail)
|
||||
reg_debug_1 = 0x1B; // pass reading bytes expected value
|
||||
|
||||
is_fail = false;
|
||||
// int
|
||||
magic1_int = magic_int;
|
||||
for ( i=0; i<INT_SIZE; i++){
|
||||
dff_ints[i] = (magic1_int*3+5)|magic_int;
|
||||
magic1_int += 11;
|
||||
}
|
||||
magic1_int = magic_int;
|
||||
|
||||
for ( i=0; i<INT_SIZE; i++){
|
||||
unsigned int t = (magic1_int*3+5)|magic_int;
|
||||
if (t != dff_ints[i]){
|
||||
reg_debug_1 = 0x2E; // fail reading ints expected value
|
||||
is_fail = true;
|
||||
break;
|
||||
}
|
||||
magic1_int += 11;
|
||||
}
|
||||
if (!is_fail)
|
||||
reg_debug_1 = 0x2B; // pass reading ints expected value
|
||||
|
||||
is_fail = false;
|
||||
|
||||
// short
|
||||
magic1_short = magic_short;
|
||||
for ( i=0; i<SHORT_SIZE; i++){
|
||||
dff_shorts[i] = (magic1_short*3+5)|magic_short;
|
||||
magic1_short += 11;
|
||||
}
|
||||
magic1_short = magic_short;
|
||||
|
||||
for ( i=0; i<SHORT_SIZE; i++){
|
||||
unsigned short t = (magic1_short*3+5)|magic_short;
|
||||
if (t != dff_shorts[i]){
|
||||
reg_debug_1 = 0x3E; // fail reading shorts expected value
|
||||
is_fail = true;
|
||||
break;
|
||||
}
|
||||
magic1_short += 11;
|
||||
}
|
||||
if (!is_fail)
|
||||
reg_debug_1 = 0x3B; // pass reading ints expected value
|
||||
|
||||
// test finish
|
||||
reg_debug_2 = 0xFF;
|
||||
}
|
||||
|
|
@ -0,0 +1,51 @@
|
|||
import random
|
||||
import cocotb
|
||||
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
|
||||
import cocotb.log
|
||||
from cpu import RiskV
|
||||
from defsParser import Regs
|
||||
from cocotb.result import TestSuccess
|
||||
from tests.common_functions.test_functions import *
|
||||
from tests.bitbang.bitbang_functions import *
|
||||
from caravel import GPIO_MODE
|
||||
|
||||
reg = Regs()
|
||||
"""Testbench of GPIO configuration through bit-bang method using the StriVe housekeeping SPI."""
|
||||
@cocotb.test()
|
||||
@repot_test
|
||||
async def mem_stress(dut):
|
||||
caravelEnv = await test_configure(dut,timeout_cycles=18613481)
|
||||
cpu = RiskV(dut)
|
||||
cpu.cpu_force_reset()
|
||||
cpu.cpu_release_reset()
|
||||
cocotb.log.info(f"[TEST] Start mem stress test")
|
||||
pass_list = (0x1B,0x2B,0x3B)
|
||||
fail_list = (0x1E,0x2E,0x3E)
|
||||
phases_fails = 3
|
||||
phases_passes = 0
|
||||
reg1 =0 # buffer
|
||||
while True:
|
||||
if cpu.read_debug_reg2() == 0xFF: # test finish
|
||||
break
|
||||
if reg1 != cpu.read_debug_reg1():
|
||||
reg1 = cpu.read_debug_reg1()
|
||||
if reg1 in pass_list: # pass phase
|
||||
phases_passes +=1
|
||||
phases_fails -=1
|
||||
cocotb.log.info(f"[TEST] pass writing and reading from {phase_to_type(hex(reg1)[2])}")
|
||||
elif reg1 in fail_list: # pass phase
|
||||
cocotb.log.error(f"[TEST] failed phase {phase_to_type(hex(reg1)[2])}")
|
||||
await ClockCycles(caravelEnv.clk,1)
|
||||
|
||||
if phases_fails > 0:
|
||||
cocotb.log.error(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails")
|
||||
else:
|
||||
cocotb.log.info(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails")
|
||||
|
||||
def phase_to_type(phase):
|
||||
if phase == "1":
|
||||
return "800 Bytes"
|
||||
elif phase == "2":
|
||||
return "200 Words"
|
||||
elif phase == "3":
|
||||
return "400 Halfwords"
|
||||
|
|
@ -0,0 +1,105 @@
|
|||
import random
|
||||
import cocotb
|
||||
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
|
||||
import cocotb.log
|
||||
from cpu import RiskV
|
||||
from defsParser import Regs
|
||||
from cocotb.result import TestSuccess
|
||||
from tests.common_functions.test_functions import *
|
||||
from tests.bitbang.bitbang_functions import *
|
||||
from caravel import GPIO_MODE
|
||||
|
||||
reg = Regs()
|
||||
"""Testbench of GPIO configuration through bit-bang method using the StriVe housekeeping SPI."""
|
||||
@cocotb.test()
|
||||
@repot_test
|
||||
async def mgmt_gpio_out(dut):
|
||||
caravelEnv = await test_configure(dut,timeout_cycles=18613481)
|
||||
cpu = RiskV(dut)
|
||||
cpu.cpu_force_reset()
|
||||
cpu.cpu_release_reset()
|
||||
cocotb.log.info(f"[TEST] Start mgmt_gpio_out test")
|
||||
phases_fails = 2
|
||||
phases_passes = 0
|
||||
reg1 =0 # buffer
|
||||
reg2 = 0 #buffer
|
||||
|
||||
while True:
|
||||
if reg2 != cpu.read_debug_reg2():
|
||||
reg2 = cpu.read_debug_reg2()
|
||||
if reg2 == 0xFF: # test finish
|
||||
break
|
||||
if reg1 != cpu.read_debug_reg1():
|
||||
reg1 = cpu.read_debug_reg1()
|
||||
cocotb.log.info(f"[TEST] waiting for {reg1} blinks")
|
||||
for i in range(reg1):
|
||||
while (True):
|
||||
if caravelEnv.monitor_mgmt_gpio() == 0:
|
||||
break
|
||||
if reg1 != cpu.read_debug_reg1():
|
||||
cocotb.log.error("[TEST] error failing to catch all blinking ")
|
||||
return
|
||||
await ClockCycles(caravelEnv.clk,10)
|
||||
|
||||
while (True):
|
||||
if caravelEnv.monitor_mgmt_gpio() == 1:
|
||||
break
|
||||
if reg1 != cpu.read_debug_reg1():
|
||||
cocotb.log.error("[TEST] error failing to catch all blinking ")
|
||||
return
|
||||
await ClockCycles(caravelEnv.clk,10)
|
||||
cocotb.log.info("[TEST] passing sending {reg1} blinks ")
|
||||
phases_fails -=1
|
||||
await ClockCycles(caravelEnv.clk,10)
|
||||
|
||||
if phases_fails != 0:
|
||||
cocotb.log.error(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails")
|
||||
else:
|
||||
cocotb.log.info(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails")
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
@repot_test
|
||||
async def mgmt_gpio_in(dut):
|
||||
caravelEnv = await test_configure(dut,timeout_cycles=18613481)
|
||||
cpu = RiskV(dut)
|
||||
cpu.cpu_force_reset()
|
||||
cpu.cpu_release_reset()
|
||||
cocotb.log.info(f"[TEST] Start mgmt_gpio_in test")
|
||||
phases_fails = 3
|
||||
phases_passes = 0
|
||||
pass_list = (0x1B,0x2B,0xFF)
|
||||
fail_list = tuple([0xEE])
|
||||
reg1 =0 # buffer
|
||||
reg2 = 0 #buffer
|
||||
|
||||
while True:
|
||||
if reg2 != cpu.read_debug_reg2():
|
||||
reg2 = cpu.read_debug_reg2()
|
||||
if reg2 in pass_list:
|
||||
cocotb.log.info (f"[TEST] reg2 = {reg2}")
|
||||
phases_passes +=1
|
||||
phases_fails -=1
|
||||
if reg2 == 0xFF: # test finish
|
||||
break
|
||||
elif reg2 == 0x1B:
|
||||
cocotb.log.info(f"[TEST] pass sending 10 blink ")
|
||||
elif reg2 == 0x2B:
|
||||
cocotb.log.info(f"[TEST] pass sending 20 blink ")
|
||||
if reg2 in fail_list:
|
||||
cocotb.log.error(f"[TEST] gpio change without sending anything")
|
||||
if reg1 != cpu.read_debug_reg1():
|
||||
reg1 = cpu.read_debug_reg1()
|
||||
cocotb.log.info(f"[TEST] start sending {reg1} blinks")
|
||||
for i in range(reg1):
|
||||
caravelEnv.drive_mgmt_gpio(1)
|
||||
await wait_reg2(cpu,caravelEnv,0XAA)
|
||||
caravelEnv.drive_mgmt_gpio(0)
|
||||
await wait_reg2(cpu,caravelEnv,0XBB)
|
||||
cocotb.log.info(f"[TEST] finish sending {reg1} blinks ")
|
||||
await ClockCycles(caravelEnv.clk,10)
|
||||
|
||||
if phases_fails != 0:
|
||||
cocotb.log.error(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails")
|
||||
else:
|
||||
cocotb.log.info(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails")
|
||||
|
|
@ -0,0 +1,67 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2020 Efabless Corporation
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <defs.h>
|
||||
|
||||
// --------------------------------------------------------
|
||||
|
||||
/*
|
||||
* Management SoC GPIO Pin Test
|
||||
* Tests writing to the GPIO pin.
|
||||
*/
|
||||
|
||||
void main()
|
||||
{
|
||||
int temp_in;
|
||||
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
|
||||
reg_debug_1 = 0x0;
|
||||
reg_debug_2 = 0x0;
|
||||
|
||||
reg_gpio_mode1 = 1;
|
||||
reg_gpio_mode0 = 0; // for full swing
|
||||
|
||||
reg_gpio_ien = 1;
|
||||
reg_gpio_oe = 1;
|
||||
|
||||
reg_debug_1 = 10; // wait for 10 blinks
|
||||
for (int i = 0; i < 10; i++) {
|
||||
while(reg_gpio_in == 0);
|
||||
reg_debug_2 = 0XAA; // 1 is recieved
|
||||
while(reg_gpio_in == 1);
|
||||
reg_debug_2 = 0XBB; // 0 is recieved
|
||||
}
|
||||
reg_debug_2 = 0x1B;
|
||||
reg_debug_1 = 20;
|
||||
for (int i = 0; i < 20; i++) {
|
||||
while(reg_gpio_in == 0);
|
||||
reg_debug_2 = 0XAA; // 1 is recieved
|
||||
while(reg_gpio_in == 1);
|
||||
reg_debug_2 = 0XBB; // 0 is recieved
|
||||
}
|
||||
reg_debug_2 = 0x2B;
|
||||
temp_in = reg_gpio_in;
|
||||
reg_debug_1 = 0;
|
||||
for (int i =0; i<50;i++){ // timeout
|
||||
if (temp_in != reg_gpio_in)
|
||||
reg_debug_2 = 0xEE; //finish test
|
||||
|
||||
}
|
||||
reg_debug_2 = 0xFF; //finish test
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,59 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2020 Efabless Corporation
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <defs.h>
|
||||
|
||||
// --------------------------------------------------------
|
||||
|
||||
/*
|
||||
* Management SoC GPIO Pin Test
|
||||
* Tests writing to the GPIO pin.
|
||||
*/
|
||||
|
||||
void main()
|
||||
{
|
||||
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
|
||||
reg_debug_1 = 0x0;
|
||||
reg_debug_2 = 0x0;
|
||||
|
||||
reg_gpio_mode1 = 1;
|
||||
reg_gpio_mode0 = 0; // for full swing
|
||||
|
||||
reg_gpio_ien = 1;
|
||||
reg_gpio_oe = 1;
|
||||
|
||||
reg_debug_1 = 10;
|
||||
for (int i = 0; i < 10; i++) {
|
||||
/* Fast blink for simulation */
|
||||
reg_gpio_out = 1;
|
||||
reg_gpio_out = 0;
|
||||
}
|
||||
reg_debug_1 = 20;
|
||||
for (int i = 0; i < 20; i++) {
|
||||
/* Fast blink for simulation */
|
||||
reg_gpio_out = 1;
|
||||
reg_gpio_out = 0;
|
||||
}
|
||||
reg_debug_1 = 0;
|
||||
reg_debug_1 = 0; // for more delay
|
||||
reg_debug_1 = 0;
|
||||
|
||||
reg_debug_2 = 0xFF; //finish test
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
import random
|
||||
import cocotb
|
||||
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
|
||||
import cocotb.log
|
||||
from cpu import RiskV
|
||||
from defsParser import Regs
|
||||
from cocotb.result import TestSuccess
|
||||
from tests.common_functions.test_functions import *
|
||||
from tests.bitbang.bitbang_functions import *
|
||||
from caravel import GPIO_MODE
|
||||
|
||||
reg = Regs()
|
||||
"""Testbench of GPIO configuration through bit-bang method using the StriVe housekeeping SPI."""
|
||||
@cocotb.test()
|
||||
@repot_test
|
||||
async def temp_partial(dut):
|
||||
caravelEnv = await test_configure(dut,timeout_cycles=70000)
|
||||
# Apply data 0x1809 (management standard output) to first block of
|
||||
# user 1 and user 2 (GPIO 0 and 37) bits 0, 1, 9, and 12 are "1" (data go in backwards)
|
||||
cpu = RiskV(dut)
|
||||
cpu.cpu_force_reset()
|
||||
cpu.cpu_release_reset()
|
||||
|
||||
while True:
|
||||
if cpu.read_debug_reg2() == 0xAA:
|
||||
break
|
||||
await ClockCycles(caravelEnv.clk,1)
|
||||
cpu.cpu_force_reset()
|
||||
|
||||
await ClockCycles(caravelEnv.clk,100)
|
||||
|
||||
await cpu.drive_data2address(reg.get_addr('reg_wb_enable'),1)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_debug_1'),0xAA)
|
||||
# await cpu.drive_data2address(reg.get_addr('reg_debug_2'),0xBB)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_datal'),0x0)
|
||||
|
||||
# await ClockCycles(caravelEnv.clk,100)
|
||||
|
||||
cpu.cpu_release_reset()
|
||||
|
||||
while True:
|
||||
if cpu.read_debug_reg2() == 0xBB:
|
||||
break
|
||||
await ClockCycles(caravelEnv.clk,1)
|
||||
|
||||
await ClockCycles(caravelEnv.clk,100)
|
||||
|
||||
|
|
@ -0,0 +1,103 @@
|
|||
import random
|
||||
import cocotb
|
||||
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
|
||||
import cocotb.log
|
||||
from cpu import RiskV
|
||||
from defsParser import Regs
|
||||
from cocotb.result import TestSuccess
|
||||
from tests.common_functions.test_functions import *
|
||||
from tests.bitbang.bitbang_functions import *
|
||||
from caravel import GPIO_MODE
|
||||
|
||||
reg = Regs()
|
||||
"""Testbench of GPIO configuration through bit-bang method using the StriVe housekeeping SPI."""
|
||||
@cocotb.test()
|
||||
@repot_test
|
||||
async def timer0_oneshot(dut):
|
||||
caravelEnv = await test_configure(dut,timeout_cycles=1000000000)
|
||||
cpu = RiskV(dut)
|
||||
cpu.cpu_force_reset()
|
||||
cpu.cpu_release_reset()
|
||||
cocotb.log.info(f"[TEST] Start timer0_oneshot test")
|
||||
cocotb.log.info(f"[TEST] Configure timer as oneshot")
|
||||
pass_list = (0x1B,0x2B,0x3B)
|
||||
fail_list = (0x1E,0x2E)
|
||||
phases_fails = 3
|
||||
phases_passes = 0
|
||||
reg1 =0 # buffer
|
||||
while True:
|
||||
if cpu.read_debug_reg2() == 0xFF: # test finish
|
||||
break
|
||||
if reg1 != cpu.read_debug_reg1():
|
||||
reg1 = cpu.read_debug_reg1()
|
||||
if reg1 in pass_list: # pass phase
|
||||
phases_passes +=1
|
||||
phases_fails -=1
|
||||
if reg1 == 0x1B:
|
||||
cocotb.log.info(f"[TEST] Pass timer0 value is decreasing")
|
||||
elif reg1 == 0x2B:
|
||||
cocotb.log.info(f"[TEST] Pass timer0 value reach 0")
|
||||
elif reg1 == 0x3B:
|
||||
cocotb.log.info(f"[TEST] Pass timer0 isn't changing after it reachs 0")
|
||||
elif reg1 in fail_list: # pass phase
|
||||
if reg1 == 0x1E:
|
||||
cocotb.log.info(f"[TEST] Failed timer0 value increasing not decresing in oneshot mode")
|
||||
elif reg1 == 0x2E:
|
||||
cocotb.log.error(f"[TEST] Failed timer0 is changing before it reachs 0 in oneshot mode")
|
||||
else:
|
||||
cocotb.log.error(f"[TEST] debug register 1 has illegal value")
|
||||
await ClockCycles(caravelEnv.clk,10)
|
||||
|
||||
if phases_fails != 0:
|
||||
cocotb.log.error(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails")
|
||||
else:
|
||||
cocotb.log.info(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails")
|
||||
|
||||
@cocotb.test()
|
||||
@repot_test
|
||||
async def timer0_periodic(dut):
|
||||
caravelEnv = await test_configure(dut,timeout_cycles=1000000000)
|
||||
cpu = RiskV(dut)
|
||||
cpu.cpu_force_reset()
|
||||
cpu.cpu_release_reset()
|
||||
cocotb.log.info(f"[TEST] Start timer0_periodic test")
|
||||
cocotb.log.info(f"[TEST] Configure timer as periodic")
|
||||
pass_list = (0x1B,0x2B,0x3B,0x4B)
|
||||
fail_list = (0xEE)
|
||||
phases_fails = 4
|
||||
phases_passes = 0
|
||||
reg1 =0 # buffer
|
||||
fourB_happened = False
|
||||
while True:
|
||||
if cpu.read_debug_reg2() == 0xFF: # test finish
|
||||
break
|
||||
if reg1 != cpu.read_debug_reg1():
|
||||
reg1 = cpu.read_debug_reg1()
|
||||
if reg1 in pass_list: # pass phase
|
||||
phases_passes +=1
|
||||
phases_fails -=1
|
||||
if reg1 == 0x1B:
|
||||
cocotb.log.info(f"[TEST] Pass timer0 first rollover")
|
||||
elif reg1 == 0x2B:
|
||||
cocotb.log.info(f"[TEST] Pass timer0 second rollover")
|
||||
elif reg1 == 0x3B:
|
||||
cocotb.log.info(f"[TEST] Pass timer0 third rollover")
|
||||
elif reg1 == 0x4B:
|
||||
if fourB_happened: # this phase happened one time before
|
||||
phases_passes -=1
|
||||
phases_fails +=1
|
||||
else:
|
||||
cocotb.log.info(f"[TEST] Pass timer0 counter value decreases")
|
||||
fourB_happened = True
|
||||
elif reg1 in fail_list: # pass phase
|
||||
if reg1 == 0xEE:
|
||||
cocotb.log.info(f"[TEST] Failed timer0 value hasn't rollovered in periodic mode")
|
||||
else:
|
||||
cocotb.log.error(f"[TEST] debug register 1 has illegal value")
|
||||
|
||||
await ClockCycles(caravelEnv.clk,10)
|
||||
|
||||
if phases_fails != 0:
|
||||
cocotb.log.error(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails")
|
||||
else:
|
||||
cocotb.log.info(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails")
|
||||
|
|
@ -0,0 +1,70 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2020 Efabless Corporation
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
|
||||
#include <defs.h>
|
||||
|
||||
/*
|
||||
Testing timer interrupts
|
||||
Enable interrupt for timer0 and configure it as countdown 1 shot wait for interrupt
|
||||
*/
|
||||
|
||||
|
||||
void main(){
|
||||
uint32_t value;
|
||||
uint32_t old_value;
|
||||
|
||||
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
|
||||
reg_debug_1 = 0x0;
|
||||
reg_debug_2 = 0x0;
|
||||
|
||||
/* Configure timer for a single-shot countdown */
|
||||
reg_timer0_config = 0; // disable
|
||||
reg_timer0_data = 0xF3000;
|
||||
reg_timer0_config = 1; // enable
|
||||
|
||||
// Loop, waiting for the interrupt to change reg_mprj_datah
|
||||
// test path if counter value stop updated after reach 0 and also the value is always decrementing
|
||||
reg_timer0_update = 1; // update reg_timer0_value with new counter value
|
||||
old_value = reg_timer0_value;
|
||||
// value us decrementing until it reachs zero
|
||||
while (1) {
|
||||
reg_timer0_update = 1; // update reg_timer0_value with new counter value
|
||||
value = reg_timer0_value;
|
||||
if (value < old_value && value != 0){
|
||||
reg_debug_1 = 0x1B; // value decrease
|
||||
}
|
||||
else if (value == 0){
|
||||
reg_debug_1 = 0x2B; // value reach 0
|
||||
break;
|
||||
}else{
|
||||
reg_debug_1 = 0x1F; // value updated incorrectly
|
||||
}
|
||||
old_value = value;
|
||||
}
|
||||
// check 10 times that value don't change from 0
|
||||
for (int i = 0; i < 10; i++);
|
||||
reg_timer0_update = 1; // update reg_timer0_value with new counter value
|
||||
|
||||
if (reg_timer0_value == 0){
|
||||
reg_debug_1 = 0x3B; //timer updated correctly
|
||||
}else{
|
||||
reg_debug_1 = 0x2F; //timer updated incorrectly
|
||||
}
|
||||
reg_debug_2 = 0xFF; // finish test
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,73 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2020 Efabless Corporation
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <defs.h>
|
||||
|
||||
/*
|
||||
Testing timer interrupts
|
||||
Enable interrupt for timer0 and configure it as countdown 1 shot
|
||||
wait for interrupt
|
||||
|
||||
*/
|
||||
|
||||
|
||||
void main(){
|
||||
uint32_t value;
|
||||
uint32_t old_value;
|
||||
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
|
||||
reg_debug_1 = 0x0;
|
||||
reg_debug_2 = 0x0;
|
||||
/* Configure timer for a single-shot countdown */
|
||||
reg_timer0_config = 0; // disable
|
||||
reg_timer0_data = 0;
|
||||
reg_timer0_data_periodic = 0x300;
|
||||
reg_timer0_config = 1; // enable
|
||||
|
||||
// Loop, waiting for the interrupt to change reg_mprj_datah
|
||||
// test path if counter value stop updated after reach 0 and also the value is always decrementing
|
||||
reg_timer0_update = 1; // update reg_timer0_value with new counter value
|
||||
old_value = reg_timer0_value;
|
||||
// value us decrementing until it reachs zero
|
||||
int rollover = 0;
|
||||
int timeout = 400;
|
||||
for (int i = 0; i < timeout; i++){
|
||||
reg_timer0_update = 1; // update reg_timer0_value with new counter value
|
||||
value = reg_timer0_value;
|
||||
if (value > old_value){
|
||||
rollover++;
|
||||
if (rollover==1)
|
||||
reg_debug_1 = 0x1B; // timer rollover
|
||||
else if (rollover==2)
|
||||
reg_debug_1 = 0x2B; //timer rollover second time
|
||||
else if (rollover==3){
|
||||
reg_debug_1 = 0x3B; //timer rollover second time
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (value < old_value){
|
||||
reg_debug_1 = 0x4B; // value decreases
|
||||
}
|
||||
old_value = value;
|
||||
}
|
||||
|
||||
if (rollover ==0){
|
||||
reg_debug_1 = 0xEE; // counter didn't rollover
|
||||
}
|
||||
reg_debug_2 = 0xFF; // finish test
|
||||
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,56 @@
|
|||
from curses import baudrate
|
||||
import random
|
||||
import cocotb
|
||||
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles,Timer
|
||||
import cocotb.log
|
||||
from cpu import RiskV
|
||||
from defsParser import Regs
|
||||
from cocotb.result import TestSuccess
|
||||
from tests.common_functions.test_functions import *
|
||||
from tests.bitbang.bitbang_functions import *
|
||||
from caravel import GPIO_MODE
|
||||
|
||||
baud_rate = 9600
|
||||
number_of_bits = 8
|
||||
bit_rate_ns = round((10**9)/(baud_rate*number_of_bits) )
|
||||
|
||||
reg = Regs()
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
@repot_test
|
||||
async def uart_tx(dut):
|
||||
caravelEnv = await test_configure(dut,timeout_cycles=18613481)
|
||||
cpu = RiskV(dut)
|
||||
cpu.cpu_force_reset()
|
||||
cpu.cpu_release_reset()
|
||||
cocotb.log.info(f"[TEST] Start uart test")
|
||||
expected_data = "Monitor: Test UART (RTL) passed"
|
||||
|
||||
await wait_reg1(cpu,caravelEnv,0XAA)
|
||||
|
||||
cocotb.log.info (f"[TEST] start sending on uart")
|
||||
counter =0
|
||||
data_out =''
|
||||
while True:
|
||||
if counter %8 == 0:
|
||||
if counter != 0:
|
||||
data_out = data_out+chr(int(char,2))
|
||||
cocotb.log.info (f"[TEST] msg is:'{data_out}' expected '{expected_data}'")
|
||||
if data_out == expected_data:
|
||||
cocotb.log.info (f"[TEST] Pass recieve the full expected msg '{data_out}'")
|
||||
break
|
||||
await start_of_tx(caravelEnv)
|
||||
char = ''
|
||||
# if temp != caravelEnv.monitor_gpio((6,6))
|
||||
char = caravelEnv.monitor_gpio((6,6)).binstr + char
|
||||
cocotb.log.debug (f"[TEST] bit[{counter}] = {caravelEnv.monitor_gpio((6,6))} data out = {char} ")
|
||||
await Timer(bit_rate_ns, units='ns')
|
||||
counter +=1
|
||||
|
||||
async def start_of_tx(caravelEnv):
|
||||
while (True): # wait for the start of the transimission it 1 then 0
|
||||
if (caravelEnv.monitor_gpio((6,6)).integer == 0):
|
||||
break
|
||||
await Timer(bit_rate_ns, units='ns')
|
||||
await Timer(bit_rate_ns, units='ns')
|
||||
|
|
@ -0,0 +1,53 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2020 Efabless Corporation
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <defs.h>
|
||||
#include <stub.c>
|
||||
|
||||
// --------------------------------------------------------
|
||||
|
||||
void main()
|
||||
{
|
||||
int j;
|
||||
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
|
||||
reg_debug_1 = 0x0;
|
||||
reg_debug_2 = 0x0;
|
||||
|
||||
reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
|
||||
// Set clock to 64 kbaud and enable the UART. It is important to do this
|
||||
// before applying the configuration, or else the Tx line initializes as
|
||||
// zero, which indicates the start of a byte to the receiver.
|
||||
|
||||
|
||||
// Now, apply the configuration
|
||||
reg_mprj_xfer = 1;
|
||||
while (reg_mprj_xfer == 1);
|
||||
|
||||
// reg_uart_clkdiv = 625;
|
||||
reg_uart_enable = 1;
|
||||
|
||||
reg_debug_1 = 0xAA;
|
||||
// This should appear at the output, received by the testbench UART.
|
||||
// (Makes simulation time long.)
|
||||
// print("test msg\n");
|
||||
print("Monitor: Test UART (RTL) passed");
|
||||
|
||||
// Allow transmission to complete before signalling that the program
|
||||
// has ended.
|
||||
for (j = 0; j < 160; j++);
|
||||
}
|
||||
|
|
@ -0,0 +1,157 @@
|
|||
|
||||
from fnmatch import fnmatch
|
||||
import cocotb
|
||||
from cocotb.triggers import Timer, FallingEdge,RisingEdge, ReadOnly
|
||||
from cocotb_bus.monitors import Monitor
|
||||
from cocotb.log import SimLogFormatter, SimTimeContextFilter
|
||||
from cocotb.binary import BinaryValue
|
||||
from cocotb.result import TestFailure
|
||||
from math import ceil
|
||||
import copy
|
||||
import logging
|
||||
from wb_models.housekeepingWB.HKmonitor import HKmonitor
|
||||
from common import Macros
|
||||
|
||||
|
||||
class HKSPImonitor(Monitor):
|
||||
"""Observes single input """
|
||||
def __init__(self, name, block_path,interfaces, clock,reset,is_logger = False, input=True, callback=None, event=None):
|
||||
self.name = name
|
||||
self.interfaces = interfaces
|
||||
self.clock = clock
|
||||
self.reset = reset
|
||||
self.block_path = block_path
|
||||
self.is_logger = is_logger
|
||||
self.input = input
|
||||
self.setup_logger()
|
||||
Monitor.__init__(self, callback, event)
|
||||
|
||||
|
||||
async def _monitor_recv(self):
|
||||
old_trans_hold = None
|
||||
old_trans_no_valid = None
|
||||
while True:
|
||||
if Macros['GL']:
|
||||
await RisingEdge(self.block_path.clknet_0_mgmt_gpio_in) # the main reason for doing all this can't use mgmt_gpio_in[4] as signal
|
||||
else :
|
||||
await RisingEdge(self.block_path.hkspi.SCK) # the main reason for doing all this can't use mgmt_gpio_in[4] as signal
|
||||
cocotb.log.debug(f'reset {self.reset.value.binstr }')
|
||||
|
||||
if self.reset.value.binstr == '0':
|
||||
continue
|
||||
|
||||
mgmt_gpio_in = self.block_path.mgmt_gpio_in.value
|
||||
gpio_size = mgmt_gpio_in.n_bits-1
|
||||
CSB = mgmt_gpio_in[gpio_size-3]
|
||||
if CSB.binstr == '1':
|
||||
continue
|
||||
SCK = mgmt_gpio_in[gpio_size-4]
|
||||
SDI = mgmt_gpio_in[gpio_size-2]
|
||||
SDO = self.block_path.mgmt_gpio_out.value[gpio_size-1]
|
||||
if not self.input:
|
||||
if self.block_path.hkspi.SCK.value.binstr != '0':
|
||||
continue
|
||||
# update signal
|
||||
self.interfaces['CSB']['val'] = CSB
|
||||
self.interfaces['SCK']['val'] = SCK
|
||||
|
||||
if self.input:
|
||||
self.interfaces['SDI']['val'] = SDI
|
||||
else :
|
||||
self.interfaces['SDO']['val'] = SDO
|
||||
|
||||
# logger
|
||||
self.logger.debug(f' ')
|
||||
self.handler.terminator = ""
|
||||
self.handler.setFormatter(SimLogFormatter())
|
||||
self.logger.debug(f'')
|
||||
self.handler.setFormatter(logging.Formatter('%(message)s'))
|
||||
for key2,signal in self.interfaces.items():
|
||||
if fnmatch(key2,"_*"):
|
||||
continue
|
||||
if signal['val'].is_resolvable:
|
||||
length = self.lengths[key2] - (len(hex(signal['val'].integer)))
|
||||
self.logger.debug(f" {hex(signal['val'].integer)}{' '*length}|")
|
||||
# signal['val'] = self.block_path._id(signal['signal'],False).value.integer
|
||||
else:
|
||||
length = self.lengths[key2] - (len('x'))
|
||||
self.logger.debug(f" x{' '*length}|")
|
||||
self.handler.terminator = "\n"
|
||||
self._recv(self.interfaces)
|
||||
|
||||
|
||||
|
||||
|
||||
"""method for setting up logger for WB model"""
|
||||
def setup_logger(self):
|
||||
self.logger = logging.getLogger(f'HouseKeeping{self.name}')
|
||||
self.logger.setLevel(logging.DEBUG)
|
||||
if not self.is_logger:
|
||||
self.logger.setLevel(logging.INFO)
|
||||
self.handler = logging.StreamHandler()
|
||||
# return
|
||||
else :
|
||||
self.handler = logging.FileHandler(f"{self.name}.log",mode='w')
|
||||
self.handler.addFilter(SimTimeContextFilter())
|
||||
self.logger.addHandler(self.handler)
|
||||
# get the sizes of signals
|
||||
#for key,interface in self.interfaces.items():
|
||||
for key,signal in self.interfaces.items():
|
||||
if fnmatch(key,"_*"):
|
||||
continue
|
||||
signal['val'] = BinaryValue(value=0,n_bits=1)
|
||||
size = signal['val'].n_bits
|
||||
signal['val'] = BinaryValue(value = int(size) * '1',n_bits=size)
|
||||
# set the logger file header
|
||||
# set first line
|
||||
self.handler.terminator = ""
|
||||
self.logger.debug(f' timestamp level ')
|
||||
length =0
|
||||
for key2,signal in self.interfaces.items():
|
||||
if fnmatch(key2,"_*"):
|
||||
continue
|
||||
length += max(ceil(signal['val'].n_bits/4)+2 , len(key2)) +3
|
||||
length -= len(key)+1
|
||||
self.logger.debug(f'| signals{" "*int(length)}')
|
||||
self.handler.terminator = "\n"
|
||||
self.logger.debug(f' ')
|
||||
# set second line
|
||||
self.handler.terminator = ""
|
||||
self.logger.debug(f'{" "*20}|')
|
||||
length =0
|
||||
self.lengths = dict()
|
||||
for key2,signal in self.interfaces.items():
|
||||
if fnmatch(key2,"_*"):
|
||||
continue
|
||||
self.lengths[key2] = max((len(hex(signal['val'].integer))),len(key2)) +1
|
||||
length = self.lengths[key2] - len(key2)
|
||||
self.logger.debug(f'{key2}{" "*length} ')
|
||||
self.handler.terminator = "\n"
|
||||
|
||||
|
||||
|
||||
class CSBmonitor(Monitor):
|
||||
"""Observes single input """
|
||||
def __init__(self, name, block_path,interfaces, clock,reset,is_logger = False, input=True, callback=None, event=None):
|
||||
self.name = name
|
||||
self.interfaces = interfaces
|
||||
self.clock = clock
|
||||
self.reset = reset
|
||||
self.block_path = block_path
|
||||
self.is_logger = is_logger
|
||||
self.input = input
|
||||
Monitor.__init__(self, callback, event)
|
||||
|
||||
|
||||
async def _monitor_recv(self):
|
||||
|
||||
while True:
|
||||
if Macros['GL']:
|
||||
await RisingEdge(self.block_path.net67)
|
||||
else:
|
||||
await RisingEdge(self.block_path.hkspi.CSB)
|
||||
|
||||
self._recv(True)
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,371 @@
|
|||
from audioop import add
|
||||
from ctypes import BigEndianStructure
|
||||
from operator import truediv
|
||||
from cocotb import top
|
||||
import cocotb
|
||||
from cocotb.binary import BinaryValue
|
||||
from cocotb.triggers import Timer, RisingEdge, ReadOnly
|
||||
import fnmatch
|
||||
import copy
|
||||
import logging
|
||||
from cocotb.result import TestFailure
|
||||
from cocotb_coverage.coverage import *
|
||||
|
||||
class HK_models():
|
||||
def __init__(self,reg_model,expeceted_output,hk_hdl):
|
||||
self.reg_model = reg_model
|
||||
self.expeceted_output = expeceted_output
|
||||
self.hk_hdl = hk_hdl
|
||||
self.old_hold_val = 1
|
||||
self.gpio_out_pre = BinaryValue(value=0,n_bits=38,bigEndian=False)
|
||||
self.mgmt_gpio_oeb = BinaryValue(value=0,n_bits=38,bigEndian=False)
|
||||
self.exp_out_wb = [] # expected output for wishbone
|
||||
self.exp_out_uart_rx = [self.expeceted_output['UART']] # expected output for uart
|
||||
self.exp_out_debug = [self.expeceted_output['debug']] # expected output for
|
||||
self.exp_out_spi = [self.expeceted_output['SPI']] # expected output for
|
||||
self.reset_spi_vals(True)
|
||||
self.input_dis =3
|
||||
self.regs_full_list()
|
||||
self.intial_cov()
|
||||
|
||||
|
||||
|
||||
"""model for the wishbone interface with housekeeping"""
|
||||
def wishbone_model(self,trans):
|
||||
clock_signal = trans["_clk"]["signal"]
|
||||
if trans["stb"]["val"] == 1 : # valid data
|
||||
address = trans["adr"]["val"]
|
||||
data = trans["data"]["val"]
|
||||
# if ack isn't realsead don't care about the new input it must be the same as the old and the monitor checks that
|
||||
if (self.old_hold_val == 0):
|
||||
self.old_hold_val = trans["_hold"]["val"]
|
||||
return
|
||||
self.old_hold_val = trans["_hold"]["val"]
|
||||
if trans["write_en"]["val"] ==1 : # write cycle
|
||||
cocotb.log.debug(f'[HK_models][_valid_address] write enable for address: {hex(address)} and data: {hex(data)} ')
|
||||
select = trans["sel"]["val"]
|
||||
cocotb.scheduler.add(self._write_reg_wb(address,data,select,clock_signal))
|
||||
else: #read cycle
|
||||
self.write_exp_out_wb(self._read_reg_wb(address))
|
||||
self.wishbone_last_trans = trans
|
||||
|
||||
"""model for the system interface with housekeeping"""
|
||||
def system_model(self,trans):
|
||||
self.reg_model['sys']['0x00'][0][6] = trans["vdd2_good"]["val"]
|
||||
self.reg_model['sys']['0x00'][1][6] = trans["vdd1_good"]["val"]
|
||||
self.reg_model['sys']['0x00'][2][6] = trans["vcc2_good"]["val"]
|
||||
self.reg_model['sys']['0x00'][3][6] = trans["vcc1_good"]["val"]
|
||||
|
||||
|
||||
"""model for the UART interface with housekeeping"""
|
||||
def UART_model(self,trans):
|
||||
# when transmiting TX the gpio data out should change to the tx value
|
||||
if trans["enable"]["val"]:
|
||||
self.gpio_out_pre[6]= trans["TX"]["val"].value
|
||||
else:
|
||||
gpio_data = self._read_reg_keys(["GPIO","0x0c"]) # mgmt_gpio_data[7:0]
|
||||
self.gpio_out_pre[6]= int(gpio_data[len(gpio_data)-1 -6]) # mgmt_gpio_data[6]
|
||||
# predecting the rx output value when the value UART is enble is the value drom pin [5]
|
||||
gpio_in_size = trans["gpio_in"]["val"].n_bits -1
|
||||
output = self.expeceted_output['UART']
|
||||
output["RX"]["val"] = 0
|
||||
if trans["enable"]["val"]:
|
||||
output["RX"]["val"] = trans["gpio_in"]["val"][gpio_in_size-5] #gpio_in[5]
|
||||
self.exp_out_uart_rx.append(output)
|
||||
|
||||
|
||||
"""model for the debug interface with housekeeping"""
|
||||
def debug_model(self,trans):
|
||||
# when debug is enable gpio out [0] should follow debug_out
|
||||
if trans["enable"]["val"]:
|
||||
self.gpio_out_pre[0] = trans["data"]["val"].value
|
||||
self.mgmt_gpio_oeb[0] = trans["data"]["val"].value
|
||||
else:
|
||||
gpio_data = self._read_reg_keys(["GPIO","0x0c"]) # mgmt_gpio_data[7:0]
|
||||
self.gpio_out_pre[0]= int(gpio_data[len(gpio_data)-1 -0]) # mgmt_gpio_data[6]
|
||||
gpio_data_en = self._read_reg_keys(["GPIO","0x24"]) # gpio_configure[0][7:0]
|
||||
self.mgmt_gpio_oeb[0]= 1- int(gpio_data[len(gpio_data_en)-1 -self.input_dis]) # gpio_configure[0][3]
|
||||
|
||||
# predecting the debug in signal when debug mode is enbled taking the value from pin [0]
|
||||
gpio_in_size = trans["gpio_in"]["val"].n_bits -1
|
||||
output = self.expeceted_output['debug']
|
||||
output["data"]["val"] = 0
|
||||
if trans["enable"]["val"]:
|
||||
output["data"]["val"] = trans["gpio_in"]["val"][gpio_in_size-0] # mgmt_gpio_in[0]
|
||||
self.exp_out_debug.append(output)
|
||||
|
||||
"""model for the SPI interface with housekeeping"""
|
||||
def spi_model(self,trans):
|
||||
output = self.expeceted_output['SPI']
|
||||
output["SDO"]["val"] = 0
|
||||
cocotb.log.debug(f'[HK_models][spi_model] spi mode {self.spi_mode[0]} bit number {self.spi_mode[1]} command = {self.command_spi} address = {self.address_spi} write = {self.write_spi} stream = {self.spi_mode[2]}')
|
||||
if self.spi_mode[0] == "command":
|
||||
self._setCommand(trans['SDI']['val'].binstr)
|
||||
self.exp_out_spi.append(output)
|
||||
elif self.spi_mode[0] == "address":
|
||||
self._setAddress(trans['SDI']['val'].binstr)
|
||||
self.exp_out_spi.append(output)
|
||||
elif self.spi_mode[0] == "write":
|
||||
self._setWriteData(trans['SDI']['val'].binstr)
|
||||
self.exp_out_spi.append(output)
|
||||
elif self.spi_mode[0] == "read":
|
||||
output["SDO"]["val"] = self._getReadData()
|
||||
self.exp_out_spi.append(output)
|
||||
elif self.spi_mode[0] == "read/write":
|
||||
output["SDO"]["val"] = self._getReadData()
|
||||
self.exp_out_spi.append(output)
|
||||
elif self.spi_mode[0] == "noOP":
|
||||
self._setWriteData(trans['SDI']['val'].binstr)
|
||||
else:
|
||||
raise TestFailure("[HK_models][spi_model] invalid command type")
|
||||
|
||||
|
||||
"""reset the spi vals when CSB is going from low to high"""
|
||||
def reset_spi_vals(self,trans):
|
||||
cocotb.log.info(f"[HK_models][reset_spi_vals] CSB is disabled")
|
||||
self.spi_mode = ["command",0,0] # [mode type, bit number, stream number]
|
||||
self.command_spi = ['0']*8
|
||||
self.address_spi = ['0']*8
|
||||
self.write_spi = ['0']*8
|
||||
self.read_spi = ['0']*8
|
||||
|
||||
def _setCommand(self,bit):
|
||||
if bit not in ['0','1']:
|
||||
cocotb.log.warning(f"[HK_models][_setCommand] incorrect bit size bit = {bit}")
|
||||
self.command_spi[self.spi_mode[1]] = bit
|
||||
self.spi_mode[1] += 1
|
||||
self.spi_mode[2] = 0 # stream number
|
||||
if self.spi_mode[1] >= 8:
|
||||
self.spi_mode[0] = "address"
|
||||
self.spi_mode[1] = 0
|
||||
|
||||
def _setAddress(self,bit):
|
||||
if bit not in ['0','1']:
|
||||
cocotb.log.warning(f"[HK_models][_setAddress] incorrect bit size bit = {bit}")
|
||||
self.address_spi[self.spi_mode[1]] = bit
|
||||
self.spi_mode[1] += 1
|
||||
self.spi_mode[2] = 0 # stream number
|
||||
if self.spi_mode[1] >= 8:
|
||||
self.spi_mode[1] = 0
|
||||
if self.command_spi[0:2] == ['0','0']:
|
||||
self.spi_mode[0] = "noOP"
|
||||
if self.command_spi[0:2] == ['1','0']:
|
||||
self.spi_mode[0] = "write"
|
||||
if self.command_spi[0:2] == ['0','1']:
|
||||
self.spi_mode[0] = "read"
|
||||
if self.command_spi[0:2] == ['1','1']:
|
||||
self.spi_mode[0] = "read/write"
|
||||
|
||||
def _setWriteData(self,bit):
|
||||
if bit not in ['0','1']:
|
||||
cocotb.log.warning(f"[HK_models][_setWriteData] incorrect bit size bit = {bit}")
|
||||
# return if write is write n-bytes command and number of bytes exceeds the required
|
||||
if self.command_spi[2:5] != ['0','0','0']:
|
||||
self.spi_mode_cov('write-n')
|
||||
byte_num = int(''.join(self.command_spi[2:5]),2)
|
||||
if byte_num <= self.spi_mode[2]: #number of written byte <= stream number
|
||||
self.spi_mode[0] = "noOP"
|
||||
return
|
||||
else: self.spi_mode_cov('write')
|
||||
self.write_spi[self.spi_mode[1]] = bit
|
||||
self.spi_mode[1] += 1
|
||||
if self.spi_mode[1] >= 8:
|
||||
self.spi_mode[1] = 0
|
||||
address = int(''.join(self.address_spi),2) + self.spi_mode[2]
|
||||
data = ''.join(self.write_spi)
|
||||
data = BinaryValue(value = data, n_bits =8)
|
||||
is_valid, keys=self._valid_address_spi(address)
|
||||
if is_valid:
|
||||
self.reg_cov(keys[0],keys[1],is_read=False)
|
||||
cocotb.log.debug(f'[HK_models][_valid_address] writing {data} to memory:{keys[0]} field: {keys[1]} through housekeeping SPI address = {address}')
|
||||
self._write_fields(keys,data)
|
||||
if self.command_spi[2:5] != ['0','0','0']:self.spi_mode_cov('write-n')
|
||||
else: self.spi_mode_cov('write')
|
||||
self.spi_mode[2] += 1 # stream number
|
||||
|
||||
|
||||
def _getReadData(self):
|
||||
# return if write is write n-bytes command and number of bytes exceeds the required
|
||||
if self.command_spi[2:5] != ['0','0','0']:
|
||||
byte_num = int(''.join(self.command_spi[2:5]),2)
|
||||
if byte_num <= self.spi_mode[2]: #number of written byte <= stream number
|
||||
self.spi_mode[0] = "noOP"
|
||||
return
|
||||
bit_num = self.spi_mode[1]
|
||||
address = int(''.join(self.address_spi),2) + self.spi_mode[2]
|
||||
is_valid, keys=self._valid_address_spi(address)
|
||||
data = ''
|
||||
if is_valid:
|
||||
self.reg_cov(keys[0],keys[1])
|
||||
cocotb.log.info(f'[HK_models][_getReadData] reading from memory:{keys[0]} field: {keys[1]} through SPI')
|
||||
for field in self.reg_model[keys[0]][keys[1]]:
|
||||
data = str(bin(field[6])[2:]).zfill(field[3]) + data
|
||||
data = data.zfill(8)
|
||||
cocotb.log.info(f'[HK_models][_getReadData] reading from memory:{keys[0]} field: {keys[1]} through SPI data {data} bit[{7-bit_num}] = {data[bit_num]}')
|
||||
|
||||
self.spi_mode[1] += 1
|
||||
if self.spi_mode[1] >= 8:
|
||||
self.spi_mode[1] = 0
|
||||
self.spi_mode[2] += 1 # stream number
|
||||
if self.command_spi[2:5] != ['0','0','0']:self.spi_mode_cov('read-n')
|
||||
else: self.spi_mode_cov('read')
|
||||
|
||||
if data == '':
|
||||
return 0
|
||||
return int(data[bit_num],2)
|
||||
|
||||
|
||||
def write_exp_out_wb(self,data):
|
||||
output = self.expeceted_output['wishbone']
|
||||
output['ack']['val'] = 1
|
||||
output['_valid_cycle']['val'] = 1
|
||||
output['data']['val'] = BinaryValue(value = data,n_bits = 32,bigEndian=False)
|
||||
self.exp_out_wb.append(output)
|
||||
|
||||
"""write register through wishbone """
|
||||
async def _write_reg_wb(self,address,data,select,clk):
|
||||
old_data = self._read_reg_wb(address)
|
||||
self.write_exp_out_wb(old_data)
|
||||
|
||||
if address == 0x2600000c: # mgmt_gpio_data is a special case as it got written completely at the end of the serial writing
|
||||
for i in range(6):
|
||||
await RisingEdge(self.hk_hdl._id(clk,False))
|
||||
|
||||
for i in range(3):
|
||||
await RisingEdge(self.hk_hdl._id(clk,False))
|
||||
|
||||
for i,sel in enumerate(select.binstr):
|
||||
temp_addr = BinaryValue(value=(address.value +i))
|
||||
if sel is '1':
|
||||
is_valid, keys=self._valid_address(temp_addr)
|
||||
if is_valid:
|
||||
self.reg_cov(keys[0],keys[1],is_SPI=False,is_read=False)
|
||||
cocotb.log.debug(f'[HK_models][_valid_address] writing {data[(8*((4-i-1))):8*(4-i)-1]} to memory:{keys[0]} field: {keys[1]}')
|
||||
temp_data = data[(8*((4-i-1))):8*(4-i)-1]
|
||||
self._write_fields(keys,temp_data)
|
||||
cocotb.log.debug(f" [HK_models][_valid_address] address {hex(address)} used for access housekeeping memory success")
|
||||
if address != 0x2600000c:
|
||||
for i in range(2):
|
||||
await RisingEdge(self.hk_hdl._id(clk,False))
|
||||
|
||||
def _write_fields(self,keys,data):
|
||||
for field in self.reg_model[keys[0]][keys[1]]:
|
||||
if field[4] == "RW":
|
||||
shift = field[2]
|
||||
size = field[3]
|
||||
cocotb.log.debug(f'[HK_models][_write_fields] before update field : {field[1]} data = {bin(field[6])} with data {data[shift:shift+size-1]} ')
|
||||
field[6] = data[8-shift-size:8-shift-1]
|
||||
cocotb.log.debug(f'[HK_models][_write_fields] after update field : {field[1]} data = {bin(field[6])} with data {data[shift:shift+size-1]} ')
|
||||
"""read register value using keys return size binary value"""
|
||||
def _read_reg_keys(self,keys:list):
|
||||
size =0
|
||||
data = ""
|
||||
for field in self.reg_model[keys[0]][keys[1]]:
|
||||
size += field[3]
|
||||
data += bin(field[6])[2:].zfill(size)
|
||||
return data
|
||||
|
||||
|
||||
"""read register through wishbone """
|
||||
def _read_reg_wb(self,address):
|
||||
total_size = 32
|
||||
data_string ="0"
|
||||
data_out = list(bin(0)[2:].zfill(total_size))
|
||||
for i in range(4):
|
||||
temp_addr = BinaryValue(value=(address.value +i))
|
||||
is_valid, keys=self._valid_address(temp_addr)
|
||||
if is_valid:
|
||||
self.reg_cov(keys[0],keys[1],is_SPI=False)
|
||||
for field in self.reg_model[keys[0]][keys[1]]:
|
||||
shift = field[2]
|
||||
size = field[3]
|
||||
first_index = ((8 *(4-i))) - shift-size
|
||||
second_index = ((8 *(4-i))) - shift
|
||||
data = bin(field[6])[2:].zfill(size)
|
||||
cocotb.log.debug(f"[HK_models][_read_reg] memory:{keys[0]} shift:{keys[1]} field:{field[0]} data:{data} ")
|
||||
for k,j in enumerate(range(first_index, second_index, 1)):
|
||||
data_out[j] = data[k]
|
||||
data_string = "".join(data_out)
|
||||
cocotb.log.debug(f"[HK_models][_read_reg] register {hex(address)} has value {hex(int(data_string,2))} ")
|
||||
return int(data_string,2)
|
||||
|
||||
"""return false if the address isn't exist inside housekeeping if the address exist return true and the key of address in JSON file"""
|
||||
def _valid_address(self,address):
|
||||
size = max(len(address),32)
|
||||
address = address.binstr.zfill(size)
|
||||
for key,memory in self.reg_model.items():
|
||||
if fnmatch.fnmatch(key, "_*") :
|
||||
continue
|
||||
# remove the first 2 element 0b and
|
||||
base_addr= bin(memory["base_addr"][1])[2:].zfill(size)
|
||||
cocotb.log.debug(f'[HK_models][_valid_address] base address[:13]={hex(int(base_addr[size-32:size-13],2))} target address[:13]={hex(int(address[size-32:size-13],2))} shift={"{0:#0{1}x}".format(int(address[size-12:],2),4)}')
|
||||
if base_addr[size-32:size-13] == address[size-32:size-13]:
|
||||
if "{0:#0{1}x}".format(int(address[size-12:],2),4) in memory:
|
||||
cocotb.log.debug(f'[HK_models][_valid_address] base address={hex(int(base_addr,2))} key {key}')
|
||||
return True, [key,"{0:#0{1}x}".format(int(address[size-12:],2),4)]
|
||||
cocotb.log.warning(f"[HK_models][_valid_address] address {hex(int(address,2))} used for access housekeeping memory isn't valid")
|
||||
return False, None
|
||||
|
||||
"""return false if the address isn't exist inside housekeeping if the address exist return true and the key of address in JSON file"""
|
||||
def _valid_address_spi(self,address):
|
||||
for key,memory in self.reg_model.items():
|
||||
if fnmatch.fnmatch(key, "_*") :
|
||||
continue
|
||||
for key2,reg in memory.items():
|
||||
if key2 == "base_addr" :
|
||||
continue
|
||||
for field in reg:
|
||||
if field[7] == address:
|
||||
return True,[key,key2]
|
||||
cocotb.log.warning(f"[HK_models][_valid_address_spi] address {hex(address)} for SPI housekeeping isn't valid")
|
||||
return False, None
|
||||
|
||||
|
||||
######################## coverage ############################
|
||||
def regs_full_list(self):
|
||||
bins = list()
|
||||
labels = list()
|
||||
for key,mem in self.reg_model.items():
|
||||
if fnmatch.fnmatch(key, "_*"):
|
||||
continue
|
||||
for key2,fields in mem.items():
|
||||
if key2=='base_addr':
|
||||
continue
|
||||
bins.append((key,key2))
|
||||
labels.append((self.reg_model[key][key2][0][0]))
|
||||
self.reg_bins = bins
|
||||
self.reg_labels = labels
|
||||
def intial_cov(self):
|
||||
for i in [True,False]:
|
||||
for j in [True,False]:
|
||||
self.reg_cov(0,0,i,j)
|
||||
self.spi_mode_cov(0)
|
||||
|
||||
def reg_cov(self,key1,key2,is_SPI=True,is_read=True):
|
||||
s=''
|
||||
if is_SPI:
|
||||
s = "spi."
|
||||
else:
|
||||
s="wishbone."
|
||||
if is_read:
|
||||
s +="read"
|
||||
else:
|
||||
s+= "write"
|
||||
@CoverPoint(f"top.caravel.housekeeping.regs.{s}",
|
||||
xf = lambda key1,key2:(key1,key2),
|
||||
bins = self.reg_bins,
|
||||
bins_labels=self.reg_labels)
|
||||
def cov(key1,key2):
|
||||
pass
|
||||
cov(key1,key2)
|
||||
return (key1,key2)
|
||||
|
||||
|
||||
def spi_mode_cov(self,mode):
|
||||
@CoverPoint(f"top.caravel.housekeeping.spi.modes",
|
||||
bins = ['noOP','write','read','read/write','write-n','read-n','read/write-n','Pass-m','pass-u'],
|
||||
bins_labels=['No operation','Write in streaming mode','Read in streaming mode','Simultaneous Read/Write in streaming mode','Write in n-byte mode','Read in n-byte mode','Simultaneous Read/Write in n-byte mode','Pass-through (management) Read/Write streaming mode','Pass-through (user) Read/Write in streaming mode' ])
|
||||
def cov(mode):
|
||||
pass
|
||||
cov(mode)
|
||||
return mode
|
||||
|
|
@ -0,0 +1,129 @@
|
|||
{
|
||||
"_comment": "the list contain the fields in register with shift spcified [field name,name iniside housekeeping, shift, size,mode,reset,value(intial is reset value), SPI address map] the shift is from the base address like SPI, system and gpio base address",
|
||||
"_comment2": "Base address is the first element and called first address",
|
||||
|
||||
|
||||
"SPI":{ "base_addr": ["SPI_BASE_ADR",638582784],
|
||||
"0x00": [["SPI status",null,0,8,"undefined",0,0,0]],
|
||||
"0x06": [["Manufacturer ID",["mfgr_id",11,8],0,4,"RO",4,4,1]],
|
||||
"0x05": [["Manufacturer ID",["mfgr_id",7,0],0,8,"RO",86,86,2]],
|
||||
"0x04": [["Manufacturer ID",["prod_id",7,0],0,8,"RO",17,17,3]],
|
||||
"0x0b": [["User project ID",["mask_rev",31,24],0,8,"RO",0,0,4]],
|
||||
"0x0a": [["User project ID",["mask_rev",23,16],0,8,"RO",0,0,5]],
|
||||
"0x09": [["User project ID",["mask_rev",15,8],0,8,"RO",0,0,6]],
|
||||
"0x08": [["User project ID",["mask_rev",7,0],0,8,"RO",0,0,7]],
|
||||
"0x0c": [["PLL enables","pll_ena",0,1,"RW",0,0,8],["PLL DCO enables","pll_dco_ena",1,1,"RW",1,1,8]],
|
||||
"0x10": [["PLL bypass","pll_bypass",0,1,"RW",1,1,9]],
|
||||
"0x14": [["CPU IRQ","irq_spi",0,1,"RW",0,0,10]],
|
||||
"0x18": [["CPU reset","reset_reg",0,1,"RW",0,0,11]],
|
||||
"0x28": [["CPU trap","trap",0,1,"RW",0,0,12]],
|
||||
"0x1c": [["DCO trim",["pll_trim",7,0],0,8,"RW",255,255,13]],
|
||||
"0x1d": [["DCO trim",["pll_trim",15,8],0,8,"RW",239,239,14]],
|
||||
"0x1e": [["DCO trim",["pll_trim",23,16],0,8,"RW",255,255,15]],
|
||||
"0x1f": [["DCO trim",["pll_trim",25,24],0,2,"RW",3,3,16]],
|
||||
"0x20": [["PLL output divider","pll_sel",0,3,"RW",2,2,17],["PLL output divider 2","pll90_sel",3,3,"RW",2,2,17]],
|
||||
"0x24": [["PLL feedback divider","pll_div",0,5,"RW",4,4,18]],
|
||||
"0x34": [["SRAM read-only control","sram_ro_csb",0,1,"RW",1,1,20],["SRAM read-only control","sram_ro_clk",0,1,"RW",0,0,20]],
|
||||
"0x30": [["SRAM read-only address","sram_ro_addr",0,8,"RW",0,0,21]]
|
||||
},
|
||||
|
||||
"GPIO":{ "base_addr": ["GPIO_BASE_ADR",637534208],
|
||||
"0x00": [["xfer","serial_xfer",0,1,"RW",0,0,19],["bit bang enable","serial_bb_enable",1,1,"RW",0,0,19],
|
||||
["bit bang reset","serial_bb_resetn",2,1,"RW",0,0,19],["bit bang load","serial_bb_load",3,1,"RW",0,0,19],
|
||||
["bit bang clock","serial_bb_clock",4,1,"RW",0,0,19],["bit bang data1","serial_bb_data_1",5,1,"RW",0,0,19],
|
||||
["bit bang data1","serial_bb_data_2",6,1,"RW",0,0,19]],
|
||||
"0x04": [["GPIO power control (reg_mprj_pwr)","pwr_ctrl_out",0,4,"RW",0,0,110]],
|
||||
"0x0c": [["GPIO data low(reg_mprj_datal)",["mgmt_gpio_data",7,0],0,8,"RW",0,0,109]],
|
||||
"0x0d": [["GPIO data low(reg_mprj_datal)",["mgmt_gpio_data",15,8],0,8,"RW",0,0,108]],
|
||||
"0x0e": [["GPIO data low(reg_mprj_datal)",["mgmt_gpio_data",23,16],0,8,"RW",0,0,107]],
|
||||
"0x0f": [["GPIO data low(reg_mprj_datal)",["mgmt_gpio_data",31,24],0,8,"RW",0,0,106]],
|
||||
"0x10": [["GPIO data high(reg_mprj_datah)",["mgmt_gpio_data",37,32],0,5,"RW",0,0,105]],
|
||||
"0x24": [["mprj_io[00](reg_mprj_io_0)",["gpio_configure[0]",7,0],0,8,"RW",3,3,30]],
|
||||
"0x25": [["mprj_io[00](reg_mprj_io_0)",["gpio_configure[0]",12,8],0,5,"RW",24,24,29]],
|
||||
"0x28": [["mprj_io[01](reg_mprj_io_1)",["gpio_configure[1]",7,0],0,8,"RW",3,3,32]],
|
||||
"0x29": [["mprj_io[01](reg_mprj_io_1)",["gpio_configure[1]",12,8],0,5,"RW",24,24,31]],
|
||||
"0x2c": [["mprj_io[02](reg_mprj_io_2)",["gpio_configure[2]",7,0],0,8,"RW",3,3,34]],
|
||||
"0x2d": [["mprj_io[02](reg_mprj_io_2)",["gpio_configure[2]",12,8],0,5,"RW",4,4,33]],
|
||||
"0x30": [["mprj_io[03](reg_mprj_io_3)",["gpio_configure[3]",7,0],0,8,"RW",3,3,36]],
|
||||
"0x31": [["mprj_io[03](reg_mprj_io_3)",["gpio_configure[3]",12,8],0,5,"RW",4,4,35]],
|
||||
"0x34": [["mprj_io[04](reg_mprj_io_4)",["gpio_configure[4]",7,0],0,8,"RW",3,3,38]],
|
||||
"0x35": [["mprj_io[04](reg_mprj_io_4)",["gpio_configure[4]",12,8],0,5,"RW",4,4,37]],
|
||||
"0x38": [["mprj_io[05](reg_mprj_io_5)",["gpio_configure[5]",7,0],0,8,"RW",3,3,40]],
|
||||
"0x39": [["mprj_io[05](reg_mprj_io_5)",["gpio_configure[5]",12,8],0,5,"RW",4,4,39]],
|
||||
"0x3c": [["mprj_io[06](reg_mprj_io_6)",["gpio_configure[6]",7,0],0,8,"RW",3,3,42]],
|
||||
"0x3d": [["mprj_io[06](reg_mprj_io_6)",["gpio_configure[6]",12,8],0,5,"RW",4,4,41]],
|
||||
"0x40": [["mprj_io[07](reg_mprj_io_7)",["gpio_configure[7]",7,0],0,8,"RW",3,3,44]],
|
||||
"0x41": [["mprj_io[07](reg_mprj_io_7)",["gpio_configure[7]",12,8],0,5,"RW",4,4,43]],
|
||||
"0x44": [["mprj_io[08](reg_mprj_io_8)",["gpio_configure[8]",7,0],0,8,"RW",3,3,46]],
|
||||
"0x45": [["mprj_io[08](reg_mprj_io_8)",["gpio_configure[8]",12,8],0,5,"RW",4,4,45]],
|
||||
"0x48": [["mprj_io[09](reg_mprj_io_9)",["gpio_configure[9]",7,0],0,8,"RW",3,3,48]],
|
||||
"0x49": [["mprj_io[09](reg_mprj_io_9)",["gpio_configure[9]",12,8],0,5,"RW",4,4,47]],
|
||||
"0x4c": [["mprj_io[10](reg_mprj_io_10)",["gpio_configure[10]",7,0],0,8,"RW",3,3,50]],
|
||||
"0x4d": [["mprj_io[10](reg_mprj_io_10)",["gpio_configure[10]",12,8],0,5,"RW",4,4,49]],
|
||||
"0x50": [["mprj_io[11](reg_mprj_io_11)",["gpio_configure[11]",7,0],0,8,"RW",3,3,52]],
|
||||
"0x51": [["mprj_io[11](reg_mprj_io_11)",["gpio_configure[11]",12,8],0,5,"RW",4,4,51]],
|
||||
"0x54": [["mprj_io[12](reg_mprj_io_12)",["gpio_configure[12]",7,0],0,8,"RW",3,3,54]],
|
||||
"0x55": [["mprj_io[12](reg_mprj_io_12)",["gpio_configure[12]",12,8],0,5,"RW",4,4,53]],
|
||||
"0x58": [["mprj_io[13](reg_mprj_io_13)",["gpio_configure[13]",7,0],0,8,"RW",3,3,56]],
|
||||
"0x59": [["mprj_io[13](reg_mprj_io_13)",["gpio_configure[13]",12,8],0,5,"RW",4,4,55]],
|
||||
"0x5c": [["mprj_io[14](reg_mprj_io_14)",["gpio_configure[14]",7,0],0,8,"RW",3,3,58]],
|
||||
"0x5d": [["mprj_io[14](reg_mprj_io_14)",["gpio_configure[14]",12,8],0,5,"RW",4,4,57]],
|
||||
"0x60": [["mprj_io[15](reg_mprj_io_15)",["gpio_configure[15]",7,0],0,8,"RW",3,3,60]],
|
||||
"0x61": [["mprj_io[15](reg_mprj_io_15)",["gpio_configure[15]",12,8],0,5,"RW",4,4,59]],
|
||||
"0x64": [["mprj_io[16](reg_mprj_io_16)",["gpio_configure[16]",7,0],0,8,"RW",3,3,62]],
|
||||
"0x65": [["mprj_io[16](reg_mprj_io_16)",["gpio_configure[16]",12,8],0,5,"RW",4,4,61]],
|
||||
"0x68": [["mprj_io[17](reg_mprj_io_17)",["gpio_configure[17]",7,0],0,8,"RW",3,3,64]],
|
||||
"0x69": [["mprj_io[17](reg_mprj_io_17)",["gpio_configure[17]",12,8],0,5,"RW",4,4,63]],
|
||||
"0x6c": [["mprj_io[18](reg_mprj_io_18)",["gpio_configure[18]",7,0],0,8,"RW",3,3,66]],
|
||||
"0x6d": [["mprj_io[18](reg_mprj_io_18)",["gpio_configure[18]",12,8],0,5,"RW",4,4,65]],
|
||||
"0x70": [["mprj_io[19](reg_mprj_io_19)",["gpio_configure[19]",7,0],0,8,"RW",3,3,68]],
|
||||
"0x71": [["mprj_io[19](reg_mprj_io_19)",["gpio_configure[19]",12,8],0,5,"RW",4,4,67]],
|
||||
"0x74": [["mprj_io[20](reg_mprj_io_20)",["gpio_configure[20]",7,0],0,8,"RW",3,3,70]],
|
||||
"0x75": [["mprj_io[20](reg_mprj_io_20)",["gpio_configure[20]",12,8],0,5,"RW",4,4,69]],
|
||||
"0x78": [["mprj_io[21](reg_mprj_io_21)",["gpio_configure[21]",7,0],0,8,"RW",3,3,72]],
|
||||
"0x79": [["mprj_io[21](reg_mprj_io_21)",["gpio_configure[21]",12,8],0,5,"RW",4,4,71]],
|
||||
"0x7c": [["mprj_io[22](reg_mprj_io_22)",["gpio_configure[22]",7,0],0,8,"RW",3,3,74]],
|
||||
"0x7d": [["mprj_io[22](reg_mprj_io_22)",["gpio_configure[22]",12,8],0,5,"RW",4,4,73]],
|
||||
"0x80": [["mprj_io[23](reg_mprj_io_23)",["gpio_configure[23]",7,0],0,8,"RW",3,3,76]],
|
||||
"0x81": [["mprj_io[23](reg_mprj_io_23)",["gpio_configure[23]",12,8],0,5,"RW",4,4,75]],
|
||||
"0x84": [["mprj_io[24](reg_mprj_io_24)",["gpio_configure[24]",7,0],0,8,"RW",3,3,78]],
|
||||
"0x85": [["mprj_io[24](reg_mprj_io_24)",["gpio_configure[24]",12,8],0,5,"RW",4,4,77]],
|
||||
"0x88": [["mprj_io[25](reg_mprj_io_25)",["gpio_configure[25]",7,0],0,8,"RW",3,3,80]],
|
||||
"0x89": [["mprj_io[25](reg_mprj_io_25)",["gpio_configure[25]",12,8],0,5,"RW",4,4,79]],
|
||||
"0x8c": [["mprj_io[26](reg_mprj_io_26)",["gpio_configure[26]",7,0],0,8,"RW",3,3,82]],
|
||||
"0x8d": [["mprj_io[26](reg_mprj_io_26)",["gpio_configure[26]",12,8],0,5,"RW",4,4,81]],
|
||||
"0x90": [["mprj_io[27](reg_mprj_io_27)",["gpio_configure[27]",7,0],0,8,"RW",3,3,84]],
|
||||
"0x91": [["mprj_io[27](reg_mprj_io_27)",["gpio_configure[27]",12,8],0,5,"RW",4,4,83]],
|
||||
"0x94": [["mprj_io[28](reg_mprj_io_28)",["gpio_configure[28]",7,0],0,8,"RW",3,3,86]],
|
||||
"0x95": [["mprj_io[28](reg_mprj_io_28)",["gpio_configure[28]",12,8],0,5,"RW",4,4,85]],
|
||||
"0x98": [["mprj_io[29](reg_mprj_io_29)",["gpio_configure[29]",7,0],0,8,"RW",3,3,88]],
|
||||
"0x99": [["mprj_io[29](reg_mprj_io_29)",["gpio_configure[29]",12,8],0,5,"RW",4,4,87]],
|
||||
"0x9c": [["mprj_io[30](reg_mprj_io_30)",["gpio_configure[30]",7,0],0,8,"RW",3,3,90]],
|
||||
"0x9d": [["mprj_io[30](reg_mprj_io_30)",["gpio_configure[30]",12,8],0,5,"RW",4,4,89]],
|
||||
"0xa0": [["mprj_io[31](reg_mprj_io_31)",["gpio_configure[31]",7,0],0,8,"RW",3,3,92]],
|
||||
"0xa1": [["mprj_io[31](reg_mprj_io_31)",["gpio_configure[31]",12,8],0,5,"RW",4,4,91]],
|
||||
"0xa4": [["mprj_io[32](reg_mprj_io_32)",["gpio_configure[32]",7,0],0,8,"RW",3,3,94]],
|
||||
"0xa5": [["mprj_io[32](reg_mprj_io_32)",["gpio_configure[32]",12,8],0,5,"RW",4,4,93]],
|
||||
"0xa8": [["mprj_io[33](reg_mprj_io_33)",["gpio_configure[33]",7,0],0,8,"RW",3,3,96]],
|
||||
"0xa9": [["mprj_io[33](reg_mprj_io_33)",["gpio_configure[33]",12,8],0,5,"RW",4,4,95]],
|
||||
"0xac": [["mprj_io[34](reg_mprj_io_34)",["gpio_configure[34]",7,0],0,8,"RW",3,3,98]],
|
||||
"0xad": [["mprj_io[34](reg_mprj_io_34)",["gpio_configure[34]",12,8],0,5,"RW",4,4,97]],
|
||||
"0xb0": [["mprj_io[35](reg_mprj_io_35)",["gpio_configure[35]",7,0],0,8,"RW",3,3,100]],
|
||||
"0xb1": [["mprj_io[35](reg_mprj_io_35)",["gpio_configure[35]",12,8],0,5,"RW",4,4,99]],
|
||||
"0xb4": [["mprj_io[36](reg_mprj_io_36)",["gpio_configure[36]",7,0],0,8,"RW",3,3,102]],
|
||||
"0xb5": [["mprj_io[36](reg_mprj_io_36)",["gpio_configure[36]",12,8],0,5,"RW",24,24,101]],
|
||||
"0xb8": [["mprj_io[37](reg_mprj_io_37)",["gpio_configure[37]",7,0],0,8,"RW",3,3,104]],
|
||||
"0xb9": [["mprj_io[37](reg_mprj_io_37)",["gpio_configure[37]",12,8],0,5,"RW",24,24,103]]
|
||||
},
|
||||
|
||||
"sys":{ "base_addr": ["SYS_BASE_ADR",639631360],
|
||||
"0x00": [["user2 vdd good","usr2_vdd_pwrgood",0,1,"RO",0,0,26],["user1 vdd good","usr1_vdd_pwrgood",1,1,"RO",0,0,26],
|
||||
["user2 vcc good","usr2_vcc_pwrgood",2,1,"RO",0,0,26],["user1 vcc good","usr1_vcc_pwrgood",3,1,"RO",0,0,26]],
|
||||
"0x04": [["Trap output redirect","trap_output_dest",0,1,"RW",0,0,27],
|
||||
["clock2 output redirect","clk2_output_dest",1,1,"RW",0,0,27],
|
||||
["clock1 output redirect","clk1_output_dest",2,1,"RW",0,0,27]],
|
||||
"0x0c": [["IRQ1 input redirect","irq_1_inputsrc",0,1,"RW",0,0,28],["IRQ2 redirect","irq_2_inputsrc",1,1,"RW",0,0,28]],
|
||||
"0x10": [["Housekeeping SPI disable","hkspi_disable",0,1,"RW",0,0,111]]
|
||||
}
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,92 @@
|
|||
from cocotb_bus.scoreboard import Scoreboard
|
||||
from cocotb.utils import hexdump, hexdiffs
|
||||
from cocotb.log import SimLog
|
||||
from cocotb.result import TestFailure, TestSuccess
|
||||
from cocotb_bus.monitors import Monitor
|
||||
import cocotb
|
||||
|
||||
|
||||
class HKScoreboard(Scoreboard):
|
||||
def __init__(self, dut, reorder_depth=0, fail_immediately=True):
|
||||
|
||||
Scoreboard.__init__(self, dut, reorder_depth, fail_immediately)
|
||||
|
||||
def compare(self, got, exp, log, strict_type=True):
|
||||
# Compare the types
|
||||
if strict_type and type(got) != type(exp):
|
||||
self.errors += 1
|
||||
log.error("Received transaction type is different than expected")
|
||||
log.info("Received: %s but expected %s" %
|
||||
(str(type(got)), str(type(exp))))
|
||||
if self._imm:
|
||||
raise TestFailure("Received transaction of wrong type. "
|
||||
"Set strict_type=False to avoid this.")
|
||||
return
|
||||
# Or convert to a string before comparison
|
||||
elif not strict_type:
|
||||
got, exp = str(got), str(exp)
|
||||
|
||||
# Compare directly
|
||||
if self.dict_compare(got, exp):
|
||||
self.errors += 1
|
||||
|
||||
# Try our best to print out something useful
|
||||
strgot, strexp = str(got), str(exp)
|
||||
|
||||
log.error("Received transaction differed from expected output")
|
||||
if not strict_type:
|
||||
log.info("Expected:\n" + hexdump(strexp))
|
||||
else:
|
||||
log.info("Expected:\n" + repr(exp))
|
||||
if not isinstance(exp, str):
|
||||
try:
|
||||
for word in exp:
|
||||
log.info(str(word))
|
||||
except Exception:
|
||||
pass
|
||||
if not strict_type:
|
||||
log.info("Received:\n" + hexdump(strgot))
|
||||
else:
|
||||
log.info("Received:\n" + repr(got))
|
||||
if not isinstance(got, str):
|
||||
try:
|
||||
for word in got:
|
||||
log.info(str(word))
|
||||
except Exception:
|
||||
pass
|
||||
log.warning("Difference:\n%s" % hexdiffs(strexp, strgot))
|
||||
if self._imm:
|
||||
raise TestFailure("Received transaction differed from expected "
|
||||
"transaction")
|
||||
else:
|
||||
# Don't want to fail the test
|
||||
# if we're passed something without __len__
|
||||
try:
|
||||
log.debug("Received expected transaction %d bytes" %
|
||||
(len(got)))
|
||||
log.debug(repr(got))
|
||||
except Exception:
|
||||
pass
|
||||
|
||||
def dict_compare(self,d1, d2):
|
||||
d1_keys = set(d1.keys())
|
||||
d2_keys = set(d2.keys())
|
||||
shared_keys = d1_keys.intersection(d2_keys)
|
||||
different_keys = d1_keys.symmetric_difference(d2_keys)
|
||||
if different_keys is not None:
|
||||
cocotb.log.info(f"[HKScoreboard][dict_compare] return False because different_keys \n {d1} \n {d2}")
|
||||
self.print_expected()
|
||||
return False
|
||||
modified = {o : (d1[o], d2[o]) for o in shared_keys if d1[o] != d2[o]}
|
||||
if modified is not None:
|
||||
cocotb.log.info(f"[HKScoreboard][dict_compare] return False because modified \n {d1} \n {d2}")
|
||||
self.print_expected()
|
||||
return False
|
||||
cocotb.log.info(f"[HKScoreboard][dict_compare] return True \n {d1} \n {d2}")
|
||||
self.print_expected()
|
||||
return True
|
||||
|
||||
|
||||
def print_expected(self):
|
||||
for val in self.expected.items():
|
||||
cocotb.log.info(val)
|
||||
|
|
@ -0,0 +1,167 @@
|
|||
|
||||
import cocotb
|
||||
from cocotb.triggers import Timer, RisingEdge, ReadOnly
|
||||
from cocotb_bus.monitors import Monitor
|
||||
from cocotb.log import SimLogFormatter, SimTimeContextFilter
|
||||
from cocotb.binary import BinaryValue
|
||||
from cocotb.result import TestFailure
|
||||
from math import ceil
|
||||
import copy
|
||||
import logging
|
||||
from fnmatch import fnmatch
|
||||
|
||||
|
||||
class HKmonitor(Monitor):
|
||||
"""Observes single input """
|
||||
def __init__(self, name, block_path,interfaces, clock,reset,is_logger = False, callback=None, event=None):
|
||||
self.name = name
|
||||
self.interfaces = interfaces
|
||||
self.clock = clock
|
||||
self.reset = reset
|
||||
self.block_path = block_path
|
||||
self.is_logger = is_logger
|
||||
self.setup_logger()
|
||||
Monitor.__init__(self, callback, event)
|
||||
|
||||
|
||||
async def _monitor_recv(self):
|
||||
old_trans_hold = None
|
||||
old_trans_no_valid = None
|
||||
while True:
|
||||
# Capture signal at rising edge of clock
|
||||
if "_clk" in self.interfaces: # for interfaces with own clock
|
||||
signal = self.block_path._id(self.interfaces['_clk']['signal'],False)
|
||||
await RisingEdge(signal)
|
||||
else:
|
||||
await RisingEdge(self.clock)
|
||||
|
||||
|
||||
# if self.reset.value.binstr == '0':
|
||||
# continue
|
||||
|
||||
if "_valid_cycle" in self.interfaces: # for interfaces with valid signal
|
||||
signal = self.block_path._id(self.interfaces['_valid_cycle']['signal'],False).value.binstr
|
||||
if signal is not '1':
|
||||
continue
|
||||
|
||||
if "_valid_cycle_n" in self.interfaces: # for interfaces with valid signal
|
||||
signal = self.block_path._id(self.interfaces['_valid_cycle']['signal'],False).value.binstr
|
||||
if signal is not '0':
|
||||
continue
|
||||
|
||||
# update signal
|
||||
for key2,signal in self.interfaces.items():
|
||||
# if fnmatch(key2,"_*"):
|
||||
# continue
|
||||
signal['val'] = self.block_path._id(signal['signal'],False).value
|
||||
|
||||
# if no_valid signal exist trans didn't change so monitor will not monitor anything
|
||||
# no_valid means if the signal didn't change no addition action would needed
|
||||
if "_no_valid" in self.interfaces:
|
||||
if old_trans_no_valid is None:
|
||||
old_trans_no_valid = copy.deepcopy(self.interfaces)
|
||||
elif (old_trans_no_valid == self.interfaces):
|
||||
return
|
||||
else:
|
||||
old_trans_no_valid = copy.deepcopy(self.interfaces)
|
||||
|
||||
# logger
|
||||
self.logger.debug(f' ')
|
||||
self.handler.terminator = ""
|
||||
self.handler.setFormatter(SimLogFormatter())
|
||||
self.logger.debug(f'')
|
||||
self.handler.setFormatter(logging.Formatter('%(message)s'))
|
||||
for key2,signal in self.interfaces.items():
|
||||
if fnmatch(key2,"_*"):
|
||||
continue
|
||||
if signal['val'].is_resolvable:
|
||||
length = self.lengths[key2] - (len(hex(signal['val'].integer)))
|
||||
self.logger.debug(f" {hex(signal['val'].integer)}{' '*length}|")
|
||||
# signal['val'] = self.block_path._id(signal['signal'],False).value.integer
|
||||
else:
|
||||
length = self.lengths[key2] - (len('x'))
|
||||
self.logger.debug(f" x{' '*length}|")
|
||||
self.handler.terminator = "\n"
|
||||
|
||||
# special case in HKoutputsMonitorwishbone when writing to reg_mprj_datal(because it uses _buf) the data out is x's
|
||||
# and in this case scoreboard raise obejection that the value is unresolved
|
||||
if self.name == "HKoutputsMonitorwishbone":
|
||||
if not self.interfaces['data']['val'].is_resolvable:
|
||||
self.interfaces['data']['val'] = BinaryValue(value=0,n_bits=self.interfaces['data']['val'].n_bits)
|
||||
cocotb.log.debug(f'[HKmonitor][_monitor_recv] interface at monitor {self.name} self.interfaces {self.interfaces}')
|
||||
self._recv(self.interfaces)
|
||||
|
||||
## assertion that the values can't change until hold is released
|
||||
if "_hold" in self.interfaces:
|
||||
if old_trans_hold is None:
|
||||
skip = False
|
||||
old_trans_hold = copy.deepcopy(self.interfaces)
|
||||
elif self.interfaces['_hold']['val'] == BinaryValue(value=1):
|
||||
skip = True
|
||||
elif skip:
|
||||
old_trans_hold = copy.deepcopy(self.interfaces)
|
||||
skip = False
|
||||
else:
|
||||
if old_trans_hold != self.interfaces:
|
||||
cocotb.log.error(f'[HKmonitor][_monitor_recv] interface at monitor {self.name} change value before hold value is asserted \nold value {old_trans_hold} \nnew value {self.interfaces}')
|
||||
raise TestFailure
|
||||
|
||||
|
||||
"""method for setting up logger for WB model"""
|
||||
def setup_logger(self):
|
||||
self.logger = logging.getLogger(f'HouseKeeping{self.name}')
|
||||
self.logger.setLevel(logging.DEBUG)
|
||||
if not self.is_logger:
|
||||
self.logger.setLevel(logging.INFO)
|
||||
self.handler = logging.StreamHandler()
|
||||
# return
|
||||
else :
|
||||
self.handler = logging.FileHandler(f"{self.name}.log",mode='w')
|
||||
self.handler.addFilter(SimTimeContextFilter())
|
||||
self.logger.addHandler(self.handler)
|
||||
# get the sizes of signals
|
||||
#for key,interface in self.interfaces.items():
|
||||
for key,signal in self.interfaces.items():
|
||||
if fnmatch(key,"_*"):
|
||||
continue
|
||||
signal['val'] = self.block_path._id(signal['signal'],False).value
|
||||
size = signal['val'].n_bits
|
||||
signal['val'] = BinaryValue(value = int(size) * '1',n_bits=size)
|
||||
# set the logger file header
|
||||
# set first line
|
||||
self.handler.terminator = ""
|
||||
self.logger.debug(f' timestamp level ')
|
||||
length =0
|
||||
for key2,signal in self.interfaces.items():
|
||||
if fnmatch(key2,"_*"):
|
||||
continue
|
||||
length += max(ceil(signal['val'].n_bits/4)+2 , len(key2)) +3
|
||||
length -= len(key)+1
|
||||
self.logger.debug(f'| signals {" "*int(length)}')
|
||||
self.handler.terminator = "\n"
|
||||
self.logger.debug(f' ')
|
||||
# set second line
|
||||
self.handler.terminator = ""
|
||||
self.logger.debug(f'{" "*20}|')
|
||||
length =0
|
||||
self.lengths = dict()
|
||||
for key2,signal in self.interfaces.items():
|
||||
if fnmatch(key2,"_*"):
|
||||
continue
|
||||
self.lengths[key2] = max((len(hex(signal['val'].integer))),len(key2)) +1
|
||||
length = self.lengths[key2] - len(key2)
|
||||
self.logger.debug(f'{key2}{" "*length} ')
|
||||
self.handler.terminator = "\n"
|
||||
|
||||
|
||||
class color:
|
||||
PURPLE = '\033[95m'
|
||||
CYAN = '\033[96m'
|
||||
DARKCYAN = '\033[36m'
|
||||
BLUE = '\033[94m'
|
||||
GREEN = '\033[92m'
|
||||
YELLOW = '\033[93m'
|
||||
RED = '\033[91m'
|
||||
BOLD = '\033[1m'
|
||||
UNDERLINE = '\033[4m'
|
||||
END = '\033[0m'
|
||||
|
|
@ -0,0 +1,133 @@
|
|||
{
|
||||
"inputs" : { "wishbone": {"adr": {"signal":"wb_adr_i","val":0},
|
||||
"data": {"signal":"wb_dat_i","val":0},
|
||||
"sel": {"signal":"wb_sel_i","val":0},
|
||||
"write_en": {"signal":"wb_we_i","val":0},
|
||||
"cycle_valid": {"signal":"wb_cyc_i","val":0},
|
||||
"stb": {"signal":"wb_stb_i","val":0},
|
||||
"_clk": {"signal":"wb_clk_i","val":0},
|
||||
"_rst": {"signal":"wb_rstn_i","val":0},
|
||||
"_hold": {"signal":"wb_ack_o","val":0},
|
||||
"_valid_cycle":{"signal":"wb_cyc_i","val":0}},
|
||||
|
||||
"user_clk": {"user_clk": {"signal":"user_clock","val":0}},
|
||||
"trap": {"user_clk": {"signal":"trap","val":0}},
|
||||
|
||||
"UART": {"TX": {"signal":"ser_tx","val":0},
|
||||
"gpio_in": {"signal":"mgmt_gpio_in","val":0},
|
||||
"enable": {"signal":"uart_enabled","val":0}},
|
||||
|
||||
"SPI": {"CSB": {"signal":"bin3","val":0},
|
||||
"SCK": {"signal":"bin4","val":0},
|
||||
"SDI": {"signal":"bin2","val":0},
|
||||
"_clk": {"signal":"bin4","val":0},
|
||||
"_valid_cycle_n":{"signal":"bin3","val":0}
|
||||
},
|
||||
|
||||
"SPI_master": {"CSB": {"signal":"spi_csb","val":0},
|
||||
"SCK": {"signal":"spi_sck","val":0},
|
||||
"SDO": {"signal":"spi_sdo","val":0},
|
||||
"SDO_en": {"signal":"spi_sdoenb","val":0},
|
||||
"spi_enabled": {"signal":"spi_enabled","val":0},
|
||||
"_clk": {"signal":"spi_sck","val":0},
|
||||
"_valid_cycle_n":{"signal":"spi_csb","val":0}
|
||||
},
|
||||
|
||||
"gpio_data": {"data": {"signal":"mgmt_gpio_in","val":0}},
|
||||
|
||||
"QSPI_mgmt": {"clk": {"signal":"spimemio_flash_clk","val":0},
|
||||
"CSB": {"signal":"spimemio_flash_csb","val":0},
|
||||
"io0_oen": {"signal":"spimemio_flash_io0_oeb","val":0},
|
||||
"io1_oen": {"signal":"spimemio_flash_io1_oeb","val":0},
|
||||
"io2_oen": {"signal":"spimemio_flash_io2_oeb","val":0},
|
||||
"io3_oen": {"signal":"spimemio_flash_io3_oeb","val":0},
|
||||
"data0": {"signal":"spimemio_flash_io0_do","val":0},
|
||||
"data1": {"signal":"spimemio_flash_io1_do","val":0},
|
||||
"data2": {"signal":"spimemio_flash_io2_do","val":0},
|
||||
"data3": {"signal":"spimemio_flash_io3_do","val":0},
|
||||
"qspi_en": {"signal":"qspi_enabled","val":0},
|
||||
"_clk": {"signal":"spimemio_flash_clk","val":0}},
|
||||
|
||||
"debug": {"data": {"signal":"debug_out","val":0},
|
||||
"out_en": {"signal":"debug_oeb","val":0},
|
||||
"gpio_in": {"signal":"mgmt_gpio_in","val":0},
|
||||
"enable": {"signal":"debug_mode","val":0}},
|
||||
|
||||
"QSPI_pad": {"data0": {"signal":"pad_flash_io0_di","val":0},
|
||||
"data1": {"signal":"pad_flash_io1_di","val":0}},
|
||||
|
||||
"sram": {"data": {"signal":"pad_flash_io0_di","val":0}},
|
||||
|
||||
"system": {"vcc1_good": {"signal":"usr1_vcc_pwrgood","val":0},
|
||||
"vcc2_good": {"signal":"usr2_vcc_pwrgood","val":0},
|
||||
"vdd1_good": {"signal":"usr1_vdd_pwrgood","val":0},
|
||||
"vdd2_good": {"signal":"usr2_vdd_pwrgood","val":0},
|
||||
"_no_valid": {"signal":"usr2_vdd_pwrgood","val":0}},
|
||||
|
||||
"project_id": {"mask": {"signal":"mask_rev_in","val":0}}
|
||||
|
||||
},
|
||||
|
||||
"outputs" : { "wishbone": {"ack": {"signal":"wb_ack_o","val":0},
|
||||
"data": {"signal":"wb_dat_o","val":0},
|
||||
"_valid_cycle":{"signal":"wb_ack_o","val":0}},
|
||||
|
||||
"UART": {"RX": {"signal":"ser_rx","val":0}},
|
||||
|
||||
"SPI": {"CSB": {"signal":"bin3","val":0},
|
||||
"SCK": {"signal":"bin4","val":0},
|
||||
"SDO": {"signal":"bin1","val":0},
|
||||
"_clk": {"signal":"bin4","val":0},
|
||||
"_valid_cycle_n":{"signal":"bin3","val":0}
|
||||
},
|
||||
|
||||
"SPI_master": {"SDI": {"signal":"spi_sdi","val":0},
|
||||
"_clk": {"signal":"spi_sck","val":0}},
|
||||
|
||||
"clk_ctrl": {"pll_en": {"signal":"pll_ena","val":0},
|
||||
"pll_dco_en": {"signal":"pll_dco_ena","val":0},
|
||||
"pll_div": {"signal":"pll_div","val":0},
|
||||
"pll_sel": {"signal":"pll_sel","val":0},
|
||||
"pll90_sel": {"signal":"pll90_sel","val":0},
|
||||
"pll_trim": {"signal":"pll_trim","val":0},
|
||||
"pll_bypass": {"signal":"pll_bypass","val":0}},
|
||||
|
||||
"external": {"irq": {"signal":"irq","val":0},
|
||||
"rst": {"signal":"reset","val":0}},
|
||||
|
||||
"gpio_loader":{"clk": {"signal":"serial_clock","val":0},
|
||||
"load": {"signal":"serial_load","val":0},
|
||||
"rst": {"signal":"serial_resetn","val":0},
|
||||
"data_1": {"signal":"serial_data_1","val":0},
|
||||
"data_2": {"signal":"serial_data_2","val":0}},
|
||||
|
||||
"gpio_data": {"data": {"signal":"mgmt_gpio_out","val":0},
|
||||
"enable": {"signal":"mgmt_gpio_oeb","val":0}},
|
||||
|
||||
"pwr_ctrl": {"data": {"signal":"pwr_ctrl_out","val":0}},
|
||||
|
||||
"QSPI_mgmt": {"data0": {"signal":"spimemio_flash_io0_di","val":0},
|
||||
"data1": {"signal":"spimemio_flash_io1_di","val":0},
|
||||
"data2": {"signal":"spimemio_flash_io2_di","val":0},
|
||||
"data3": {"signal":"spimemio_flash_io3_di","val":0}},
|
||||
|
||||
"debug": {"data": {"signal":"debug_in","val":0}},
|
||||
|
||||
"QSPI_pad": {"clk": {"signal":"pad_flash_clk","val":0},
|
||||
"clk_en": {"signal":"pad_flash_clk_oeb","val":0},
|
||||
"CSB": {"signal":"pad_flash_csb","val":0},
|
||||
"CSB_en": {"signal":"pad_flash_csb_oeb","val":0},
|
||||
"data0": {"signal":"pad_flash_io0_do","val":0},
|
||||
"data0_oen": {"signal":"pad_flash_io0_oeb","val":0},
|
||||
"data0_ien": {"signal":"pad_flash_io0_ieb","val":0},
|
||||
"data1": {"signal":"pad_flash_io1_do","val":0},
|
||||
"data1_oen": {"signal":"pad_flash_io1_oeb","val":0},
|
||||
"data1_ien": {"signal":"pad_flash_io1_ieb","val":0},
|
||||
"_clk": {"signal":"spimemio_flash_clk","val":0}},
|
||||
|
||||
"sram": {"clk": {"signal":"sram_ro_clk","val":0},
|
||||
"CSB": {"signal":"sram_ro_csb","val":0},
|
||||
"adr": {"signal":"sram_ro_addr","val":0}}
|
||||
}
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,114 @@
|
|||
import json
|
||||
import cocotb
|
||||
from cocotb.triggers import Timer, RisingEdge, ReadOnly
|
||||
from cocotb_bus.monitors import Monitor
|
||||
from cocotb.log import SimLogFormatter, SimTimeContextFilter
|
||||
from cocotb.binary import BinaryValue
|
||||
from math import ceil
|
||||
from wb_models.housekeepingWB.HKmonitor import HKmonitor
|
||||
from wb_models.housekeepingWB.HKSPImonitor import HKSPImonitor
|
||||
from wb_models.housekeepingWB.HKSPImonitor import CSBmonitor
|
||||
from wb_models.housekeepingWB.HK_models import HK_models
|
||||
from cocotb_bus.scoreboard import Scoreboard
|
||||
import logging
|
||||
import fnmatch
|
||||
import copy
|
||||
from cocotb.result import TestFailure
|
||||
from common import Macros
|
||||
|
||||
|
||||
class HK_whiteBox:
|
||||
def __init__(self,dut,loggers=False):
|
||||
self.dut = dut
|
||||
self.hk_hdl = dut.uut.housekeeping
|
||||
# self.hkspi_hdl = dut.uut.housekeeping.hkspi
|
||||
self.clk = self.dut.uut.mprj_clock
|
||||
self.reset = self.dut.uut.resetb
|
||||
self.logger = loggers
|
||||
self.load_js()
|
||||
self.setupModels()
|
||||
self.Monitors()
|
||||
cocotb.scheduler.add(self.reg_model_sb())
|
||||
"""load json models"""
|
||||
def load_js(self):
|
||||
with open('wb_models/housekeepingWB/housekeepingIF.json') as f:
|
||||
self.interface = json.load(f)
|
||||
with open('wb_models/housekeepingWB/HK_regs.json') as f:
|
||||
self.reg_model = json.load(f)
|
||||
self.output_if = copy.deepcopy(self.interface['outputs'])
|
||||
|
||||
""""method to add the housekeeping monitors"""
|
||||
def Monitors(self):
|
||||
inputs = self.interface['inputs']
|
||||
outputs = self.interface['outputs']
|
||||
# wishbone
|
||||
wishbone_mon_i = HKmonitor(f"HKinputsMonitorwishbone",self.hk_hdl,inputs['wishbone'],self.clk,self.reset,self.logger,callback=self.wb_models.wishbone_model)
|
||||
wishbone_mon_o = HKmonitor(f"HKoutputsMonitorwishbone",self.hk_hdl,outputs['wishbone'],self.clk,self.reset,self.logger)
|
||||
wishbone_sb = Scoreboard(SB_name("wishbone_sb"),fail_immediately=False)
|
||||
wishbone_sb.add_interface(wishbone_mon_o, self.wb_models.exp_out_wb)
|
||||
# system
|
||||
system_mon_i = HKmonitor(f"HKinputsMonitorsystem",self.hk_hdl,inputs['system'],self.clk,self.reset,self.logger,callback=self.wb_models.system_model)
|
||||
# UART
|
||||
UART_mon_i = HKmonitor(f"HKinputsMonitorUART",self.hk_hdl,inputs['UART'],self.clk,self.reset,self.logger,callback=self.wb_models.UART_model)
|
||||
UART_mon_o = HKmonitor(f"HKoutputsMonitorUART",self.hk_hdl,outputs['UART'],self.clk,self.reset,self.logger)
|
||||
UART_sb = Scoreboard(SB_name("UART_sb"),fail_immediately=False)
|
||||
UART_sb.add_interface(UART_mon_o, self.wb_models.exp_out_uart_rx)
|
||||
|
||||
# debug
|
||||
debug_mon_i = HKmonitor(f"HKinputsMonitordebug",self.hk_hdl,inputs['debug'],self.clk,self.reset,self.logger,callback=self.wb_models.debug_model)
|
||||
debug_mon_o = HKmonitor(f"HKoutputsMonitordebug",self.hk_hdl,outputs['debug'],self.clk,self.reset,self.logger)
|
||||
debug_sb = Scoreboard(SB_name("debug_sb"),fail_immediately=False)
|
||||
debug_sb.add_interface(debug_mon_o, self.wb_models.exp_out_debug)
|
||||
|
||||
# SPI
|
||||
SPI_mon_i = HKSPImonitor(f"HKinputsMonitorSPI",self.hk_hdl,inputs['SPI'],self.clk,self.reset,self.logger,callback=self.wb_models.spi_model)
|
||||
SPI_mon_o = HKSPImonitor(f"HKoutputsMonitorSPI",self.hk_hdl,outputs['SPI'],self.clk,self.reset,self.logger,input=False)
|
||||
CSBmonitor(f"HKCSBmonitor",self.hk_hdl,outputs['SPI'],self.clk,self.reset,False,callback=self.wb_models.reset_spi_vals)
|
||||
SPI_sb = Scoreboard(SB_name("SPI_sb"),fail_immediately=False)
|
||||
SPI_sb.add_interface(SPI_mon_o, self.wb_models.exp_out_spi)
|
||||
|
||||
"""initialize all models needed"""
|
||||
def setupModels(self):
|
||||
with open('wb_models/housekeepingWB/HK_regs.json') as f:
|
||||
self.reg_model = json.load(f)
|
||||
self.wb_models = HK_models(self.reg_model,self.output_if,self.hk_hdl)
|
||||
|
||||
"""scoreboard for register model check the reg model with RTL every clock"""
|
||||
async def reg_model_sb(self):
|
||||
while True:
|
||||
await RisingEdge(self.clk)
|
||||
for key,memory_block in self.reg_model.items():
|
||||
if fnmatch.fnmatch(key, "_*"):
|
||||
continue
|
||||
for reg_shift,reg in memory_block.items():
|
||||
for field in reg:
|
||||
if reg_shift == "base_addr":
|
||||
continue
|
||||
RTL_reg_name = field[1]
|
||||
if RTL_reg_name == None:
|
||||
cocotb.log.debug(f"[HK_whiteBox][reg_model_sb] register {field[1]} in {key} doesn't have a RTL register")
|
||||
continue
|
||||
if isinstance(field[1],list):
|
||||
RTL_name = field[1][0]
|
||||
first_index = int(field[1][1])
|
||||
second_index= int(field[1][2])
|
||||
if Macros['GL']:
|
||||
if RTL_name in ["mfgr_id","prod_id","mask_rev","mgmt_gpio_data"]: continue #TODO: change with SDF only
|
||||
if Macros['GL']:
|
||||
if fnmatch.fnmatch (RTL_name,"gpio_configure*"): continue #TODO: update gpio_configure and mgmt_gpio_data to get each bit in the SDF case
|
||||
RTL_reg_path = self.hk_hdl._id(RTL_name,False)
|
||||
size = RTL_reg_path.value.n_bits-1
|
||||
RTL_reg_val = RTL_reg_path.value[size-first_index:size-second_index]
|
||||
else :
|
||||
if field[1] in ["pwr_ctrl_out"]: continue #TODO: delete when reset value is spicified
|
||||
RTL_reg_path = self.hk_hdl._id(field[1],False)
|
||||
RTL_reg_val = RTL_reg_path.value
|
||||
if (RTL_reg_val.integer != field[6]):
|
||||
cocotb.log.error(f'[HK_whiteBox][reg_model_sb] mismatch in register {field[1]} in {key} expected val = {int(field[6])} actual val = {int(RTL_reg_val.binstr,2)} ' )
|
||||
else:
|
||||
cocotb.log.debug(f'[HK_whiteBox][reg_model_sb] match in register {field[1]} in {key} expected val = {field[6]} actual val = {RTL_reg_val.integer} ' )
|
||||
|
||||
class SB_name:
|
||||
def __init__(self,name) -> None:
|
||||
self._name=name
|
||||
|
||||
Loading…
Reference in New Issue