mirror of https://github.com/efabless/caravel.git
Numerous bug fixes, ending in clean full LVS for both caravel and caravan. (#76)
* (1) Modified the .magicrc file to set a default for PDK if not set in the environment. (2) Fixed the user ID programming layout to not leave holes behind when the script moves the vias around (similar to the handling of the GPIO defaults block). (3) Added substrate isolation to gpio_control_block and fixed the path references to the standard cells. (4) Fixed the four missing routes on the Caravan top level. (5) Reinstated the large rendered labels for the pads on both caravel and caravan. (6) Corrected the top level gate-level netlist for caravan to add the missing pins to the management core wrapper. (7) Did the same for the caravan top level RTL. (8) Created scripts to run full LVS including extracting the management core wrapper and reading all gate-level verilog submodules. (9) Moved all of the LVS scripts to the scripts directory. * Apply automatic changes to Manifest and README.rst * Made the changes from pull request #73 as they did not get merged successfully, and if merged now they will generate conflicts with this pull request in scripts/set_user_id.py. So it's easier to just manually add them to this pull request. * Apply automatic changes to Manifest and README.rst Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
This commit is contained in:
R. Timothy Edwards
GitHub
parent
6f99301588
commit
99518acd15
30
mag/.magicrc
30
mag/.magicrc
|
|
@ -14,7 +14,24 @@
|
|||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
puts stdout "Sourcing design .magicrc for technology $::env(PDK) ..."
|
||||
# Allow override of PDK path from environment variable PDKPATH. Failing
|
||||
# that, fall back on definitions of PDK_ROOT and PDK. If either of those
|
||||
# fails, substitute a default. If PDKPATH has been specified, then get
|
||||
# PDK_VARIANT from the tail of PDKPATH.
|
||||
|
||||
if {[catch {set PDKPATH $env(PDKPATH)}]} {
|
||||
if {[catch {set PDK_ROOT $env(PDK_ROOT)}]} {
|
||||
set PDK_ROOT /usr/share/pdk
|
||||
}
|
||||
if {[catch {set PDK_VARIANT $env(PDK)}]} {
|
||||
set PDK_VARIANT sky130A
|
||||
}
|
||||
set PDKPATH ${PDK_ROOT}/${PDK_VARIANT}
|
||||
} else {
|
||||
set PDK_VARIANT [file tail ${PDKPATH}]
|
||||
}
|
||||
|
||||
puts stdout "Sourcing design .magicrc for technology $PDK_VARIANT ..."
|
||||
|
||||
# Put grid on 0.005 pitch. This is important, as some commands don't
|
||||
# rescale the grid automatically (such as lef read?).
|
||||
|
|
@ -27,19 +44,14 @@ if {[lindex $scalefac 1] < 2} {
|
|||
drc off
|
||||
drc euclidean on
|
||||
|
||||
# Allow override of PDK path from environment variable PDKPATH
|
||||
if {[catch {set PDKPATH $env(PDKPATH)}]} {
|
||||
set PDKPATH "$::env(PDK_ROOT)/$::env(PDK)"
|
||||
}
|
||||
|
||||
# loading technology
|
||||
tech load $PDKPATH/libs.tech/magic/$::env(PDK).tech
|
||||
tech load $PDKPATH/libs.tech/magic/${PDK_VARIANT}.tech
|
||||
|
||||
# load device generator
|
||||
source $PDKPATH/libs.tech/magic/$::env(PDK).tcl
|
||||
source $PDKPATH/libs.tech/magic/${PDK_VARIANT}.tcl
|
||||
|
||||
# load bind keys (optional)
|
||||
# source $PDKPATH/libs.tech/magic/$::env(PDK)-BindKeys
|
||||
# source $PDKPATH/libs.tech/magic/${PDK_VARIANT}-BindKeys
|
||||
|
||||
# set units to lambda grid
|
||||
snap lambda
|
||||
|
|
|
|||
311
mag/caravan.mag
311
mag/caravan.mag
|
|
@ -1,9 +1,7 @@
|
|||
magic
|
||||
tech sky130A
|
||||
magscale 1 2
|
||||
timestamp 1649962643
|
||||
<< checkpaint >>
|
||||
rect -1260 -1260 718860 1038860
|
||||
timestamp 1650318811
|
||||
<< viali >>
|
||||
rect 658360 47209 658394 47243
|
||||
<< metal1 >>
|
||||
|
|
@ -12234,6 +12232,15 @@ rect 389416 226324 411168 226352
|
|||
rect 389416 226312 389422 226324
|
||||
rect 411162 226312 411168 226324
|
||||
rect 411220 226312 411226 226364
|
||||
rect 411896 226356 411902 226408
|
||||
rect 411954 226396 411960 226408
|
||||
rect 485546 226396 485552 226406
|
||||
rect 411954 226368 485552 226396
|
||||
rect 411954 226356 411960 226368
|
||||
rect 485546 226354 485552 226368
|
||||
rect 485604 226396 485610 226406
|
||||
rect 485604 226368 485612 226396
|
||||
rect 485604 226354 485610 226368
|
||||
rect 154482 226244 154488 226296
|
||||
rect 154540 226284 154546 226296
|
||||
rect 235074 226284 235080 226296
|
||||
|
|
@ -22020,6 +22027,8 @@ rect 368020 226312 368072 226364
|
|||
rect 369952 226312 370004 226364
|
||||
rect 389364 226312 389416 226364
|
||||
rect 411168 226312 411220 226364
|
||||
rect 411902 226356 411954 226408
|
||||
rect 485552 226354 485604 226406
|
||||
rect 154488 226244 154540 226296
|
||||
rect 235080 226244 235132 226296
|
||||
rect 354128 226244 354180 226296
|
||||
|
|
@ -32202,11 +32211,20 @@ rect 467748 265804 467800 265810
|
|||
rect 467748 265746 467800 265752
|
||||
rect 463332 265328 463384 265334
|
||||
rect 463332 265270 463384 265276
|
||||
rect 573060 262329 573088 262338
|
||||
rect 573044 262320 573104 262329
|
||||
rect 573044 262251 573104 262260
|
||||
rect 572234 259193 572262 259198
|
||||
rect 572218 259184 572278 259193
|
||||
rect 572218 259115 572278 259124
|
||||
rect 184938 258632 184994 258641
|
||||
rect 184938 258567 184994 258576
|
||||
rect 56508 256760 56560 256766
|
||||
rect 56508 256702 56560 256708
|
||||
rect 184952 253994 184980 258567
|
||||
rect 571410 255912 571438 255930
|
||||
rect 571385 255852 571394 255912
|
||||
rect 571454 255852 571463 255912
|
||||
rect 184860 253966 184980 253994
|
||||
rect 184860 246498 184888 253966
|
||||
rect 416778 252784 416834 252793
|
||||
|
|
@ -36379,8 +36397,6 @@ rect 410352 217410 410380 227666
|
|||
rect 410812 224913 410840 231676
|
||||
rect 411180 227633 411208 231676
|
||||
rect 411548 227730 411576 231676
|
||||
rect 414020 230104 414072 230110
|
||||
rect 414020 230046 414072 230052
|
||||
rect 411536 227724 411588 227730
|
||||
rect 411536 227666 411588 227672
|
||||
rect 411166 227624 411222 227633
|
||||
|
|
@ -36390,9 +36406,14 @@ rect 411076 227394 411128 227400
|
|||
rect 410798 224904 410854 224913
|
||||
rect 410798 224839 410854 224848
|
||||
rect 411088 223650 411116 227394
|
||||
rect 411914 226414 411942 231698
|
||||
rect 414020 230104 414072 230110
|
||||
rect 414020 230046 414072 230052
|
||||
rect 411996 226976 412048 226982
|
||||
rect 411996 226918 412048 226924
|
||||
rect 411902 226408 411954 226414
|
||||
rect 411168 226364 411220 226370
|
||||
rect 411902 226350 411954 226356
|
||||
rect 411168 226306 411220 226312
|
||||
rect 411180 226137 411208 226306
|
||||
rect 411166 226128 411222 226137
|
||||
|
|
@ -36881,6 +36902,34 @@ rect 488906 227352 488962 227361
|
|||
rect 488906 227287 488962 227296
|
||||
rect 488446 227216 488502 227225
|
||||
rect 488446 227151 488502 227160
|
||||
rect 485552 226406 485604 226412
|
||||
rect 485552 226348 485604 226354
|
||||
rect 464264 217382 464600 217410
|
||||
rect 465092 217382 465428 217410
|
||||
rect 465920 217382 466256 217410
|
||||
rect 466748 217382 467084 217410
|
||||
rect 467576 217382 467912 217410
|
||||
rect 468404 217382 468740 217410
|
||||
rect 469232 217382 469568 217410
|
||||
rect 470152 217382 470488 217410
|
||||
rect 470980 217382 471316 217410
|
||||
rect 471992 217382 472144 217410
|
||||
rect 472636 217382 472972 217410
|
||||
rect 473464 217382 473800 217410
|
||||
rect 474292 217382 474628 217410
|
||||
rect 475120 217382 475456 217410
|
||||
rect 476040 217382 476376 217410
|
||||
rect 476868 217382 477204 217410
|
||||
rect 477788 217382 478032 217410
|
||||
rect 478524 217382 478860 217410
|
||||
rect 479352 217382 479688 217410
|
||||
rect 480364 217382 480516 217410
|
||||
rect 481008 217382 481344 217410
|
||||
rect 481928 217382 482264 217410
|
||||
rect 483032 217382 483092 217410
|
||||
rect 483584 217382 483920 217410
|
||||
rect 484412 217382 484748 217410
|
||||
rect 485564 217388 485592 226348
|
||||
rect 487804 226228 487856 226234
|
||||
rect 487804 226170 487856 226176
|
||||
rect 487160 226092 487212 226098
|
||||
|
|
@ -36922,31 +36971,6 @@ rect 492770 223343 492826 223352
|
|||
rect 492266 217592 492318 217598
|
||||
rect 492266 217534 492318 217540
|
||||
rect 492278 217410 492306 217534
|
||||
rect 464264 217382 464600 217410
|
||||
rect 465092 217382 465428 217410
|
||||
rect 465920 217382 466256 217410
|
||||
rect 466748 217382 467084 217410
|
||||
rect 467576 217382 467912 217410
|
||||
rect 468404 217382 468740 217410
|
||||
rect 469232 217382 469568 217410
|
||||
rect 470152 217382 470488 217410
|
||||
rect 470980 217382 471316 217410
|
||||
rect 471992 217382 472144 217410
|
||||
rect 472636 217382 472972 217410
|
||||
rect 473464 217382 473800 217410
|
||||
rect 474292 217382 474628 217410
|
||||
rect 475120 217382 475456 217410
|
||||
rect 476040 217382 476376 217410
|
||||
rect 476868 217382 477204 217410
|
||||
rect 477788 217382 478032 217410
|
||||
rect 478524 217382 478860 217410
|
||||
rect 479352 217382 479688 217410
|
||||
rect 480364 217382 480516 217410
|
||||
rect 481008 217382 481344 217410
|
||||
rect 481928 217382 482264 217410
|
||||
rect 483032 217382 483092 217410
|
||||
rect 483584 217382 483920 217410
|
||||
rect 484412 217382 484748 217410
|
||||
rect 486344 217382 486740 217410
|
||||
rect 487172 217382 487232 217410
|
||||
rect 487816 217382 488152 217410
|
||||
|
|
@ -37488,8 +37512,6 @@ rect 567120 221785 567148 251194
|
|||
rect 567292 248464 567344 248470
|
||||
rect 567292 248406 567344 248412
|
||||
rect 567304 222193 567332 248406
|
||||
rect 654140 230988 654192 230994
|
||||
rect 654140 230930 654192 230936
|
||||
rect 567936 227792 567988 227798
|
||||
rect 567936 227734 567988 227740
|
||||
rect 567290 222184 567346 222193
|
||||
|
|
@ -37509,14 +37531,6 @@ rect 568580 222838 568632 222844
|
|||
rect 568592 217410 568620 222838
|
||||
rect 569328 217410 569356 227559
|
||||
rect 570248 217410 570276 227666
|
||||
rect 654152 226334 654180 230930
|
||||
rect 654152 226306 655192 226334
|
||||
rect 607588 223576 607640 223582
|
||||
rect 607588 223518 607640 223524
|
||||
rect 574374 222184 574430 222193
|
||||
rect 574374 222119 574430 222128
|
||||
rect 573546 221504 573602 221513
|
||||
rect 573546 221439 573602 221448
|
||||
rect 570880 217456 570932 217462
|
||||
rect 559300 217382 559636 217410
|
||||
rect 560450 217396 560524 217410
|
||||
|
|
@ -37540,6 +37554,20 @@ rect 568592 217382 568836 217410
|
|||
rect 569328 217382 569664 217410
|
||||
rect 570248 217404 570880 217410
|
||||
rect 570248 217398 570932 217404
|
||||
rect 570248 217382 570920 217398
|
||||
rect 571410 217348 571438 255852
|
||||
rect 572234 217352 572262 259115
|
||||
rect 573060 217364 573088 262251
|
||||
rect 654140 230988 654192 230994
|
||||
rect 654140 230930 654192 230936
|
||||
rect 654152 226334 654180 230930
|
||||
rect 654152 226306 655192 226334
|
||||
rect 607588 223576 607640 223582
|
||||
rect 607588 223518 607640 223524
|
||||
rect 574374 222184 574430 222193
|
||||
rect 574374 222119 574430 222128
|
||||
rect 573546 221504 573602 221513
|
||||
rect 573546 221439 573602 221448
|
||||
rect 573560 217410 573588 221439
|
||||
rect 574388 217410 574416 222119
|
||||
rect 575202 221776 575258 221785
|
||||
|
|
@ -37549,7 +37577,6 @@ rect 607128 218136 607180 218142
|
|||
rect 607128 218078 607180 218084
|
||||
rect 606668 218068 606720 218074
|
||||
rect 606668 218010 606720 218016
|
||||
rect 570248 217382 570920 217398
|
||||
rect 573560 217382 573896 217410
|
||||
rect 574388 217382 574724 217410
|
||||
rect 575216 217382 575552 217410
|
||||
|
|
@ -45457,7 +45484,10 @@ rect 636750 269320 636806 269376
|
|||
rect 645030 271768 645086 271824
|
||||
rect 646226 269184 646282 269240
|
||||
rect 648618 269048 648674 269104
|
||||
rect 573044 262260 573104 262320
|
||||
rect 572218 259124 572278 259184
|
||||
rect 184938 258576 184994 258632
|
||||
rect 571394 255852 571454 255912
|
||||
rect 416778 252728 416834 252784
|
||||
rect 416778 249464 416834 249520
|
||||
rect 187606 247968 187662 248024
|
||||
|
|
@ -52911,6 +52941,12 @@ rect 675937 262520 675942 262576
|
|||
rect 675998 262520 676292 262576
|
||||
rect 675937 262518 676292 262520
|
||||
rect 675937 262515 676003 262518
|
||||
rect 412380 262320 573116 262334
|
||||
rect 412380 262274 573044 262320
|
||||
rect 573039 262260 573044 262274
|
||||
rect 573104 262274 573116 262320
|
||||
rect 573104 262260 573109 262274
|
||||
rect 573039 262255 573109 262260
|
||||
rect 676029 262170 676095 262173
|
||||
rect 676029 262168 676292 262170
|
||||
rect 676029 262112 676034 262168
|
||||
|
|
@ -52960,6 +52996,13 @@ rect 676029 259256 676034 259312
|
|||
rect 676090 259256 676292 259312
|
||||
rect 676029 259254 676292 259256
|
||||
rect 676029 259251 676095 259254
|
||||
rect 572213 259186 572283 259189
|
||||
rect 412380 259184 572292 259186
|
||||
rect 412380 259126 572218 259184
|
||||
rect 572213 259124 572218 259126
|
||||
rect 572278 259126 572292 259184
|
||||
rect 572278 259124 572283 259126
|
||||
rect 572213 259119 572283 259124
|
||||
rect 676121 258770 676187 258773
|
||||
rect 676262 258770 676322 258876
|
||||
rect 676121 258768 676322 258770
|
||||
|
|
@ -53023,6 +53066,12 @@ rect 41462 256264 41510 256320
|
|||
rect 41566 256264 41571 256320
|
||||
rect 41462 256259 41571 256264
|
||||
rect 41462 256020 41522 256259
|
||||
rect 412336 255912 571470 255924
|
||||
rect 412336 255864 571394 255912
|
||||
rect 571389 255852 571394 255864
|
||||
rect 571454 255864 571470 255912
|
||||
rect 571454 255852 571459 255864
|
||||
rect 571389 255847 571459 255852
|
||||
rect 39990 255508 40050 255612
|
||||
rect 39982 255444 39988 255508
|
||||
rect 40052 255444 40058 255508
|
||||
|
|
@ -58804,111 +58853,111 @@ timestamp 1649951985
|
|||
transform 1 0 149318 0 1 16066
|
||||
box -262 -10162 35048 2764
|
||||
use gpio_control_block gpio_control_bidir_1\[0\]
|
||||
timestamp 1649446267
|
||||
timestamp 1650313688
|
||||
transform -1 0 710203 0 1 121000
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_bidir_1\[1\]
|
||||
timestamp 1649446267
|
||||
timestamp 1650313688
|
||||
transform -1 0 710203 0 1 166200
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_bidir_2\[0\]
|
||||
timestamp 1649446267
|
||||
timestamp 1650313688
|
||||
transform 1 0 7631 0 1 289000
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_bidir_2\[1\]
|
||||
timestamp 1649446267
|
||||
timestamp 1650313688
|
||||
transform 1 0 7631 0 1 245800
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_bidir_2\[2\]
|
||||
timestamp 1649446267
|
||||
timestamp 1650313688
|
||||
transform 1 0 7631 0 1 202600
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_in_1\[0\]
|
||||
timestamp 1649446267
|
||||
timestamp 1650313688
|
||||
transform -1 0 710203 0 1 523800
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_in_1\[1\]
|
||||
timestamp 1649446267
|
||||
timestamp 1650313688
|
||||
transform -1 0 710203 0 1 568800
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_in_1\[2\]
|
||||
timestamp 1649446267
|
||||
timestamp 1650313688
|
||||
transform -1 0 710203 0 1 614000
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_in_1\[3\]
|
||||
timestamp 1649446267
|
||||
timestamp 1650313688
|
||||
transform -1 0 710203 0 1 659000
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_in_1\[4\]
|
||||
timestamp 1649446267
|
||||
timestamp 1650313688
|
||||
transform -1 0 710203 0 1 704200
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_in_1\[5\]
|
||||
timestamp 1649446267
|
||||
timestamp 1650313688
|
||||
transform -1 0 710203 0 1 884800
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_in_1a\[0\]
|
||||
timestamp 1649446267
|
||||
timestamp 1650313688
|
||||
transform -1 0 710203 0 1 211200
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_in_1a\[1\]
|
||||
timestamp 1649446267
|
||||
timestamp 1650313688
|
||||
transform -1 0 710203 0 1 256400
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_in_1a\[2\]
|
||||
timestamp 1649446267
|
||||
timestamp 1650313688
|
||||
transform -1 0 710203 0 1 301400
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_in_1a\[3\]
|
||||
timestamp 1649446267
|
||||
timestamp 1650313688
|
||||
transform -1 0 710203 0 1 346400
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_in_1a\[4\]
|
||||
timestamp 1649446267
|
||||
timestamp 1650313688
|
||||
transform -1 0 710203 0 1 391600
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_in_1a\[5\]
|
||||
timestamp 1649446267
|
||||
timestamp 1650313688
|
||||
transform -1 0 710203 0 1 479800
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_in_2\[0\]
|
||||
timestamp 1649446267
|
||||
timestamp 1650313688
|
||||
transform 1 0 7631 0 1 805400
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_in_2\[1\]
|
||||
timestamp 1649446267
|
||||
timestamp 1650313688
|
||||
transform 1 0 7631 0 1 762200
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_in_2\[2\]
|
||||
timestamp 1649446267
|
||||
timestamp 1650313688
|
||||
transform 1 0 7631 0 1 719000
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_in_2\[3\]
|
||||
timestamp 1649446267
|
||||
timestamp 1650313688
|
||||
transform 1 0 7631 0 1 675800
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_in_2\[4\]
|
||||
timestamp 1649446267
|
||||
timestamp 1650313688
|
||||
transform 1 0 7631 0 1 632600
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_in_2\[5\]
|
||||
timestamp 1649446267
|
||||
timestamp 1650313688
|
||||
transform 1 0 7631 0 1 589400
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_in_2\[6\]
|
||||
timestamp 1649446267
|
||||
timestamp 1650313688
|
||||
transform 1 0 7631 0 1 546200
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_in_2\[7\]
|
||||
timestamp 1649446267
|
||||
timestamp 1650313688
|
||||
transform 1 0 7631 0 1 418600
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_in_2\[8\]
|
||||
timestamp 1649446267
|
||||
timestamp 1650313688
|
||||
transform 1 0 7631 0 1 375400
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_in_2\[9\]
|
||||
timestamp 1649446267
|
||||
timestamp 1650313688
|
||||
transform 1 0 7631 0 1 332200
|
||||
box 882 416 34000 13000
|
||||
use gpio_defaults_block gpio_defaults_block_0\[0\]
|
||||
|
|
@ -59080,131 +59129,131 @@ timestamp 1638030917
|
|||
transform 1 0 656624 0 1 88126
|
||||
box 0 0 7109 7077
|
||||
<< labels >>
|
||||
rlabel metal5 s 187640 6598 200160 19088 6 clock
|
||||
flabel metal5 s 187640 6598 200160 19088 0 FreeSans 25000 0 0 0 clock
|
||||
port 0 nsew signal input
|
||||
rlabel metal5 s 351040 6598 363560 19088 6 flash_clk
|
||||
flabel metal5 s 351040 6598 363560 19088 0 FreeSans 25000 0 0 0 flash_clk
|
||||
port 1 nsew signal tristate
|
||||
rlabel metal5 s 296240 6598 308760 19088 6 flash_csb
|
||||
flabel metal5 s 296240 6598 308760 19088 0 FreeSans 25000 0 0 0 flash_csb
|
||||
port 2 nsew signal tristate
|
||||
rlabel metal5 s 405840 6598 418360 19088 6 flash_io0
|
||||
flabel metal5 s 405840 6598 418360 19088 0 FreeSans 25000 0 0 0 flash_io0
|
||||
port 3 nsew signal tristate
|
||||
rlabel metal5 s 460640 6598 473160 19088 6 flash_io1
|
||||
flabel metal5 s 460640 6598 473160 19088 0 FreeSans 25000 0 0 0 flash_io1
|
||||
port 4 nsew signal tristate
|
||||
rlabel metal5 s 515440 6598 527960 19088 6 gpio
|
||||
flabel metal5 s 515440 6598 527960 19088 0 FreeSans 25000 0 0 0 gpio
|
||||
port 5 nsew signal bidirectional
|
||||
rlabel metal5 s 698512 101240 711002 113760 6 mprj_io[0]
|
||||
flabel metal5 s 698512 101240 711002 113760 0 FreeSans 25000 0 0 0 mprj_io[0]
|
||||
port 6 nsew signal bidirectional
|
||||
rlabel metal5 s 698512 684440 711002 696960 6 mprj_io[10]
|
||||
flabel metal5 s 698512 684440 711002 696960 0 FreeSans 25000 0 0 0 mprj_io[10]
|
||||
port 7 nsew signal bidirectional
|
||||
rlabel metal5 s 698512 729440 711002 741960 6 mprj_io[11]
|
||||
flabel metal5 s 698512 729440 711002 741960 0 FreeSans 25000 0 0 0 mprj_io[11]
|
||||
port 8 nsew signal bidirectional
|
||||
rlabel metal5 s 698512 774440 711002 786960 6 mprj_io[12]
|
||||
flabel metal5 s 698512 774440 711002 786960 0 FreeSans 25000 0 0 0 mprj_io[12]
|
||||
port 9 nsew signal bidirectional
|
||||
rlabel metal5 s 698512 863640 711002 876160 6 mprj_io[13]
|
||||
flabel metal5 s 698512 863640 711002 876160 0 FreeSans 25000 0 0 0 mprj_io[13]
|
||||
port 10 nsew signal bidirectional
|
||||
rlabel metal5 s 698624 953022 710788 965190 6 mprj_io[14]
|
||||
flabel metal5 s 698624 953022 710788 965190 0 FreeSans 25000 0 0 0 mprj_io[14]
|
||||
port 11 nsew signal bidirectional
|
||||
rlabel metal5 s 628410 1018624 640578 1030788 6 mprj_io[15]
|
||||
flabel metal5 s 628410 1018624 640578 1030788 0 FreeSans 25000 0 0 0 mprj_io[15]
|
||||
port 12 nsew signal bidirectional
|
||||
rlabel metal5 s 526610 1018624 538778 1030788 6 mprj_io[16]
|
||||
flabel metal5 s 526610 1018624 538778 1030788 0 FreeSans 25000 0 0 0 mprj_io[16]
|
||||
port 13 nsew signal bidirectional
|
||||
rlabel metal5 s 475210 1018624 487378 1030788 6 mprj_io[17]
|
||||
flabel metal5 s 475210 1018624 487378 1030788 0 FreeSans 25000 0 0 0 mprj_io[17]
|
||||
port 14 nsew signal bidirectional
|
||||
rlabel metal5 s 386210 1018624 398378 1030788 6 mprj_io[18]
|
||||
flabel metal5 s 386210 1018624 398378 1030788 0 FreeSans 25000 0 0 0 mprj_io[18]
|
||||
port 15 nsew signal bidirectional
|
||||
rlabel metal5 s 284410 1018624 296578 1030788 6 mprj_io[19]
|
||||
flabel metal5 s 284410 1018624 296578 1030788 0 FreeSans 25000 0 0 0 mprj_io[19]
|
||||
port 16 nsew signal bidirectional
|
||||
rlabel metal5 s 698512 146440 711002 158960 6 mprj_io[1]
|
||||
flabel metal5 s 698512 146440 711002 158960 0 FreeSans 25000 0 0 0 mprj_io[1]
|
||||
port 17 nsew signal bidirectional
|
||||
rlabel metal5 s 231810 1018624 243978 1030788 6 mprj_io[20]
|
||||
flabel metal5 s 231810 1018624 243978 1030788 0 FreeSans 25000 0 0 0 mprj_io[20]
|
||||
port 18 nsew signal bidirectional
|
||||
rlabel metal5 s 181410 1018624 193578 1030788 6 mprj_io[21]
|
||||
flabel metal5 s 181410 1018624 193578 1030788 0 FreeSans 25000 0 0 0 mprj_io[21]
|
||||
port 19 nsew signal bidirectional
|
||||
rlabel metal5 s 130010 1018624 142178 1030788 6 mprj_io[22]
|
||||
flabel metal5 s 130010 1018624 142178 1030788 0 FreeSans 25000 0 0 0 mprj_io[22]
|
||||
port 20 nsew signal bidirectional
|
||||
rlabel metal5 s 78610 1018624 90778 1030788 6 mprj_io[23]
|
||||
flabel metal5 s 78610 1018624 90778 1030788 0 FreeSans 25000 0 0 0 mprj_io[23]
|
||||
port 21 nsew signal bidirectional
|
||||
rlabel metal5 s 6811 956610 18975 968778 6 mprj_io[24]
|
||||
flabel metal5 s 6811 956610 18975 968778 0 FreeSans 25000 0 0 0 mprj_io[24]
|
||||
port 22 nsew signal bidirectional
|
||||
rlabel metal5 s 6598 786640 19088 799160 6 mprj_io[25]
|
||||
flabel metal5 s 6598 786640 19088 799160 0 FreeSans 25000 0 0 0 mprj_io[25]
|
||||
port 23 nsew signal bidirectional
|
||||
rlabel metal5 s 6598 743440 19088 755960 6 mprj_io[26]
|
||||
flabel metal5 s 6598 743440 19088 755960 0 FreeSans 25000 0 0 0 mprj_io[26]
|
||||
port 24 nsew signal bidirectional
|
||||
rlabel metal5 s 6598 700240 19088 712760 6 mprj_io[27]
|
||||
flabel metal5 s 6598 700240 19088 712760 0 FreeSans 25000 0 0 0 mprj_io[27]
|
||||
port 25 nsew signal bidirectional
|
||||
rlabel metal5 s 6598 657040 19088 669560 6 mprj_io[28]
|
||||
flabel metal5 s 6598 657040 19088 669560 0 FreeSans 25000 0 0 0 mprj_io[28]
|
||||
port 26 nsew signal bidirectional
|
||||
rlabel metal5 s 6598 613840 19088 626360 6 mprj_io[29]
|
||||
flabel metal5 s 6598 613840 19088 626360 0 FreeSans 25000 0 0 0 mprj_io[29]
|
||||
port 27 nsew signal bidirectional
|
||||
rlabel metal5 s 698512 191440 711002 203960 6 mprj_io[2]
|
||||
flabel metal5 s 698512 191440 711002 203960 0 FreeSans 25000 0 0 0 mprj_io[2]
|
||||
port 28 nsew signal bidirectional
|
||||
rlabel metal5 s 6598 570640 19088 583160 6 mprj_io[30]
|
||||
flabel metal5 s 6598 570640 19088 583160 0 FreeSans 25000 0 0 0 mprj_io[30]
|
||||
port 29 nsew signal bidirectional
|
||||
rlabel metal5 s 6598 527440 19088 539960 6 mprj_io[31]
|
||||
flabel metal5 s 6598 527440 19088 539960 0 FreeSans 25000 0 0 0 mprj_io[31]
|
||||
port 30 nsew signal bidirectional
|
||||
rlabel metal5 s 6598 399840 19088 412360 6 mprj_io[32]
|
||||
flabel metal5 s 6598 399840 19088 412360 0 FreeSans 25000 0 0 0 mprj_io[32]
|
||||
port 31 nsew signal bidirectional
|
||||
rlabel metal5 s 6598 356640 19088 369160 6 mprj_io[33]
|
||||
flabel metal5 s 6598 356640 19088 369160 0 FreeSans 25000 0 0 0 mprj_io[33]
|
||||
port 32 nsew signal bidirectional
|
||||
rlabel metal5 s 6598 313440 19088 325960 6 mprj_io[34]
|
||||
flabel metal5 s 6598 313440 19088 325960 0 FreeSans 25000 0 0 0 mprj_io[34]
|
||||
port 33 nsew signal bidirectional
|
||||
rlabel metal5 s 6598 270240 19088 282760 6 mprj_io[35]
|
||||
flabel metal5 s 6598 270240 19088 282760 0 FreeSans 25000 0 0 0 mprj_io[35]
|
||||
port 34 nsew signal bidirectional
|
||||
rlabel metal5 s 6598 227040 19088 239560 6 mprj_io[36]
|
||||
flabel metal5 s 6598 227040 19088 239560 0 FreeSans 25000 0 0 0 mprj_io[36]
|
||||
port 35 nsew signal bidirectional
|
||||
rlabel metal5 s 6598 183840 19088 196360 6 mprj_io[37]
|
||||
flabel metal5 s 6598 183840 19088 196360 0 FreeSans 25000 0 0 0 mprj_io[37]
|
||||
port 36 nsew signal bidirectional
|
||||
rlabel metal5 s 698512 236640 711002 249160 6 mprj_io[3]
|
||||
flabel metal5 s 698512 236640 711002 249160 0 FreeSans 25000 0 0 0 mprj_io[3]
|
||||
port 37 nsew signal bidirectional
|
||||
rlabel metal5 s 698512 281640 711002 294160 6 mprj_io[4]
|
||||
flabel metal5 s 698512 281640 711002 294160 0 FreeSans 25000 0 0 0 mprj_io[4]
|
||||
port 38 nsew signal bidirectional
|
||||
rlabel metal5 s 698512 326640 711002 339160 6 mprj_io[5]
|
||||
flabel metal5 s 698512 326640 711002 339160 0 FreeSans 25000 0 0 0 mprj_io[5]
|
||||
port 39 nsew signal bidirectional
|
||||
rlabel metal5 s 698512 371840 711002 384360 6 mprj_io[6]
|
||||
flabel metal5 s 698512 371840 711002 384360 0 FreeSans 25000 0 0 0 mprj_io[6]
|
||||
port 40 nsew signal bidirectional
|
||||
rlabel metal5 s 698512 549040 711002 561560 6 mprj_io[7]
|
||||
flabel metal5 s 698512 549040 711002 561560 0 FreeSans 25000 0 0 0 mprj_io[7]
|
||||
port 41 nsew signal bidirectional
|
||||
rlabel metal5 s 698512 594240 711002 606760 6 mprj_io[8]
|
||||
flabel metal5 s 698512 594240 711002 606760 0 FreeSans 25000 0 0 0 mprj_io[8]
|
||||
port 42 nsew signal bidirectional
|
||||
rlabel metal5 s 698512 639240 711002 651760 6 mprj_io[9]
|
||||
flabel metal5 s 698512 639240 711002 651760 0 FreeSans 25000 0 0 0 mprj_io[9]
|
||||
port 43 nsew signal bidirectional
|
||||
rlabel metal5 s 136713 7143 144149 18309 6 resetb
|
||||
flabel metal5 s 136713 7143 144149 18309 0 FreeSans 25000 0 0 0 resetb
|
||||
port 44 nsew signal input
|
||||
rlabel metal5 s 697980 909666 711432 920546 6 vccd1
|
||||
flabel metal5 s 697980 909666 711432 920546 0 FreeSans 25000 0 0 0 vccd1
|
||||
port 45 nsew signal bidirectional
|
||||
rlabel metal5 s 6167 914054 19619 924934 6 vccd2
|
||||
flabel metal5 s 6167 914054 19619 924934 0 FreeSans 25000 0 0 0 vccd2
|
||||
port 46 nsew signal bidirectional
|
||||
rlabel metal5 s 624222 6811 636390 18975 6 vdda
|
||||
flabel metal5 s 624222 6811 636390 18975 0 FreeSans 25000 0 0 0 vdda
|
||||
port 47 nsew signal bidirectional
|
||||
rlabel metal5 s 698624 819822 710788 831990 6 vdda1
|
||||
flabel metal5 s 698624 819822 710788 831990 0 FreeSans 25000 0 0 0 vdda1
|
||||
port 48 nsew signal bidirectional
|
||||
rlabel metal5 s 698624 505222 710788 517390 6 vdda1_2
|
||||
flabel metal5 s 698624 505222 710788 517390 0 FreeSans 25000 0 0 0 vdda1_2
|
||||
port 49 nsew signal bidirectional
|
||||
rlabel metal5 s 6811 484410 18975 496578 6 vdda2
|
||||
flabel metal5 s 6811 484410 18975 496578 0 FreeSans 25000 0 0 0 vdda2
|
||||
port 50 nsew signal bidirectional
|
||||
rlabel metal5 s 6811 871210 18975 883378 6 vddio_2
|
||||
flabel metal5 s 6811 871210 18975 883378 0 FreeSans 25000 0 0 0 vddio_2
|
||||
port 51 nsew signal bidirectional
|
||||
rlabel metal5 s 577010 1018624 589178 1030788 6 vssa1
|
||||
flabel metal5 s 577010 1018624 589178 1030788 0 FreeSans 25000 0 0 0 vssa1
|
||||
port 52 nsew signal bidirectional
|
||||
rlabel metal5 s 698624 417022 710788 429190 6 vssa1_2
|
||||
flabel metal5 s 698624 417022 710788 429190 0 FreeSans 25000 0 0 0 vssa1_2
|
||||
port 53 nsew signal bidirectional
|
||||
rlabel metal5 s 6811 829010 18975 841178 6 vssa2
|
||||
flabel metal5 s 6811 829010 18975 841178 0 FreeSans 25000 0 0 0 vssa2
|
||||
port 54 nsew signal bidirectional
|
||||
rlabel metal5 s 697980 461866 711432 472746 6 vssd1
|
||||
flabel metal5 s 697980 461866 711432 472746 0 FreeSans 25000 0 0 0 vssd1
|
||||
port 55 nsew signal bidirectional
|
||||
rlabel metal5 s 6167 442854 19619 453734 6 vssd2
|
||||
flabel metal5 s 6167 442854 19619 453734 0 FreeSans 25000 0 0 0 vssd2
|
||||
port 56 nsew signal bidirectional
|
||||
rlabel metal5 s 334810 1018624 346978 1030788 6 vssio_2
|
||||
flabel metal5 s 334810 1018624 346978 1030788 0 FreeSans 25000 0 0 0 vssio_2
|
||||
port 57 nsew signal bidirectional
|
||||
rlabel metal5 s 6811 111610 18975 123778 6 vddio
|
||||
flabel metal5 s 6811 111610 18975 123778 0 FreeSans 25000 0 0 0 vddio
|
||||
port 58 nsew signal bidirectional
|
||||
rlabel metal5 s 570422 6811 582590 18975 6 vssio
|
||||
flabel metal5 s 570422 6811 582590 18975 0 FreeSans 25000 0 0 0 vssio
|
||||
port 59 nsew signal bidirectional
|
||||
rlabel metal5 s 80222 6811 92390 18975 6 vssa
|
||||
flabel metal5 s 80222 6811 92390 18975 0 FreeSans 25000 0 0 0 vssa
|
||||
port 60 nsew signal bidirectional
|
||||
rlabel metal5 s 6167 70054 19619 80934 6 vccd
|
||||
flabel metal5 s 6167 70054 19619 80934 0 FreeSans 25000 0 0 0 vccd
|
||||
port 61 nsew signal bidirectional
|
||||
rlabel metal5 s 243266 6167 254146 19619 6 vssd
|
||||
flabel metal5 s 243266 6167 254146 19619 0 FreeSans 25000 0 0 0 vssd
|
||||
port 62 nsew signal bidirectional
|
||||
<< properties >>
|
||||
string FIXED_BBOX 0 0 717600 1037600
|
||||
|
|
|
|||
344
mag/caravel.mag
344
mag/caravel.mag
|
|
@ -73721,155 +73721,155 @@ timestamp 1649268499
|
|||
transform 1 0 149554 0 1 16026
|
||||
box -262 -10348 35048 2764
|
||||
use gpio_control_block gpio_control_bidir_1\[0\]
|
||||
timestamp 1649446267
|
||||
timestamp 1649688056
|
||||
transform -1 0 710203 0 1 121000
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_bidir_1\[1\]
|
||||
timestamp 1649446267
|
||||
timestamp 1649688056
|
||||
transform -1 0 710203 0 1 166200
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_bidir_2\[0\]
|
||||
timestamp 1649446267
|
||||
timestamp 1649688056
|
||||
transform 1 0 7631 0 1 289000
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_bidir_2\[1\]
|
||||
timestamp 1649446267
|
||||
timestamp 1649688056
|
||||
transform 1 0 7631 0 1 245800
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_bidir_2\[2\]
|
||||
timestamp 1649446267
|
||||
timestamp 1649688056
|
||||
transform 1 0 7631 0 1 202600
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_in_1\[0\]
|
||||
timestamp 1649446267
|
||||
timestamp 1649688056
|
||||
transform -1 0 710203 0 1 523800
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_in_1\[1\]
|
||||
timestamp 1649446267
|
||||
timestamp 1649688056
|
||||
transform -1 0 710203 0 1 568800
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_in_1\[2\]
|
||||
timestamp 1649446267
|
||||
timestamp 1649688056
|
||||
transform -1 0 710203 0 1 614000
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_in_1\[3\]
|
||||
timestamp 1649446267
|
||||
timestamp 1649688056
|
||||
transform -1 0 710203 0 1 659000
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_in_1\[4\]
|
||||
timestamp 1649446267
|
||||
timestamp 1649688056
|
||||
transform -1 0 710203 0 1 704200
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_in_1\[5\]
|
||||
timestamp 1649446267
|
||||
timestamp 1649688056
|
||||
transform -1 0 710203 0 1 749200
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_in_1\[6\]
|
||||
timestamp 1649446267
|
||||
timestamp 1649688056
|
||||
transform -1 0 710203 0 1 927600
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_in_1\[7\]
|
||||
timestamp 1649446267
|
||||
timestamp 1649688056
|
||||
transform 0 1 549200 -1 0 1030077
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_in_1\[8\]
|
||||
timestamp 1649446267
|
||||
timestamp 1649688056
|
||||
transform 0 1 497800 -1 0 1030077
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_in_1\[9\]
|
||||
timestamp 1649446267
|
||||
timestamp 1649688056
|
||||
transform 0 1 420800 -1 0 1030077
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_in_1\[10\]
|
||||
timestamp 1649446267
|
||||
timestamp 1649688056
|
||||
transform 0 1 353400 -1 0 1030077
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_in_1a\[0\]
|
||||
timestamp 1649446267
|
||||
timestamp 1649688056
|
||||
transform -1 0 710203 0 1 211200
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_in_1a\[1\]
|
||||
timestamp 1649446267
|
||||
timestamp 1649688056
|
||||
transform -1 0 710203 0 1 256400
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_in_1a\[2\]
|
||||
timestamp 1649446267
|
||||
timestamp 1649688056
|
||||
transform -1 0 710203 0 1 301400
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_in_1a\[3\]
|
||||
timestamp 1649446267
|
||||
timestamp 1649688056
|
||||
transform -1 0 710203 0 1 346400
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_in_1a\[4\]
|
||||
timestamp 1649446267
|
||||
timestamp 1649688056
|
||||
transform -1 0 710203 0 1 391600
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_in_1a\[5\]
|
||||
timestamp 1649446267
|
||||
timestamp 1649688056
|
||||
transform -1 0 710203 0 1 479800
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_in_2\[0\]
|
||||
timestamp 1649446267
|
||||
timestamp 1649688056
|
||||
transform 0 1 303000 -1 0 1030077
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_in_2\[1\]
|
||||
timestamp 1649446267
|
||||
timestamp 1649688056
|
||||
transform 0 1 251400 -1 0 1030077
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_in_2\[2\]
|
||||
timestamp 1649446267
|
||||
timestamp 1649688056
|
||||
transform 0 1 200000 -1 0 1030077
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_in_2\[3\]
|
||||
timestamp 1649446267
|
||||
timestamp 1649688056
|
||||
transform 0 1 148600 -1 0 1030077
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_in_2\[4\]
|
||||
timestamp 1649446267
|
||||
timestamp 1649688056
|
||||
transform 0 1 97200 -1 0 1030077
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_in_2\[5\]
|
||||
timestamp 1649446267
|
||||
timestamp 1649688056
|
||||
transform 1 0 7631 0 1 931200
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_in_2\[6\]
|
||||
timestamp 1649446267
|
||||
timestamp 1649688056
|
||||
transform 1 0 7631 0 1 805400
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_in_2\[7\]
|
||||
timestamp 1649446267
|
||||
timestamp 1649688056
|
||||
transform 1 0 7631 0 1 762200
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_in_2\[8\]
|
||||
timestamp 1649446267
|
||||
timestamp 1649688056
|
||||
transform 1 0 7631 0 1 719000
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_in_2\[9\]
|
||||
timestamp 1649446267
|
||||
timestamp 1649688056
|
||||
transform 1 0 7631 0 1 675800
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_in_2\[10\]
|
||||
timestamp 1649446267
|
||||
timestamp 1649688056
|
||||
transform 1 0 7631 0 1 632600
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_in_2\[11\]
|
||||
timestamp 1649446267
|
||||
timestamp 1649688056
|
||||
transform 1 0 7631 0 1 589400
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_in_2\[12\]
|
||||
timestamp 1649446267
|
||||
timestamp 1649688056
|
||||
transform 1 0 7631 0 1 546200
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_in_2\[13\]
|
||||
timestamp 1649446267
|
||||
timestamp 1649688056
|
||||
transform 1 0 7631 0 1 418600
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_in_2\[14\]
|
||||
timestamp 1649446267
|
||||
timestamp 1649688056
|
||||
transform 1 0 7631 0 1 375400
|
||||
box 882 416 34000 13000
|
||||
use gpio_control_block gpio_control_in_2\[15\]
|
||||
timestamp 1649446267
|
||||
timestamp 1649688056
|
||||
transform 1 0 7631 0 1 332200
|
||||
box 882 416 34000 13000
|
||||
use gpio_defaults_block gpio_defaults_block_0\[0\]
|
||||
|
|
@ -74029,7 +74029,7 @@ timestamp 1638464048
|
|||
transform 1 0 606434 0 1 100002
|
||||
box 0 0 60046 110190
|
||||
use mgmt_protect mgmt_buffers
|
||||
timestamp 1649327869
|
||||
timestamp 1649962643
|
||||
transform 1 0 192180 0 1 232036
|
||||
box -400 -400 220400 32400
|
||||
use user_project_wrapper mprj
|
||||
|
|
@ -74085,258 +74085,132 @@ timestamp 1638030917
|
|||
transform 1 0 656624 0 1 88126
|
||||
box 0 0 7109 7077
|
||||
<< labels >>
|
||||
rlabel metal5 s 187640 6598 200160 19088 6 clock
|
||||
flabel metal5 s 187640 6598 200160 19088 0 FreeSans 25000 0 0 0 clock
|
||||
port 0 nsew signal input
|
||||
rlabel metal5 s 187640 6598 200160 19088 6 clock
|
||||
port 1 nsew signal input
|
||||
rlabel metal5 s 351040 6598 363560 19088 6 flash_clk
|
||||
flabel metal5 s 351040 6598 363560 19088 0 FreeSans 25000 0 0 0 flash_clk
|
||||
port 1 nsew signal tristate
|
||||
flabel metal5 s 296240 6598 308760 19088 0 FreeSans 25000 0 0 0 flash_csb
|
||||
port 2 nsew signal tristate
|
||||
rlabel metal5 s 351040 6598 363560 19088 6 flash_clk
|
||||
flabel metal5 s 405840 6598 418360 19088 0 FreeSans 25000 0 0 0 flash_io0
|
||||
port 3 nsew signal tristate
|
||||
rlabel metal5 s 296240 6598 308760 19088 6 flash_csb
|
||||
flabel metal5 s 460640 6598 473160 19088 0 FreeSans 25000 0 0 0 flash_io1
|
||||
port 4 nsew signal tristate
|
||||
rlabel metal5 s 296240 6598 308760 19088 6 flash_csb
|
||||
port 5 nsew signal tristate
|
||||
rlabel metal5 s 405840 6598 418360 19088 6 flash_io0
|
||||
port 6 nsew signal tristate
|
||||
rlabel metal5 s 405840 6598 418360 19088 6 flash_io0
|
||||
port 7 nsew signal tristate
|
||||
rlabel metal5 s 460640 6598 473160 19088 6 flash_io1
|
||||
port 8 nsew signal tristate
|
||||
rlabel metal5 s 460640 6598 473160 19088 6 flash_io1
|
||||
port 9 nsew signal tristate
|
||||
rlabel metal5 s 515440 6598 527960 19088 6 gpio
|
||||
flabel metal5 s 515440 6598 527960 19088 0 FreeSans 25000 0 0 0 gpio
|
||||
port 5 nsew signal bidirectional
|
||||
flabel metal5 s 698512 101240 711002 113760 0 FreeSans 25000 0 0 0 mprj_io[0]
|
||||
port 6 nsew signal bidirectional
|
||||
flabel metal5 s 698512 684440 711002 696960 0 FreeSans 25000 0 0 0 mprj_io[10]
|
||||
port 7 nsew signal bidirectional
|
||||
flabel metal5 s 698512 729440 711002 741960 0 FreeSans 25000 0 0 0 mprj_io[11]
|
||||
port 8 nsew signal bidirectional
|
||||
flabel metal5 s 698512 774440 711002 786960 0 FreeSans 25000 0 0 0 mprj_io[12]
|
||||
port 9 nsew signal bidirectional
|
||||
flabel metal5 s 698512 863640 711002 876160 0 FreeSans 25000 0 0 0 mprj_io[13]
|
||||
port 10 nsew signal bidirectional
|
||||
rlabel metal5 s 515440 6598 527960 19088 6 gpio
|
||||
flabel metal5 s 698512 952840 711002 965360 0 FreeSans 25000 0 0 0 mprj_io[14]
|
||||
port 11 nsew signal bidirectional
|
||||
rlabel metal5 s 698512 101240 711002 113760 6 mprj_io[0]
|
||||
flabel metal5 s 628240 1018512 640760 1031002 0 FreeSans 25000 0 0 0 mprj_io[15]
|
||||
port 12 nsew signal bidirectional
|
||||
rlabel metal5 s 698512 101240 711002 113760 6 mprj_io[0]
|
||||
flabel metal5 s 526440 1018512 538960 1031002 0 FreeSans 25000 0 0 0 mprj_io[16]
|
||||
port 13 nsew signal bidirectional
|
||||
rlabel metal5 s 698512 684440 711002 696960 6 mprj_io[10]
|
||||
flabel metal5 s 475040 1018512 487560 1031002 0 FreeSans 25000 0 0 0 mprj_io[17]
|
||||
port 14 nsew signal bidirectional
|
||||
rlabel metal5 s 698512 684440 711002 696960 6 mprj_io[10]
|
||||
flabel metal5 s 386040 1018512 398560 1031002 0 FreeSans 25000 0 0 0 mprj_io[18]
|
||||
port 15 nsew signal bidirectional
|
||||
rlabel metal5 s 698512 729440 711002 741960 6 mprj_io[11]
|
||||
flabel metal5 s 284240 1018512 296760 1031002 0 FreeSans 25000 0 0 0 mprj_io[19]
|
||||
port 16 nsew signal bidirectional
|
||||
rlabel metal5 s 698512 729440 711002 741960 6 mprj_io[11]
|
||||
flabel metal5 s 698512 146440 711002 158960 0 FreeSans 25000 0 0 0 mprj_io[1]
|
||||
port 17 nsew signal bidirectional
|
||||
rlabel metal5 s 698512 774440 711002 786960 6 mprj_io[12]
|
||||
flabel metal5 s 232640 1018512 245160 1031002 0 FreeSans 25000 0 0 0 mprj_io[20]
|
||||
port 18 nsew signal bidirectional
|
||||
rlabel metal5 s 698512 774440 711002 786960 6 mprj_io[12]
|
||||
flabel metal5 s 181240 1018512 193760 1031002 0 FreeSans 25000 0 0 0 mprj_io[21]
|
||||
port 19 nsew signal bidirectional
|
||||
rlabel metal5 s 698512 863640 711002 876160 6 mprj_io[13]
|
||||
flabel metal5 s 129840 1018512 142360 1031002 0 FreeSans 25000 0 0 0 mprj_io[22]
|
||||
port 20 nsew signal bidirectional
|
||||
rlabel metal5 s 698512 863640 711002 876160 6 mprj_io[13]
|
||||
flabel metal5 s 78440 1018512 90960 1031002 0 FreeSans 25000 0 0 0 mprj_io[23]
|
||||
port 21 nsew signal bidirectional
|
||||
rlabel metal5 s 698512 952840 711002 965360 6 mprj_io[14]
|
||||
flabel metal5 s 6598 956440 19088 968960 0 FreeSans 25000 0 0 0 mprj_io[24]
|
||||
port 22 nsew signal bidirectional
|
||||
rlabel metal5 s 698512 952840 711002 965360 6 mprj_io[14]
|
||||
flabel metal5 s 6598 786640 19088 799160 0 FreeSans 25000 0 0 0 mprj_io[25]
|
||||
port 23 nsew signal bidirectional
|
||||
rlabel metal5 s 628240 1018512 640760 1031002 6 mprj_io[15]
|
||||
flabel metal5 s 6598 743440 19088 755960 0 FreeSans 25000 0 0 0 mprj_io[26]
|
||||
port 24 nsew signal bidirectional
|
||||
rlabel metal5 s 628240 1018512 640760 1031002 6 mprj_io[15]
|
||||
flabel metal5 s 6598 700240 19088 712760 0 FreeSans 25000 0 0 0 mprj_io[27]
|
||||
port 25 nsew signal bidirectional
|
||||
rlabel metal5 s 526440 1018512 538960 1031002 6 mprj_io[16]
|
||||
flabel metal5 s 6598 657040 19088 669560 0 FreeSans 25000 0 0 0 mprj_io[28]
|
||||
port 26 nsew signal bidirectional
|
||||
rlabel metal5 s 526440 1018512 538960 1031002 6 mprj_io[16]
|
||||
flabel metal5 s 6598 613840 19088 626360 0 FreeSans 25000 0 0 0 mprj_io[29]
|
||||
port 27 nsew signal bidirectional
|
||||
rlabel metal5 s 475040 1018512 487560 1031002 6 mprj_io[17]
|
||||
flabel metal5 s 698512 191440 711002 203960 0 FreeSans 25000 0 0 0 mprj_io[2]
|
||||
port 28 nsew signal bidirectional
|
||||
rlabel metal5 s 475040 1018512 487560 1031002 6 mprj_io[17]
|
||||
flabel metal5 s 6598 570640 19088 583160 0 FreeSans 25000 0 0 0 mprj_io[30]
|
||||
port 29 nsew signal bidirectional
|
||||
rlabel metal5 s 386040 1018512 398560 1031002 6 mprj_io[18]
|
||||
flabel metal5 s 6598 527440 19088 539960 0 FreeSans 25000 0 0 0 mprj_io[31]
|
||||
port 30 nsew signal bidirectional
|
||||
rlabel metal5 s 386040 1018512 398560 1031002 6 mprj_io[18]
|
||||
flabel metal5 s 6598 399840 19088 412360 0 FreeSans 25000 0 0 0 mprj_io[32]
|
||||
port 31 nsew signal bidirectional
|
||||
rlabel metal5 s 284240 1018512 296760 1031002 6 mprj_io[19]
|
||||
flabel metal5 s 6598 356640 19088 369160 0 FreeSans 25000 0 0 0 mprj_io[33]
|
||||
port 32 nsew signal bidirectional
|
||||
rlabel metal5 s 284240 1018512 296760 1031002 6 mprj_io[19]
|
||||
flabel metal5 s 6598 313440 19088 325960 0 FreeSans 25000 0 0 0 mprj_io[34]
|
||||
port 33 nsew signal bidirectional
|
||||
rlabel metal5 s 698512 146440 711002 158960 6 mprj_io[1]
|
||||
flabel metal5 s 6598 270240 19088 282760 0 FreeSans 25000 0 0 0 mprj_io[35]
|
||||
port 34 nsew signal bidirectional
|
||||
rlabel metal5 s 698512 146440 711002 158960 6 mprj_io[1]
|
||||
flabel metal5 s 6598 227040 19088 239560 0 FreeSans 25000 0 0 0 mprj_io[36]
|
||||
port 35 nsew signal bidirectional
|
||||
rlabel metal5 s 232640 1018512 245160 1031002 6 mprj_io[20]
|
||||
flabel metal5 s 6598 183840 19088 196360 0 FreeSans 25000 0 0 0 mprj_io[37]
|
||||
port 36 nsew signal bidirectional
|
||||
rlabel metal5 s 232640 1018512 245160 1031002 6 mprj_io[20]
|
||||
flabel metal5 s 698512 236640 711002 249160 0 FreeSans 25000 0 0 0 mprj_io[3]
|
||||
port 37 nsew signal bidirectional
|
||||
rlabel metal5 s 181240 1018512 193760 1031002 6 mprj_io[21]
|
||||
flabel metal5 s 698512 281640 711002 294160 0 FreeSans 25000 0 0 0 mprj_io[4]
|
||||
port 38 nsew signal bidirectional
|
||||
rlabel metal5 s 181240 1018512 193760 1031002 6 mprj_io[21]
|
||||
flabel metal5 s 698512 326640 711002 339160 0 FreeSans 25000 0 0 0 mprj_io[5]
|
||||
port 39 nsew signal bidirectional
|
||||
rlabel metal5 s 129840 1018512 142360 1031002 6 mprj_io[22]
|
||||
flabel metal5 s 698512 371840 711002 384360 0 FreeSans 25000 0 0 0 mprj_io[6]
|
||||
port 40 nsew signal bidirectional
|
||||
rlabel metal5 s 129840 1018512 142360 1031002 6 mprj_io[22]
|
||||
flabel metal5 s 698512 549040 711002 561560 0 FreeSans 25000 0 0 0 mprj_io[7]
|
||||
port 41 nsew signal bidirectional
|
||||
rlabel metal5 s 78440 1018512 90960 1031002 6 mprj_io[23]
|
||||
flabel metal5 s 698512 594240 711002 606760 0 FreeSans 25000 0 0 0 mprj_io[8]
|
||||
port 42 nsew signal bidirectional
|
||||
rlabel metal5 s 78440 1018512 90960 1031002 6 mprj_io[23]
|
||||
flabel metal5 s 698512 639240 711002 651760 0 FreeSans 25000 0 0 0 mprj_io[9]
|
||||
port 43 nsew signal bidirectional
|
||||
rlabel metal5 s 6598 956440 19088 968960 6 mprj_io[24]
|
||||
port 44 nsew signal bidirectional
|
||||
rlabel metal5 s 6598 956440 19088 968960 6 mprj_io[24]
|
||||
flabel metal5 s 136713 7143 144150 18309 0 FreeSans 25000 0 0 0 resetb
|
||||
port 44 nsew signal input
|
||||
flabel metal5 s 6167 70054 19620 80934 0 FreeSans 25000 0 0 0 vccd
|
||||
port 45 nsew signal bidirectional
|
||||
rlabel metal5 s 6598 786640 19088 799160 6 mprj_io[25]
|
||||
flabel metal5 s 697980 909666 711433 920546 0 FreeSans 25000 0 0 0 vccd1
|
||||
port 46 nsew signal bidirectional
|
||||
rlabel metal5 s 6598 786640 19088 799160 6 mprj_io[25]
|
||||
flabel metal5 s 6167 914054 19620 924934 0 FreeSans 25000 0 0 0 vccd2
|
||||
port 47 nsew signal bidirectional
|
||||
rlabel metal5 s 6598 743440 19088 755960 6 mprj_io[26]
|
||||
flabel metal5 s 624222 6811 636390 18976 0 FreeSans 25000 0 0 0 vdda
|
||||
port 48 nsew signal bidirectional
|
||||
rlabel metal5 s 6598 743440 19088 755960 6 mprj_io[26]
|
||||
flabel metal5 s 698624 819822 710789 831990 0 FreeSans 25000 0 0 0 vdda1
|
||||
port 49 nsew signal bidirectional
|
||||
rlabel metal5 s 6598 700240 19088 712760 6 mprj_io[27]
|
||||
flabel metal5 s 698624 505222 710789 517390 0 FreeSans 25000 0 0 0 vdda1_2
|
||||
port 50 nsew signal bidirectional
|
||||
rlabel metal5 s 6598 700240 19088 712760 6 mprj_io[27]
|
||||
flabel metal5 s 6811 484410 18976 496578 0 FreeSans 25000 0 0 0 vdda2
|
||||
port 51 nsew signal bidirectional
|
||||
rlabel metal5 s 6598 657040 19088 669560 6 mprj_io[28]
|
||||
flabel metal5 s 6811 111610 18976 123778 0 FreeSans 25000 0 0 0 vddio
|
||||
port 52 nsew signal bidirectional
|
||||
rlabel metal5 s 6598 657040 19088 669560 6 mprj_io[28]
|
||||
flabel metal5 s 6811 871210 18976 883378 0 FreeSans 25000 0 0 0 vddio_2
|
||||
port 53 nsew signal bidirectional
|
||||
rlabel metal5 s 6598 613840 19088 626360 6 mprj_io[29]
|
||||
flabel metal5 s 80222 6811 92390 18976 0 FreeSans 25000 0 0 0 vssa
|
||||
port 54 nsew signal bidirectional
|
||||
rlabel metal5 s 6598 613840 19088 626360 6 mprj_io[29]
|
||||
flabel metal5 s 577010 1018624 589178 1030789 0 FreeSans 25000 0 0 0 vssa1
|
||||
port 55 nsew signal bidirectional
|
||||
rlabel metal5 s 698512 191440 711002 203960 6 mprj_io[2]
|
||||
flabel metal5 s 698624 417022 710789 429190 0 FreeSans 25000 0 0 0 vssa1_2
|
||||
port 56 nsew signal bidirectional
|
||||
rlabel metal5 s 698512 191440 711002 203960 6 mprj_io[2]
|
||||
flabel metal5 s 6811 829010 18976 841178 0 FreeSans 25000 0 0 0 vssa2
|
||||
port 57 nsew signal bidirectional
|
||||
rlabel metal5 s 6598 570640 19088 583160 6 mprj_io[30]
|
||||
flabel metal5 s 243266 6167 254146 19620 0 FreeSans 25000 0 0 0 vssd
|
||||
port 58 nsew signal bidirectional
|
||||
rlabel metal5 s 6598 570640 19088 583160 6 mprj_io[30]
|
||||
flabel metal5 s 697980 461866 711433 472746 0 FreeSans 25000 0 0 0 vssd1
|
||||
port 59 nsew signal bidirectional
|
||||
rlabel metal5 s 6598 527440 19088 539960 6 mprj_io[31]
|
||||
flabel metal5 s 6167 442854 19620 453734 0 FreeSans 25000 0 0 0 vssd2
|
||||
port 60 nsew signal bidirectional
|
||||
rlabel metal5 s 6598 527440 19088 539960 6 mprj_io[31]
|
||||
flabel metal5 s 570422 6811 582590 18976 0 FreeSans 25000 0 0 0 vssio
|
||||
port 61 nsew signal bidirectional
|
||||
rlabel metal5 s 6598 399840 19088 412360 6 mprj_io[32]
|
||||
flabel metal5 s 334810 1018624 346978 1030789 0 FreeSans 25000 0 0 0 vssio_2
|
||||
port 62 nsew signal bidirectional
|
||||
rlabel metal5 s 6598 399840 19088 412360 6 mprj_io[32]
|
||||
port 63 nsew signal bidirectional
|
||||
rlabel metal5 s 6598 356640 19088 369160 6 mprj_io[33]
|
||||
port 64 nsew signal bidirectional
|
||||
rlabel metal5 s 6598 356640 19088 369160 6 mprj_io[33]
|
||||
port 65 nsew signal bidirectional
|
||||
rlabel metal5 s 6598 313440 19088 325960 6 mprj_io[34]
|
||||
port 66 nsew signal bidirectional
|
||||
rlabel metal5 s 6598 313440 19088 325960 6 mprj_io[34]
|
||||
port 67 nsew signal bidirectional
|
||||
rlabel metal5 s 6598 270240 19088 282760 6 mprj_io[35]
|
||||
port 68 nsew signal bidirectional
|
||||
rlabel metal5 s 6598 270240 19088 282760 6 mprj_io[35]
|
||||
port 69 nsew signal bidirectional
|
||||
rlabel metal5 s 6598 227040 19088 239560 6 mprj_io[36]
|
||||
port 70 nsew signal bidirectional
|
||||
rlabel metal5 s 6598 227040 19088 239560 6 mprj_io[36]
|
||||
port 71 nsew signal bidirectional
|
||||
rlabel metal5 s 6598 183840 19088 196360 6 mprj_io[37]
|
||||
port 72 nsew signal bidirectional
|
||||
rlabel metal5 s 6598 183840 19088 196360 6 mprj_io[37]
|
||||
port 73 nsew signal bidirectional
|
||||
rlabel metal5 s 698512 236640 711002 249160 6 mprj_io[3]
|
||||
port 74 nsew signal bidirectional
|
||||
rlabel metal5 s 698512 236640 711002 249160 6 mprj_io[3]
|
||||
port 75 nsew signal bidirectional
|
||||
rlabel metal5 s 698512 281640 711002 294160 6 mprj_io[4]
|
||||
port 76 nsew signal bidirectional
|
||||
rlabel metal5 s 698512 281640 711002 294160 6 mprj_io[4]
|
||||
port 77 nsew signal bidirectional
|
||||
rlabel metal5 s 698512 326640 711002 339160 6 mprj_io[5]
|
||||
port 78 nsew signal bidirectional
|
||||
rlabel metal5 s 698512 326640 711002 339160 6 mprj_io[5]
|
||||
port 79 nsew signal bidirectional
|
||||
rlabel metal5 s 698512 371840 711002 384360 6 mprj_io[6]
|
||||
port 80 nsew signal bidirectional
|
||||
rlabel metal5 s 698512 371840 711002 384360 6 mprj_io[6]
|
||||
port 81 nsew signal bidirectional
|
||||
rlabel metal5 s 698512 549040 711002 561560 6 mprj_io[7]
|
||||
port 82 nsew signal bidirectional
|
||||
rlabel metal5 s 698512 549040 711002 561560 6 mprj_io[7]
|
||||
port 83 nsew signal bidirectional
|
||||
rlabel metal5 s 698512 594240 711002 606760 6 mprj_io[8]
|
||||
port 84 nsew signal bidirectional
|
||||
rlabel metal5 s 698512 594240 711002 606760 6 mprj_io[8]
|
||||
port 85 nsew signal bidirectional
|
||||
rlabel metal5 s 698512 639240 711002 651760 6 mprj_io[9]
|
||||
port 86 nsew signal bidirectional
|
||||
rlabel metal5 s 698512 639240 711002 651760 6 mprj_io[9]
|
||||
port 87 nsew signal bidirectional
|
||||
rlabel metal5 s 136713 7143 144150 18309 6 resetb
|
||||
port 88 nsew signal input
|
||||
rlabel metal5 s 136713 7143 144150 18309 6 resetb
|
||||
port 89 nsew signal input
|
||||
rlabel metal5 s 6167 70054 19620 80934 6 vccd
|
||||
port 90 nsew signal bidirectional
|
||||
rlabel metal5 s 6167 70054 19620 80934 6 vccd
|
||||
port 91 nsew signal bidirectional
|
||||
rlabel metal5 s 697980 909666 711433 920546 6 vccd1
|
||||
port 92 nsew signal bidirectional
|
||||
rlabel metal5 s 697980 909666 711433 920546 6 vccd1
|
||||
port 93 nsew signal bidirectional
|
||||
rlabel metal5 s 6167 914054 19620 924934 6 vccd2
|
||||
port 94 nsew signal bidirectional
|
||||
rlabel metal5 s 6167 914054 19620 924934 6 vccd2
|
||||
port 95 nsew signal bidirectional
|
||||
rlabel metal5 s 624222 6811 636390 18976 6 vdda
|
||||
port 96 nsew signal bidirectional
|
||||
rlabel metal5 s 624222 6811 636390 18976 6 vdda
|
||||
port 97 nsew signal bidirectional
|
||||
rlabel metal5 s 698624 819822 710789 831990 6 vdda1
|
||||
port 98 nsew signal bidirectional
|
||||
rlabel metal5 s 698624 819822 710789 831990 6 vdda1
|
||||
port 99 nsew signal bidirectional
|
||||
rlabel metal5 s 698624 505222 710789 517390 6 vdda1_2
|
||||
port 100 nsew signal bidirectional
|
||||
rlabel metal5 s 698624 505222 710789 517390 6 vdda1_2
|
||||
port 101 nsew signal bidirectional
|
||||
rlabel metal5 s 6811 484410 18976 496578 6 vdda2
|
||||
port 102 nsew signal bidirectional
|
||||
rlabel metal5 s 6811 484410 18976 496578 6 vdda2
|
||||
port 103 nsew signal bidirectional
|
||||
rlabel metal5 s 6811 111610 18976 123778 6 vddio
|
||||
port 104 nsew signal bidirectional
|
||||
rlabel metal5 s 6811 111610 18976 123778 6 vddio
|
||||
port 105 nsew signal bidirectional
|
||||
rlabel metal5 s 6811 871210 18976 883378 6 vddio_2
|
||||
port 106 nsew signal bidirectional
|
||||
rlabel metal5 s 6811 871210 18976 883378 6 vddio_2
|
||||
port 107 nsew signal bidirectional
|
||||
rlabel metal5 s 80222 6811 92390 18976 6 vssa
|
||||
port 108 nsew signal bidirectional
|
||||
rlabel metal5 s 80222 6811 92390 18976 6 vssa
|
||||
port 109 nsew signal bidirectional
|
||||
rlabel metal5 s 577010 1018624 589178 1030789 6 vssa1
|
||||
port 110 nsew signal bidirectional
|
||||
rlabel metal5 s 577010 1018624 589178 1030789 6 vssa1
|
||||
port 111 nsew signal bidirectional
|
||||
rlabel metal5 s 698624 417022 710789 429190 6 vssa1_2
|
||||
port 112 nsew signal bidirectional
|
||||
rlabel metal5 s 698624 417022 710789 429190 6 vssa1_2
|
||||
port 113 nsew signal bidirectional
|
||||
rlabel metal5 s 6811 829010 18976 841178 6 vssa2
|
||||
port 114 nsew signal bidirectional
|
||||
rlabel metal5 s 6811 829010 18976 841178 6 vssa2
|
||||
port 115 nsew signal bidirectional
|
||||
rlabel metal5 s 243266 6167 254146 19620 6 vssd
|
||||
port 116 nsew signal bidirectional
|
||||
rlabel metal5 s 243266 6167 254146 19620 6 vssd
|
||||
port 117 nsew signal bidirectional
|
||||
rlabel metal5 s 697980 461866 711433 472746 6 vssd1
|
||||
port 118 nsew signal bidirectional
|
||||
rlabel metal5 s 697980 461866 711433 472746 6 vssd1
|
||||
port 119 nsew signal bidirectional
|
||||
rlabel metal5 s 6167 442854 19620 453734 6 vssd2
|
||||
port 120 nsew signal bidirectional
|
||||
rlabel metal5 s 6167 442854 19620 453734 6 vssd2
|
||||
port 121 nsew signal bidirectional
|
||||
rlabel metal5 s 570422 6811 582590 18976 6 vssio
|
||||
port 122 nsew signal bidirectional
|
||||
rlabel metal5 s 570422 6811 582590 18976 6 vssio
|
||||
port 123 nsew signal bidirectional
|
||||
rlabel metal5 s 334810 1018624 346978 1030789 6 vssio_2
|
||||
port 124 nsew signal bidirectional
|
||||
rlabel metal5 s 334810 1018624 346978 1030789 6 vssio_2
|
||||
port 125 nsew signal bidirectional
|
||||
<< properties >>
|
||||
string FIXED_BBOX 0 0 717600 1037600
|
||||
<< end >>
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
4
manifest
4
manifest
|
|
@ -2,7 +2,7 @@
|
|||
87735eb5981740ca4d4b48e6b0321c8bb0023800 verilog/rtl/__uprj_netlists.v
|
||||
684085713662e37a26f9f981d35be7c6c7ff6e9a verilog/rtl/__user_analog_project_wrapper.v
|
||||
b5ad3558a91e508fad154b91565c7d664b247020 verilog/rtl/__user_project_wrapper.v
|
||||
c9a9c1b2a4cc5edc68d8f3812a8d437465439357 verilog/rtl/caravan.v
|
||||
ee12097291acd2855e8f357edf4671dbe60fc254 verilog/rtl/caravan.v
|
||||
a855d65d6fc59352e4f8a994e451418d113586fc verilog/rtl/caravan_netlists.v
|
||||
a3d12a2d2d3596800bec47d1266dce2399a2fcc6 verilog/rtl/caravan_openframe.v
|
||||
cb320bf7e981979c4e823270d823395ea609c77e verilog/rtl/caravel.v
|
||||
|
|
@ -28,6 +28,6 @@ ce49f9af199b5f16d2c39c417d58e5890bc7bab2 verilog/rtl/digital_pll_controller.v
|
|||
6f802b6ab7e6502160adfe41e313958b86d2c277 verilog/rtl/simple_por.v
|
||||
1b1705d41992b318c791a5703e0d43d0bcda8f12 verilog/rtl/spare_logic_block.v
|
||||
8f0bec01c914efe790a09ffe62bbfe0781069e35 verilog/rtl/xres_buf.v
|
||||
b00f5fb7e2f176dd4ca7ea1fcd3b8cf82b15fa76 scripts/set_user_id.py
|
||||
272e08b7330bbc55f97a8a60c03fdb5255557f04 scripts/set_user_id.py
|
||||
98168b1fb6f80b196f9a05e725ec6ad99bc57ac6 scripts/generate_fill.py
|
||||
3210e724c6dc99563af780ff1778fada5b432604 scripts/compositor.py
|
||||
|
|
|
|||
|
|
@ -18,8 +18,8 @@
|
|||
#
|
||||
# gen_gpio_defaults.py ---
|
||||
#
|
||||
# Manipulate the magic database and GDS to create and apply defaults
|
||||
# to the GPIO control blocks based on the user's specification in the
|
||||
# Manipulate the magic database to create and apply defaults to
|
||||
# the GPIO control blocks based on the user's specification in the
|
||||
# user_defines.v file.
|
||||
#
|
||||
# The GPIO defaults block contains 13 bits that set the state of the
|
||||
|
|
@ -121,7 +121,6 @@ if __name__ == '__main__':
|
|||
sys.exit(1)
|
||||
|
||||
magpath = user_project_path + '/mag'
|
||||
gdspath = user_project_path + '/gds'
|
||||
vpath = user_project_path + '/verilog'
|
||||
glpath = vpath + '/gl'
|
||||
|
||||
|
|
@ -132,10 +131,6 @@ if __name__ == '__main__':
|
|||
caravel_path = os.getcwd()
|
||||
|
||||
# Check paths
|
||||
if not os.path.isdir(gdspath):
|
||||
print('No directory ' + gdspath + ' found (path to GDS).')
|
||||
sys.exit(1)
|
||||
|
||||
if not os.path.isdir(vpath):
|
||||
print('No directory ' + vpath + ' found (path to verilog).')
|
||||
sys.exit(1)
|
||||
|
|
|
|||
|
|
@ -1,9 +1,12 @@
|
|||
#!/bin/bash
|
||||
#
|
||||
# Run top-level LVS on caravan. The extraction in magic does not include the SoC,
|
||||
# which is abstracted.
|
||||
#
|
||||
echo ${PDK_ROOT:=/usr/share/pdk} > /dev/null
|
||||
echo ${PDK:=sky130A} > /dev/null
|
||||
|
||||
if [ ! -f caravan.spice ]; then
|
||||
cd ../mag
|
||||
magic -dnull -noconsole -rcfile $PDK_ROOT/$PDK/libs.tech/magic/$PDK.magicrc << EOF
|
||||
drc off
|
||||
crashbackups stop
|
||||
|
|
@ -16,7 +19,11 @@ ext2spice lvs
|
|||
ext2spice
|
||||
EOF
|
||||
rm -f *.ext
|
||||
fi
|
||||
|
||||
export NETGEN_COLUMNS=60
|
||||
netgen -batch lvs "caravan.spice caravan" "../verilog/gl/caravan.v caravan" $PDK_ROOT/$PDK/libs.tech/netgen/${PDK}_setup.tcl comp.out
|
||||
netgen -batch lvs "caravan.spice caravan" "../verilog/gl/caravan.v caravan" \
|
||||
$PDK_ROOT/$PDK/libs.tech/netgen/${PDK}_setup.tcl caravan_comp.out
|
||||
|
||||
mv caravan.spice ../spi/lvs/caravan_lvs.spice
|
||||
mv caravan_comp.out ../signoff/
|
||||
exit 0
|
||||
|
|
@ -1,36 +1,41 @@
|
|||
#!/bin/bash
|
||||
#---------------------------------------------------------------------------
|
||||
# Run full LVS on caravan: This does not include verification of underlying
|
||||
# library components such as the I/O cells and standard cells, but does
|
||||
# include all sub-blocks of caravan.
|
||||
#
|
||||
# NOTE: The netlist caravan.spice is only regenerated if it does not exist.
|
||||
# To run a full extraction and LVS, remove any existing caravan.spice file
|
||||
# first.
|
||||
# Run full LVS on caravan: This does not include verification of underlying
|
||||
# library components such as the I/O cells, standard cells, and SRAM, but
|
||||
# does include all sub-blocks of caravan.
|
||||
#
|
||||
#---------------------------------------------------------------------------
|
||||
echo ${PDK_ROOT:=/usr/share/pdk} > /dev/null
|
||||
echo ${PDK:=sky130A} > /dev/null
|
||||
|
||||
# Extract full layout netlist
|
||||
if [ ! -f caravan.spice ]; then
|
||||
cd ../mag
|
||||
magic -dnull -noconsole -rcfile $PDK_ROOT/$PDK/libs.tech/magic/$PDK.magicrc << EOF
|
||||
drc off
|
||||
crashbackups stop
|
||||
load caravan
|
||||
# Replace the management core wrapper abstract view with the full view
|
||||
cellname filepath mgmt_core_wrapper ../../caravel_mgmt_soc_litex/mag
|
||||
flush mgmt_core_wrapper
|
||||
select top cell
|
||||
expand
|
||||
# Replace the SRAM full view with the abstract view.
|
||||
cellname filepath sky130_sram_2kbyte_1rw1r_32x512_8 $PDK_ROOT/$PDK/libs.ref/sky130_sram_macros/maglef
|
||||
flush sky130_sram_2kbyte_1rw1r_32x512_8
|
||||
extract do local
|
||||
extract all
|
||||
ext2spice lvs
|
||||
ext2spice
|
||||
EOF
|
||||
rm -f *.ext
|
||||
fi
|
||||
|
||||
# Generate black-box verilog entry for the conb cell. Otherwise, the verilog tends to
|
||||
# have only one of the pins listed which will result in an incorrect pin match.
|
||||
# Also set the USE_POWER_PINS definition, which is not set anywhere else.
|
||||
cat > conb.v << EOF
|
||||
\`define USE_POWER_PINS 1
|
||||
|
||||
/* Black-box entry for conb_1 module */
|
||||
module sky130_fd_sc_hd__conb_1 (HI, LO, VPWR, VGND, VPB, VNB);
|
||||
output HI;
|
||||
|
|
@ -40,6 +45,16 @@ module sky130_fd_sc_hd__conb_1 (HI, LO, VPWR, VGND, VPB, VNB);
|
|||
input VPB;
|
||||
input VNB;
|
||||
endmodule
|
||||
|
||||
/* Black-box entry for conb_1 module */
|
||||
module sky130_fd_sc_hvl__conb_1 (HI, LO, VPWR, VGND, VPB, VNB);
|
||||
output HI;
|
||||
output LO;
|
||||
input VPWR;
|
||||
input VGND;
|
||||
input VPB;
|
||||
input VNB;
|
||||
endmodule
|
||||
EOF
|
||||
|
||||
# Generate script for netgen
|
||||
|
|
@ -48,11 +63,15 @@ cat > netgen.tcl << EOF
|
|||
puts stdout "Reading netlist caravan.spice"
|
||||
set circuit1 [readnet spice caravan.spice]
|
||||
puts stdout "Reading gate-level netlist caravan.v"
|
||||
set circuit2 [readnet verilog ../verilog/gl/caravan.v]
|
||||
set circuit2 [readnet verilog ../verilog/rtl/defines.v]
|
||||
# Read additional subcircuits into the netlist of circuit2
|
||||
puts stdout "Reading black-box modules"
|
||||
readnet verilog conb.v \$circuit2
|
||||
puts stdout "Reading all gate-level verilog modules"
|
||||
#
|
||||
# NOTE: Cannot use __user_analog_project_wrapper module because it does
|
||||
# not correspond to the empty analog wrapper layout.
|
||||
# readnet verilog ../verilog/gl/__user_analog_project_wrapper.v \$circuit2
|
||||
readnet verilog ../verilog/gl/caravel_clocking.v \$circuit2
|
||||
readnet verilog ../verilog/gl/chip_io_alt.v \$circuit2
|
||||
readnet verilog ../verilog/gl/digital_pll.v \$circuit2
|
||||
|
|
@ -62,21 +81,28 @@ readnet verilog ../verilog/gl/gpio_defaults_block_1803.v \$circuit2
|
|||
readnet verilog ../verilog/gl/gpio_defaults_block_0403.v \$circuit2
|
||||
readnet verilog ../verilog/gl/gpio_logic_high.v \$circuit2
|
||||
readnet verilog ../verilog/gl/housekeeping.v \$circuit2
|
||||
readnet verilog ../verilog/gl/mgmt_protect.v \$circuit2
|
||||
readnet verilog ../verilog/gl/mgmt_protect_hv.v \$circuit2
|
||||
readnet verilog ../verilog/gl/mgmt_protect.v \$circuit2
|
||||
readnet verilog ../verilog/gl/mprj2_logic_high.v \$circuit2
|
||||
readnet verilog ../verilog/gl/mprj_logic_high.v \$circuit2
|
||||
readnet verilog ../verilog/gl/spare_logic_block.v \$circuit2
|
||||
readnet verilog ../verilog/gl/user_id_programming.v \$circuit2
|
||||
readnet verilog ../verilog/gl/xres_buf.v \$circuit2
|
||||
readnet verilog ../../caravel_mgmt_soc_litex/verilog/gl/DFFRAM.v \$circuit2
|
||||
readnet verilog ../../caravel_mgmt_soc_litex/verilog/gl/mgmt_core.v \$circuit2
|
||||
readnet verilog ../../caravel_mgmt_soc_litex/verilog/gl/mgmt_core_wrapper.v \$circuit2
|
||||
readnet verilog ../verilog/gl/caravan.v \$circuit2
|
||||
|
||||
# To do: Add simple_por from ../spi/lvs
|
||||
# Run LVS
|
||||
lvs "\$circuit1 caravan" "\$circuit2 caravan" $PDK_ROOT/$PDK/libs.tech/netgen/${PDK}_setup.tcl comp.out
|
||||
lvs "\$circuit1 caravan" "\$circuit2 caravan" $PDK_ROOT/$PDK/libs.tech/netgen/${PDK}_setup.tcl caravan_full_comp.out
|
||||
EOF
|
||||
|
||||
export NETGEN_COLUMNS=60
|
||||
export MAGIC_EXT_USE_GDS=1
|
||||
netgen -batch source netgen.tcl
|
||||
# rm conb.v
|
||||
# rm netgen.tcl
|
||||
rm conb.v
|
||||
rm netgen.tcl
|
||||
|
||||
mv caravan.spice ../spi/lvs/caraven_lvs_full.spice
|
||||
mv caravan_full_comp.out ../signoff/
|
||||
exit 0
|
||||
|
|
@ -1,9 +1,11 @@
|
|||
#!/bin/bash
|
||||
# Run top-level LVS on caravel. The extraction in magic does not include the SoC,
|
||||
# which is abstracted.
|
||||
#
|
||||
echo ${PDK_ROOT:=/usr/share/pdk} > /dev/null
|
||||
echo ${PDK:=sky130A} > /dev/null
|
||||
|
||||
if [ ! -f caravel.spice ]; then
|
||||
cd ../mag
|
||||
magic -dnull -noconsole -rcfile $PDK_ROOT/$PDK/libs.tech/magic/$PDK.magicrc << EOF
|
||||
drc off
|
||||
crashbackups stop
|
||||
|
|
@ -16,7 +18,11 @@ ext2spice lvs
|
|||
ext2spice
|
||||
EOF
|
||||
rm -f *.ext
|
||||
fi
|
||||
|
||||
export NETGEN_COLUMNS=60
|
||||
netgen -batch lvs "caravel.spice caravel" "../verilog/gl/caravel.v caravel" $PDK_ROOT/$PDK/libs.tech/netgen/${PDK}_setup.tcl comp.out
|
||||
netgen -batch lvs "caravel.spice caravel" "../verilog/gl/caravel.v caravel" \
|
||||
$PDK_ROOT/$PDK/libs.tech/netgen/${PDK}_setup.tcl caravel_comp.out
|
||||
|
||||
mv caravel.spice ../spi/lvs/caravel_lvs.spice
|
||||
mv caravel_comp.out ../signoff/
|
||||
exit 0
|
||||
|
|
@ -1,36 +1,42 @@
|
|||
#!/bin/bash
|
||||
#---------------------------------------------------------------------------
|
||||
# Run full LVS on caravel: This does not include verification of underlying
|
||||
# library components such as the I/O cells and standard cells, but does
|
||||
# include all sub-blocks of caravel.
|
||||
#
|
||||
# NOTE: The netlist caravel.spice is only regenerated if it does not exist.
|
||||
# To run a full extraction and LVS, remove any existing caravel.spice file
|
||||
# first.
|
||||
# Run full LVS on caravel: This does not include verification of underlying
|
||||
# library components such as the I/O cells, standard cells, and SRAM, but
|
||||
# does include all sub-blocks of caravel.
|
||||
#
|
||||
#---------------------------------------------------------------------------
|
||||
echo ${PDK_ROOT:=/usr/share/pdk} > /dev/null
|
||||
echo ${PDK:=sky130A} > /dev/null
|
||||
|
||||
# Extract full layout netlist
|
||||
cd ../mag
|
||||
if [ ! -f caravel.spice ]; then
|
||||
magic -dnull -noconsole -rcfile $PDK_ROOT/$PDK/libs.tech/magic/$PDK.magicrc << EOF
|
||||
drc off
|
||||
crashbackups stop
|
||||
load caravel
|
||||
# Replace the management core wrapper abstract view with the full view
|
||||
cellname filepath mgmt_core_wrapper ../../caravel_mgmt_soc_litex/mag
|
||||
flush mgmt_core_wrapper
|
||||
select top cell
|
||||
expand
|
||||
# Replace the SRAM full view with the abstract view.
|
||||
cellname filepath sky130_sram_2kbyte_1rw1r_32x512_8 $PDK_ROOT/$PDK/libs.ref/sky130_sram_macros/maglef
|
||||
flush sky130_sram_2kbyte_1rw1r_32x512_8
|
||||
extract do local
|
||||
extract all
|
||||
ext2spice lvs
|
||||
ext2spice
|
||||
EOF
|
||||
rm -f *.ext
|
||||
fi
|
||||
|
||||
# Generate black-box verilog entry for the conb cell. Otherwise, the verilog tends to
|
||||
# have only one of the pins listed which will result in an incorrect pin match.
|
||||
# Also set the USE_POWER_PINS definition, which is not set anywhere else.
|
||||
cat > conb.v << EOF
|
||||
\`define USE_POWER_PINS 1
|
||||
|
||||
/* Black-box entry for conb_1 module */
|
||||
module sky130_fd_sc_hd__conb_1 (HI, LO, VPWR, VGND, VPB, VNB);
|
||||
output HI;
|
||||
|
|
@ -40,6 +46,16 @@ module sky130_fd_sc_hd__conb_1 (HI, LO, VPWR, VGND, VPB, VNB);
|
|||
input VPB;
|
||||
input VNB;
|
||||
endmodule
|
||||
|
||||
/* Black-box entry for conb_1 module */
|
||||
module sky130_fd_sc_hvl__conb_1 (HI, LO, VPWR, VGND, VPB, VNB);
|
||||
output HI;
|
||||
output LO;
|
||||
input VPWR;
|
||||
input VGND;
|
||||
input VPB;
|
||||
input VNB;
|
||||
endmodule
|
||||
EOF
|
||||
|
||||
# Generate script for netgen
|
||||
|
|
@ -48,11 +64,14 @@ cat > netgen.tcl << EOF
|
|||
puts stdout "Reading netlist caravel.spice"
|
||||
set circuit1 [readnet spice caravel.spice]
|
||||
puts stdout "Reading gate-level netlist caravel.v"
|
||||
set circuit2 [readnet verilog ../verilog/gl/caravel.v]
|
||||
set circuit2 [readnet verilog ../verilog/rtl/defines.v]
|
||||
# Read additional subcircuits into the netlist of circuit2
|
||||
puts stdout "Reading black-box modules"
|
||||
readnet verilog conb.v \$circuit2
|
||||
puts stdout "Reading all gate-level verilog modules"
|
||||
# NOTE: Cannot use __user_project_wrapper.v because it is not
|
||||
# equivalent to the layout empty wrapper.
|
||||
# readnet verilog ../verilog/gl/__user_project_wrapper.v \$circuit2
|
||||
readnet verilog ../verilog/gl/caravel_clocking.v \$circuit2
|
||||
readnet verilog ../verilog/gl/chip_io.v \$circuit2
|
||||
readnet verilog ../verilog/gl/digital_pll.v \$circuit2
|
||||
|
|
@ -62,21 +81,28 @@ readnet verilog ../verilog/gl/gpio_defaults_block_1803.v \$circuit2
|
|||
readnet verilog ../verilog/gl/gpio_defaults_block_0403.v \$circuit2
|
||||
readnet verilog ../verilog/gl/gpio_logic_high.v \$circuit2
|
||||
readnet verilog ../verilog/gl/housekeeping.v \$circuit2
|
||||
readnet verilog ../verilog/gl/mgmt_protect.v \$circuit2
|
||||
readnet verilog ../verilog/gl/mgmt_protect_hv.v \$circuit2
|
||||
readnet verilog ../verilog/gl/mgmt_protect.v \$circuit2
|
||||
readnet verilog ../verilog/gl/mprj2_logic_high.v \$circuit2
|
||||
readnet verilog ../verilog/gl/mprj_logic_high.v \$circuit2
|
||||
readnet verilog ../verilog/gl/spare_logic_block.v \$circuit2
|
||||
readnet verilog ../verilog/gl/user_id_programming.v \$circuit2
|
||||
readnet verilog ../verilog/gl/xres_buf.v \$circuit2
|
||||
readnet verilog ../../caravel_mgmt_soc_litex/verilog/gl/DFFRAM.v \$circuit2
|
||||
readnet verilog ../../caravel_mgmt_soc_litex/verilog/gl/mgmt_core.v \$circuit2
|
||||
readnet verilog ../../caravel_mgmt_soc_litex/verilog/gl/mgmt_core_wrapper.v \$circuit2
|
||||
readnet verilog ../verilog/gl/caravel.v \$circuit2
|
||||
|
||||
# To do: Add simple_por from ../spi/lvs
|
||||
# Run LVS
|
||||
lvs "\$circuit1 caravel" "\$circuit2 caravel" $PDK_ROOT/$PDK/libs.tech/netgen/${PDK}_setup.tcl comp.out
|
||||
lvs "\$circuit1 caravel" "\$circuit2 caravel" $PDK_ROOT/$PDK/libs.tech/netgen/${PDK}_setup.tcl caravel_full_comp.out
|
||||
EOF
|
||||
|
||||
export NETGEN_COLUMNS=60
|
||||
export MAGIC_EXT_USE_GDS=1
|
||||
netgen -batch source netgen.tcl
|
||||
# rm conb.v
|
||||
# rm netgen.tcl
|
||||
rm conb.v
|
||||
rm netgen.tcl
|
||||
|
||||
mv caravel.spice ../spi/lvs/caravel_lvs_full.spice
|
||||
mv caravel_full_comp.out ../signoff/
|
||||
exit 0
|
||||
|
|
@ -4265,6 +4265,7 @@ module caravan(vddio, vddio_2, vssio, vssio_2, vdda, vssa, vccd, vssd, vdda1, vd
|
|||
.mprj_dat_o({ \mprj_dat_o_core[31] , \mprj_dat_o_core[30] , \mprj_dat_o_core[29] , \mprj_dat_o_core[28] , \mprj_dat_o_core[27] , \mprj_dat_o_core[26] , \mprj_dat_o_core[25] , \mprj_dat_o_core[24] , \mprj_dat_o_core[23] , \mprj_dat_o_core[22] , \mprj_dat_o_core[21] , \mprj_dat_o_core[20] , \mprj_dat_o_core[19] , \mprj_dat_o_core[18] , \mprj_dat_o_core[17] , \mprj_dat_o_core[16] , \mprj_dat_o_core[15] , \mprj_dat_o_core[14] , \mprj_dat_o_core[13] , \mprj_dat_o_core[12] , \mprj_dat_o_core[11] , \mprj_dat_o_core[10] , \mprj_dat_o_core[9] , \mprj_dat_o_core[8] , \mprj_dat_o_core[7] , \mprj_dat_o_core[6] , \mprj_dat_o_core[5] , \mprj_dat_o_core[4] , \mprj_dat_o_core[3] , \mprj_dat_o_core[2] , \mprj_dat_o_core[1] , \mprj_dat_o_core[0] }),
|
||||
.mprj_sel_o({ \mprj_sel_o_core[3] , \mprj_sel_o_core[2] , \mprj_sel_o_core[1] , \mprj_sel_o_core[0] }),
|
||||
.mprj_stb_o(mprj_stb_o_core),
|
||||
.mprj_wb_iena(mprj_iena_wb),
|
||||
.mprj_we_o(mprj_we_o_core),
|
||||
.qspi_enabled(qspi_enabled),
|
||||
.ser_rx(ser_rx),
|
||||
|
|
@ -4280,7 +4281,8 @@ module caravan(vddio, vddio_2, vssio, vssio_2, vdda, vssa, vccd, vssd, vdda1, vd
|
|||
.sram_ro_csb(hkspi_sram_csb),
|
||||
.sram_ro_data({ \hkspi_sram_data[31] , \hkspi_sram_data[30] , \hkspi_sram_data[29] , \hkspi_sram_data[28] , \hkspi_sram_data[27] , \hkspi_sram_data[26] , \hkspi_sram_data[25] , \hkspi_sram_data[24] , \hkspi_sram_data[23] , \hkspi_sram_data[22] , \hkspi_sram_data[21] , \hkspi_sram_data[20] , \hkspi_sram_data[19] , \hkspi_sram_data[18] , \hkspi_sram_data[17] , \hkspi_sram_data[16] , \hkspi_sram_data[15] , \hkspi_sram_data[14] , \hkspi_sram_data[13] , \hkspi_sram_data[12] , \hkspi_sram_data[11] , \hkspi_sram_data[10] , \hkspi_sram_data[9] , \hkspi_sram_data[8] , \hkspi_sram_data[7] , \hkspi_sram_data[6] , \hkspi_sram_data[5] , \hkspi_sram_data[4] , \hkspi_sram_data[3] , \hkspi_sram_data[2] , \hkspi_sram_data[1] , \hkspi_sram_data[0] }),
|
||||
.trap(trap),
|
||||
.uart_enabled(uart_enabled)
|
||||
.uart_enabled(uart_enabled),
|
||||
.user_irq_ena({ \user_irq_ena[2] , \user_irq_ena[1] , \user_irq_ena[0] })
|
||||
);
|
||||
spare_logic_block \spare_logic[0] (
|
||||
.spare_xfq({ \spare_xfq_nc[1] , \spare_xfq_nc[0] }),
|
||||
|
|
|
|||
|
|
@ -448,6 +448,7 @@ module caravan (
|
|||
.flash_io3_do(flash_io3_do_core),
|
||||
|
||||
// Exported Wishbone Bus
|
||||
.mrpj_wb_iena(mprj_iena_wb),
|
||||
.mprj_cyc_o(mprj_cyc_o_core),
|
||||
.mprj_stb_o(mprj_stb_o_core),
|
||||
.mprj_we_o(mprj_we_o_core),
|
||||
|
|
@ -464,6 +465,7 @@ module caravan (
|
|||
|
||||
// IRQ
|
||||
.irq({irq_spi, user_irq}),
|
||||
.user_irq_ena(user_irq_ena),
|
||||
|
||||
// Module status (these may or may not be implemented)
|
||||
.qspi_enabled(qspi_enabled),
|
||||
|
|
|
|||
Loading…
Reference in New Issue