Add new test user_pass_thru_rd

verilog/dv/cocotb/caravel_tests.py

@@ -25,6 +25,7 @@ import os
 from tests.bitbang.bitbang_tests import *
 from tests.bitbang.bitbang_tests_cpu import *
 from tests.housekeeping.housekeeping_regs.housekeeping_regs_tests import *
+from tests.housekeeping.housekeeping_spi.user_pass_thru import *
 from tests.temp_partial_test.partial import *
 from tests.hello_world.helloWorld import *
 from tests.cpu.cpu_stress import *

verilog/dv/cocotb/tests.json

@@ -194,7 +194,7 @@
             "GL":["r_gl","nightly","weekly","tape_out"],
             "GL_SDF":["r_sdf","weekly","tape_out"],
             "description":"To be deleted"}
-
+            
         ,"user_pass_thru_rd" :{"level":0, 
             "SW":true,
             "RTL":["r_rtl","setup","nightly","weekly","tape_out"],

verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/housekeeping_regs_tests.py

@@ -9,8 +9,8 @@ from cocotb.result import TestSuccess
 from tests.common_functions.test_functions import *
 from tests.bitbang.bitbang_functions import *
 from caravel import GPIO_MODE
+from tests.housekeeping.housekeeping_spi.spi_access_functions import *
 import json
-
 reg = Regs()
 
 
@@ -193,23 +193,6 @@ async def hk_regs_rst_spi(dut):
 
 
 
-async def write_reg_spi(caravelEnv,address,data):
-    await caravelEnv.enable_csb()
-    await caravelEnv.hk_write_byte(0x80) # Write stream command
-    await caravelEnv.hk_write_byte(address) # Address (register 19 = GPIO bit-bang control)
-    await caravelEnv.hk_write_byte(data) # Data = 0x01 (enable bit-bang mode)
-    await caravelEnv.disable_csb()
-
-
-async def read_reg_spi(caravelEnv,address):
-    await caravelEnv.enable_csb()
-    await caravelEnv.hk_write_byte(0x40) # read stream command
-    await caravelEnv.hk_write_byte(address) # Address 
-    data = await caravelEnv.hk_read_byte() # Data = 0x01 (enable bit-bang mode)
-    await caravelEnv.disable_csb()
-    return data
-
-
 def generate_key_from_num(num):
     hex_string = hex(num)
     hex_list = [i for i in hex_string]

verilog/dv/cocotb/tests/housekeeping/housekeeping_spi/spi_access_functions.py

@@ -0,0 +1,38 @@
+
+
+async def write_reg_spi(caravelEnv,address,data):
+    await caravelEnv.enable_csb()
+    await caravelEnv.hk_write_byte(0x80) # Write stream command
+    await caravelEnv.hk_write_byte(address) # Address (register 19 = GPIO bit-bang control)
+    await caravelEnv.hk_write_byte(data) # Data = 0x01 (enable bit-bang mode)
+    await caravelEnv.disable_csb()
+
+
+async def read_reg_spi(caravelEnv,address):
+    await caravelEnv.enable_csb()
+    await caravelEnv.hk_write_byte(0x40) # read stream command
+    await caravelEnv.hk_write_byte(address) # Address 
+    data = await caravelEnv.hk_read_byte() # Data = 0x01 (enable bit-bang mode)
+    await caravelEnv.disable_csb()
+    return data
+
+
+async def reg_spi_user_pass_thru(caravelEnv,command,address):
+    await caravelEnv.enable_csb()
+    await caravelEnv.hk_write_byte(0xc2) # Apply user pass-thru command to housekeeping SPI
+    await caravelEnv.hk_write_byte(command) # read command
+    address = address.to_bytes(3,'big')
+    await caravelEnv.hk_write_byte(address[0]) # high byte 
+    await caravelEnv.hk_write_byte(address[1]) # middle byte 
+    await caravelEnv.hk_write_byte(address[2]) # low byte 
+    
+async def reg_spi_user_pass_thru_read(caravelEnv):
+    data = await caravelEnv.hk_read_byte() 
+    return data
+
+# use for configure in mgmt pass thru or user pass thru
+async def reg_spi_op(caravelEnv,command,address):
+    await caravelEnv.enable_csb()
+    await caravelEnv.hk_write_byte(command) # command
+    await caravelEnv.hk_write_byte(address) # Address 
+    await caravelEnv.disable_csb()

verilog/dv/cocotb/tests/housekeeping/housekeeping_spi/test_data

@@ -0,0 +1,3 @@
+@00000000
+6F 00 00 0B 93 01 00 00 13 02 63 57 b5 00 23 20
+13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00

verilog/dv/cocotb/tests/housekeeping/housekeeping_spi/user_pass_thru.py

@@ -0,0 +1,51 @@
+from email.headerregistry import Address
+import random
+import cocotb
+from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles,Timer
+import cocotb.log
+from cpu import RiskV
+from defsParser import Regs
+from cocotb.result import TestSuccess
+from tests.common_functions.test_functions import *
+from tests.spi_master.SPI_VIP import read_mem ,SPI_VIP
+from tests.housekeeping.housekeeping_spi.spi_access_functions import *
+
+
+bit_time_ns = 0
+reg = Regs()
+
+
+@cocotb.test()
+@repot_test
+async def user_pass_thru_rd(dut):
+    caravelEnv,clock = await test_configure(dut,timeout_cycles=14833)
+    cpu = RiskV(dut)
+    cpu.cpu_force_reset()
+    cpu.cpu_release_reset()
+    cocotb.log.info (f"[TEST] start spi_master_rd test")
+    file_name = f"{os.getenv('CARAVEL_VERILOG_PATH')}/dv/cocotb/tests/housekeeping/housekeeping_spi/test_data"
+    mem = read_mem(file_name)
+    await  cocotb.start(SPI_VIP(dut.bin8_monitor,dut.bin9_monitor,dut.bin10_monitor,(dut.bin11_en,dut.bin11),mem)) # fork for SPI 
+    await wait_reg1(cpu,caravelEnv,0XAA) 
+    cocotb.log.info (f"[TEST] Configuration finished")
+    #The SPI flash may need to be reset
+    # 0xff and 0xAB commands are suppose to have functionality in the future but for now they would do nothing
+    await write_reg_spi(caravelEnv,0xc2,0xff) # 0xc2 is for appling user pass-thru command to housekeeping SPI   
+    await write_reg_spi(caravelEnv,0xc2,0xab) # 0xc2 is for appling user pass-thru command to housekeeping SPI   
+
+    # start reading from memory
+    address = 0x0
+    await reg_spi_user_pass_thru(caravelEnv,command = 0x3,address=address) # read command
+    for i in range(8):
+        val = await reg_spi_user_pass_thru_read(caravelEnv)
+        if val  != mem[address]:
+            cocotb.log.error(f"[TEST] reading incorrect value from address {hex(address)} expected = {hex(mem[address])} returened = {val}")
+        else:
+            cocotb.log.info(f"[TEST] reading correct value {hex(val)} from address {hex(address)} ")
+        address +=1
+   
+    await caravelEnv.disable_csb()
+
+    # Wait for processor to restart 
+    await wait_reg1(cpu,caravelEnv,0xBB) 
+    cocotb.log.info(f"[TEST] processor has restarted successfully")

verilog/dv/cocotb/tests/housekeeping/housekeeping_spi/user_pass_thru_rd.c

@@ -0,0 +1,62 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <defs.h>
+#include <stub.c>
+
+
+
+void main()
+{
+    // This program is just to keep the processor busy while the
+    // housekeeping SPI is being accessed. to show that the
+    // processor is halted while the SPI is accessing the
+    // flash SPI in pass-through mode.
+
+    reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
+    reg_debug_1  = 0x0;
+    reg_debug_2  = 0x0;
+
+    // Management needs to apply output on these pads to access the user area SPI flash
+    reg_mprj_io_11 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; // SDI
+    reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT; // SDO
+    reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT; // clk
+    reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT; // csb
+
+
+    // Apply configuration
+    reg_mprj_xfer = 1;
+    while (reg_mprj_xfer == 1);
+
+    // Start test
+    reg_debug_1 = 0xAA;
+    reg_debug_1 = 0xBB;
+    reg_uart_enable = 1;
+
+    // Test in progress
+    reg_mprj_datal = 0xa5000000;
+
+    // Test message
+//    print("Test message\n");
+    print("ABC\n");
+
+    for (int i=0; i<1200; i++);
+
+    // End test
+    reg_debug_1 = 0xFF;
+}
+