tangxifan
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1150b903a5
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add quick start tutorial for architecture modeling
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2020-06-11 19:31:09 -06:00 |
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tangxifan
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339bf87c43
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add missing file
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2020-06-11 19:31:09 -06:00 |
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tangxifan
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aa77ee9af6
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add tutorial for full testbench run
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2020-06-11 19:31:09 -06:00 |
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tangxifan
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35536ee594
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renaming design flows in documentation
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2020-06-11 19:31:09 -06:00 |
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tangxifan
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011ce5cdf6
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minor fix on the documentation
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2020-06-11 19:31:08 -06:00 |
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tangxifan
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f079c61bd3
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re organize tutorials
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2020-06-11 19:31:08 -06:00 |
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tangxifan
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dcce782a46
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update documentation about Verilog testbenches
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2020-06-11 19:31:08 -06:00 |
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tangxifan
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c5a3e44e61
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Update Verilog fabric netlist documentation
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2020-06-11 19:31:08 -06:00 |
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tangxifan
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cae7fe0fed
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minor fix on the manual subtree
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2020-06-11 19:31:08 -06:00 |
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tangxifan
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c27d77a418
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clean-up documentation for a shallow hierarchy
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2020-06-11 19:31:08 -06:00 |
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tangxifan
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f6895fcc14
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update documentation for new options of Verilog testbench writer
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2020-06-11 19:31:07 -06:00 |
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tangxifan
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c2a81c76e1
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update doc for new options
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2020-06-11 19:31:07 -06:00 |
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tangxifan
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f4dd882f0f
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documentation updated for new command
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2020-06-11 19:31:06 -06:00 |
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tangxifan
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df9cf32b49
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update documenation for configuration chain writer
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2020-06-11 19:31:06 -06:00 |
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tangxifan
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a41c8dbcb3
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change to use default sphinx build version
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2020-06-11 19:31:06 -06:00 |
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Xifan Tang
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24934aff86
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update documentation on the depth option for fabric hierarchy writer
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2020-06-11 19:31:04 -06:00 |
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Xifan Tang
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752470c2da
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update documentation on write hierarchy command and options
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2020-06-11 19:31:04 -06:00 |
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Xifan Tang
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ac378febef
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update doc about time units in SDC generator
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2020-06-11 19:31:03 -06:00 |
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Xifan Tang
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d18e924a89
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Update documentation on new fpga_sdc option
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2020-06-11 19:31:03 -06:00 |
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Xifan Tang
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ecdbdcb592
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update documentation on new SDC options
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2020-06-11 19:31:02 -06:00 |
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Xifan Tang
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52adebacfb
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update doc for file options in openfpga bitstream
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2020-04-21 14:40:53 -06:00 |
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Xifan Tang
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b4542ea34b
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minor fix on doc about the global and general purpose port
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2020-04-09 17:10:04 -06:00 |
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Xifan Tang
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d99776b260
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update documentation on the global I/O ports
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2020-04-08 18:18:53 -06:00 |
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Xifan Tang
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b9ade3fcb6
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documentation update to introduce new features in script mode of OpenFPGA shell
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2020-04-08 14:13:28 -06:00 |
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Xifan Tang
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55e68896d6
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doc update for the support on std cell MUX2 and examples
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2020-04-07 12:01:13 -06:00 |
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Xifan Tang
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7a4137fdcf
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doc update for packable XML syntax in VPR
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2020-04-06 18:37:05 -06:00 |
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Xifan Tang
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1a3a748dd2
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update documentation with the support on spypads and global I/O ports
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2020-04-05 20:12:28 -06:00 |
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Xifan Tang
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6ce0fe4ef2
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doc update for FPGA-bitstream to better motivate the different types of bitstream
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2020-04-01 12:57:28 -06:00 |
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Xifan Tang
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fd8248d9dd
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update documentation: the addon syntax on VPR and configuration protocols
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2020-04-01 12:35:52 -06:00 |
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tangxifan
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78964ce71c
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update documentation on the through channel
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2020-03-27 11:34:39 -06:00 |
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Xifan Tang
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b4221e94bb
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add documentation on the tileable routing and thru channel support
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2020-03-25 16:52:42 -06:00 |
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Xifan Tang
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cb6afea07c
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update documentation on a new option in FPGA-SDC to constrain zero-delay paths
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2020-03-25 16:00:25 -06:00 |
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Xifan Tang
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3a74fb7a04
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update documentation for the new options
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2020-03-25 15:23:21 -06:00 |
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Xifan Tang
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7e3a8e5794
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typo fixed in fpga-bitstream documentation
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2020-03-22 16:27:12 -06:00 |
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Xifan Tang
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75dfe6a045
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update documentation for write_gsb_to_xml functionality
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2020-03-22 16:21:35 -06:00 |
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tangxifan
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1d766d2a70
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minor format fix on documentation
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2020-03-11 10:22:30 -06:00 |
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Xifan Tang
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b941ac8a4a
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remove deprecated options
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2020-03-10 20:58:00 -06:00 |
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Xifan Tang
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8037d1ad93
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Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2020-03-10 20:55:02 -06:00 |
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Xifan Tang
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9f743f7f4e
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add openfpga shell documentation
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2020-03-10 20:54:42 -06:00 |
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tangxifan
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0da6f00af5
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start reworking the openfpga tool documentation
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2020-03-10 17:29:35 -06:00 |
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tangxifan
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089cc5e86e
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update documentation on circuit model annotation on VPR architecture
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2020-03-10 16:51:50 -06:00 |
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tangxifan
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7195564455
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reworked circuit model examples in documentation. Now we are consistent to latest syntax
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2020-03-10 16:17:20 -06:00 |
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tangxifan
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54dfdc0cc1
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update general documentation on circuit library
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2020-03-10 12:18:12 -06:00 |
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tangxifan
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2a3c5b98a5
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minor format fix in documentation
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2020-03-09 21:25:13 -06:00 |
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Xifan Tang
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d14fa16905
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finish documentation update on technology library
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2020-03-09 21:17:25 -06:00 |
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Xifan Tang
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cb7e4a1dfa
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finish documentation the simulation settings in VPR8 integration
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2020-03-09 20:03:37 -06:00 |
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tangxifan
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751735bf41
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update documentation in simulation setting syntax
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2020-03-09 17:40:33 -06:00 |
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tangxifan
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3c7fd30e12
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merged tutorial to online documentation and reworked compilation guidelines
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2020-03-09 13:58:24 -06:00 |
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tangxifan
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af6319a6b0
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reworked motivation in documentation
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2020-03-09 11:27:25 -06:00 |
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tangxifan
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73da4a1d6e
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rework motivation for FPGA-Verilog and FPGA-Bitstream in documentation
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2020-03-09 10:32:03 -06:00 |
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tangxifan
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f821e60405
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clean up deadlinks in doc
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2020-03-09 10:15:16 -06:00 |
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tangxifan
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d61ae5561b
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start cleanup the documentation for openfpga shell
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2020-03-09 09:44:19 -06:00 |
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tangxifan
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f67981afa8
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update ducoumentation to explain lib_name XML syntax
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2020-01-08 14:22:17 -07:00 |
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tangxifan
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13f964ea72
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add bitstream file format introduction
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2019-12-04 13:41:31 -07:00 |
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tangxifan
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40bddd4ed7
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add FPL'19 paper to documentation reference
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2019-12-04 12:05:30 -07:00 |
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tangxifan
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323c4fdc9a
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clean up documentation build warnings and add guidelines for port naming
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2019-12-04 11:59:10 -07:00 |
AurelienUoU
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36f7624b95
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Point to point truth table typo fix
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2019-10-01 13:07:27 -06:00 |
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AurelienUoU
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e2867019e1
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Typo fixing
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2019-09-30 10:38:02 -06:00 |
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AurelienUoU
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74f7a3cfb2
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Doc fixing
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2019-09-30 10:29:42 -06:00 |
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AurelienUoU
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5ac79f4805
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Point to point documentation
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2019-09-30 10:00:46 -06:00 |
Ganesh Gore
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48ec1eefcd
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Added fpga_task cmd options in doc [ci skip]
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2019-09-02 02:45:05 -06:00 |
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Ganesh Gore
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241b001282
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Added openfpga_task doc
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2019-09-01 22:15:53 -06:00 |
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Ganesh Gore
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32d47d6b8b
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Update document + Travis cache check
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2019-08-31 16:13:47 -06:00 |
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Ganesh Gore
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06c0dbb328
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Added docuementation for fpga_flow
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2019-08-31 15:19:34 -06:00 |
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Ganesh Gore
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937ebd1b85
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Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
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2019-08-25 00:53:18 -06:00 |
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Ganesh Gore
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c4180fad6d
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Added .gitignore to build docs locally
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2019-08-25 00:49:04 -06:00 |
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tangxifan
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42b528be57
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doc updates
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2019-08-21 15:11:25 -06:00 |
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tangxifan
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9c43b1b753
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complete refacotriing the inv and buf part in submodules
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2019-08-21 14:54:05 -06:00 |
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tangxifan
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b207050b03
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minor fix in documentation
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2019-08-06 14:17:57 -06:00 |
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tangxifan
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fc93a4941a
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update documentation
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2019-08-06 14:17:56 -06:00 |
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tangxifan
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7603850d72
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complete documentation for new features
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2019-08-06 14:17:56 -06:00 |
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tangxifan
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8a046394f8
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add documentation for multi-mode configurable block support
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2019-07-30 16:47:41 -06:00 |
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Xifan Tang
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afd78604c9
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Merge branch 'dev' into documentation: resolved conflicts and add logo files
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2019-07-17 17:50:11 -04:00 |
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Xifan Tang
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e7b40f06b0
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Add documentation for fracturable LUTs
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2019-07-17 15:21:07 -04:00 |
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AurelienUoU
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1cf4e78502
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Update documentation and help
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2019-07-15 21:16:15 -06:00 |
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AurelienUoU
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df53f6da2c
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Updates FPGA-Verilog command lines
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2019-07-05 13:41:34 -06:00 |
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AurelienUoU
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9e99048815
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Update documentation
Merge branch 'heterogeneous' of https://github.com/LNIS-Projects/OpenFPGA into heterogeneous
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2019-07-05 11:56:02 -06:00 |
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AurelienUoU
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27dbc527a0
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Update Readme
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2019-07-05 11:06:55 -06:00 |
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AurelienUoU
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f56adc6815
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Update documentation
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2019-07-05 10:20:16 -06:00 |
BaudouinChauviere
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cb34ac0243
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Update sc_flow.rst
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2019-04-01 16:30:31 -06:00 |
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BaudouinChauviere
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361bbc13e3
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Update func_verify.rst
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2019-04-01 16:29:42 -06:00 |
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BaudouinChauviere
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a176bf3a19
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Update file_organization.rst
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2019-04-01 16:28:48 -06:00 |
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BaudouinChauviere
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01371ce54d
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Update customize_subckt.rst
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2019-04-01 16:27:06 -06:00 |
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BaudouinChauviere
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1ea7ec3265
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Update spice_simulation.rst
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2019-04-01 16:26:02 -06:00 |
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BaudouinChauviere
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cfdc072164
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Update file_organization.rst
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2019-04-01 16:25:09 -06:00 |
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BaudouinChauviere
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fcc3bf0967
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Update command_line_usage.rst
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2019-04-01 16:23:24 -06:00 |
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BaudouinChauviere
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f4b72bd4e1
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Update link_circuit_modules.rst
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2019-04-01 16:21:59 -06:00 |
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BaudouinChauviere
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ce300c196c
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Update circuit_modules.rst
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2019-04-01 16:13:23 -06:00 |
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BaudouinChauviere
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6e065ef3b3
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Update tech_lib.rst
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2019-04-01 16:09:31 -06:00 |
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BaudouinChauviere
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aed779ca3d
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Update spice_sim_setting.rst
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2019-04-01 16:08:00 -06:00 |
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BaudouinChauviere
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4900caaed9
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Update generality.rst
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2019-04-01 16:04:17 -06:00 |
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BaudouinChauviere
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33df25366c
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Update eda_flow.rst
Correction fix
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2019-04-01 16:02:47 -06:00 |
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BaudouinChauviere
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d6261f1f59
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Update motivation.rst
Typo and better explanations correction
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2019-04-01 15:57:04 -06:00 |
Baudouin Chauviere
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39f7b0b9a2
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Update of the doc for better fit with the current version
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2019-04-01 11:55:28 -06:00 |
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BaudouinChauviere
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5dbcfa6d70
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Repair broken link
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2019-01-03 18:26:30 +01:00 |
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BaudouinChauviere
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28010f6c91
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Testing another link method
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2019-01-03 18:24:06 +01:00 |
Laboratory for Nano Integrated Systems (LNIS)
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30f2ada557
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Repaired broken links
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2019-01-03 18:18:03 +01:00 |
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LNIS-Projects
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77dd7f3e04
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correction of the name of the figure
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2018-12-29 01:45:45 +01:00 |
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LNIS-Projects
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0f6ac32f43
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Further resizing
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2018-12-29 01:44:24 +01:00 |
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LNIS-Projects
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38a3b01520
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Resize the images
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2018-12-29 01:42:43 +01:00 |
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Baudouin Chauviere
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9ee50de26a
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Adding information on the layout
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2018-12-29 01:14:26 +01:00 |
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Baudouin Chauviere
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0a5391c14f
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Addition of some illustrations
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2018-12-26 18:16:16 +01:00 |
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LNIS-Projects
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de7d646fa0
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Update func_verify.rst
Functional Verification documentation
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2018-12-26 18:05:24 +01:00 |
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LNIS-Projects
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c0626e9a1c
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Adding the Verification Step from ModelSim
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2018-12-26 18:00:03 +01:00 |
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LNIS-Projects
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c506e16d33
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Update command_line_usage.rst
Small fix
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2018-12-22 14:46:15 +01:00 |
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LNIS-Projects
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ba303450e2
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Update file_organization.rst
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2018-12-22 14:45:00 +01:00 |
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LNIS-Projects
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5fa6c84087
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New fpga_verilog commands documented
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2018-12-22 14:39:51 +01:00 |
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LNIS-Projects
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55459f7906
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Update index.rst
Reorganization
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2018-12-10 13:46:38 -07:00 |
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LNIS-Projects
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56555fc8a0
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Update index.rst
Removed abc from the project because included in Yosys
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2018-12-10 13:46:02 -07:00 |
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BaudouinChauviere
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88af64c606
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Update eda_flow.rst
Distributions compilable added
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2018-12-05 16:29:07 -07:00 |
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BaudouinChauviere
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576feb600f
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Update eda_flow.rst
Completed with FPGA-Verilog/Bitstream and corrected few errors
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2018-12-05 16:24:03 -07:00 |
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BaudouinChauviere
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0f87fb9c3f
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Update file_organization.rst
Correction on the routing
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2018-12-03 14:21:40 -07:00 |
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BaudouinChauviere
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e541834bd0
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Update file_organization.rst
Made similar to the SPICE one
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2018-12-03 14:20:34 -07:00 |
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BaudouinChauviere
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cd301a5bb8
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Update file_organization.rst
Correction of the hierarchy
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2018-12-03 14:09:11 -07:00 |
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BaudouinChauviere
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9c97125b0d
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Update spice_simulation.rst
typo
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2018-12-03 13:42:45 -07:00 |
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BaudouinChauviere
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b8f702e16d
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Update file_organization.rst
Creation of the table for better understanding
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2018-12-03 13:40:42 -07:00 |
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BaudouinChauviere
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10cbd2efef
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Update index.rst
Commenting the multi mode out until more mature
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2018-12-03 11:50:13 -07:00 |
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BaudouinChauviere
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8e7def7f88
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Update link_circuit_modules.rst
Correction of typos
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2018-12-03 11:39:44 -07:00 |
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BaudouinChauviere
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f8e801b9d1
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Merge pull request #1 from LNIS-Projects/Documentation-Update
Update index.rst
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2018-12-03 11:27:05 -07:00 |
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BaudouinChauviere
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a4d29aeb1b
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Update circuit_model_examples.rst
Typo correction
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2018-12-03 11:26:04 -07:00 |
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BaudouinChauviere
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e39e0219e9
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Update circuit_modules.rst
Move the examples from this part to their own
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2018-12-03 10:59:20 -07:00 |
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BaudouinChauviere
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7a49ca8ce2
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Update index.rst
New section in the doc
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2018-12-03 10:58:50 -07:00 |
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BaudouinChauviere
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99769c1510
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Create circuit_model_examples.rst
Better architecture of the doc
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2018-12-03 10:58:11 -07:00 |
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BaudouinChauviere
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47a214520f
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Update index.rst
Skip lines
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2018-12-03 10:32:15 -07:00 |
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BaudouinChauviere
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6827549be2
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Update index.rst
Include the links for the external documentation
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2018-12-03 10:31:02 -07:00 |
Aurelien Alacchi
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4a950c6857
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Flatten_hierarchy_doc
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2018-10-18 16:28:12 -06:00 |
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Aurelien Alacchi
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aa5449c37d
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Verif_modif_doc_title_2
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2018-10-17 16:49:55 -06:00 |
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Aurelien Alacchi
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6327a4486b
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Revert "Verif_modif_doc_title"
This reverts commit 8f7f88ebea.
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2018-10-17 16:47:32 -06:00 |
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Aurelien Alacchi
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8f7f88ebea
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Verif_modif_doc_title
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2018-10-17 16:45:42 -06:00 |
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Aurelien Alacchi
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2cfbe2b997
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FPGA-Verilog_doc_update
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2018-10-17 16:38:03 -06:00 |
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Aurelien Alacchi
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e96c6e2f02
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Revert "Bug_correction_fpga-spice_commandLine"
This reverts commit 33e76d0255.
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2018-10-12 16:09:14 -06:00 |
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Aurelien Alacchi
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33e76d0255
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Bug_correction_fpga-spice_commandLine
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2018-10-12 16:05:53 -06:00 |
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Aurelien Alacchi
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26538cb2bc
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Correction_file_commandline_fpga-spice
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2018-10-12 16:03:23 -06:00 |
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Aurelien Alacchi
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e0c2fc2c8a
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Documentation_code&example_update
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2018-10-12 15:50:09 -06:00 |
Aurelien Alacchi
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07380ed1fa
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Minor_bug_fig_name_correction
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2018-10-09 15:33:30 -06:00 |
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Aurelien Alacchi
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a43574e593
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Update_doc_circuit_level_fig_fixed
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2018-10-09 15:29:15 -06:00 |
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Aurelien Alacchi
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d1c01cd68b
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Update_bug_fig_doc_CL
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2018-10-08 17:54:44 -06:00 |
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Aurelien Alacchi
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7c51129a33
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test42docFig
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2018-10-08 16:20:34 -06:00 |
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Aurelien Alacchi
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8723722e99
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test_correction_bug_fig_doc_CL
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2018-10-08 16:18:56 -06:00 |
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Aurelien Alacchi
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ebd4b282f5
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test_correction_figure
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2018-10-08 16:00:21 -06:00 |
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Aurelien Alacchi
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a318f8e20e
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Update_doc_circuit_level_bug_image
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2018-10-08 15:48:54 -06:00 |
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Aurelien Alacchi
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f79913f379
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Update_doc_circuit_level_bug_image
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2018-10-08 15:42:19 -06:00 |
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Aurelien Alacchi
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44bdca0429
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Revert "figure_correction_doc_circuit_level"
This reverts commit 046829bd13.
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2018-10-08 15:30:47 -06:00 |
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Aurelien Alacchi
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054a2bb186
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Revert "bug_correction_fig_circuit_level"
This reverts commit c6cd63462c.
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2018-10-08 15:30:36 -06:00 |
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Aurelien Alacchi
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c6cd63462c
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bug_correction_fig_circuit_level
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2018-10-08 15:30:03 -06:00 |
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Aurelien Alacchi
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046829bd13
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figure_correction_doc_circuit_level
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2018-10-08 15:27:30 -06:00 |
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Aurelien Alacchi
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cf1dddff5f
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Merge branch 'master' of https://github.com/LNIS-Projects/OpenFPGA
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2018-10-08 15:19:48 -06:00 |
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Aurelien Alacchi
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cf804b8fb2
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Define Circuit Level update
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2018-10-08 15:15:44 -06:00 |
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LNIS-Projects
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05f70548f3
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Add files via upload
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2018-10-08 15:02:16 -06:00 |
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Baudouin Chauviere
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16c0c4656e
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Adds titles and WiP tags for new parts. Tutorials included
Added title and WiP tags for comprehension and also to see what is missing and what is going to happen in the near future in the documentation
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2018-09-25 14:53:04 -06:00 |
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Baudouin Chauviere
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70d303dfb5
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Define Circuit doc improvement
Added some content, better spacing for understanding and made some changes in the options we show
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2018-09-25 11:53:53 -06:00 |
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tangxifan
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f47246e8b7
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Fixed doc ref problem
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2018-09-14 14:02:47 -06:00 |
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tangxifan
|
087ba475bb
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debugging bibtex
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2018-09-14 13:58:20 -06:00 |
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tangxifan
|
965835debe
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debugging doc ref
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2018-09-14 13:48:57 -06:00 |
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tangxifan
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4afbce10a3
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fixing bugs for doc references
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2018-09-14 13:44:40 -06:00 |
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tangxifan
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5d697da4e7
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refine doc hierarchy
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2018-09-14 13:27:05 -06:00 |
唐希凡
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0bfbc9b0aa
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update docs
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2018-09-14 13:11:51 -06:00 |
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Xifan Tang
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44e63ec98b
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Test new template
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2018-09-13 23:00:56 -06:00 |
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Xifan Tang
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fec0daa2a8
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Update a draft
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2018-09-13 22:58:54 -06:00 |
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唐希凡
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0f31d51c1a
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update doc html template
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2018-09-13 17:59:53 -06:00 |
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唐希凡
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655baa3cd9
|
Debugged Doc
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2018-09-13 17:39:57 -06:00 |
Xifan Tang
|
cea41801da
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updating documentation
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2018-09-13 16:25:24 -06:00 |
|
Xifan Tang
|
c94cc01c83
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debugging documentation
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2018-09-13 15:52:08 -06:00 |
|
Xifan Tang
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7261a53f3c
|
update docs theme
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2018-09-13 15:48:10 -06:00 |
|
Xifan Tang
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d6d6951496
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Adding documentation
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2018-09-13 15:38:41 -06:00 |