Eddie Hung
6a163b5ddd
xilinx_dsp: another typo; move xilinx specific test
2020-01-17 17:07:03 -08:00
Eddie Hung
db68e4c2a7
ice40_dsp: fix typo
2020-01-17 16:08:04 -08:00
Eddie Hung
e17f3f8c63
Consistency
2020-01-17 16:06:20 -08:00
Eddie Hung
ee500b6d8e
xilinx_dsp: add parameter defaults
2020-01-17 16:05:10 -08:00
Eddie Hung
4985318263
ice40_dsp: add default values for parameters
2020-01-17 15:37:52 -08:00
Eddie Hung
6692e5d558
ice40_dsp: tolerant of fanout-less outputs, as well as all-zero inputs
2020-01-17 15:28:02 -08:00
Miodrag Milanovic
3e14ff1667
fixed invalid char
2019-12-25 20:38:48 +01:00
Marcin Kościelnicki
e226a8f7f1
Minor nit fixes
2019-12-25 15:39:40 +01:00
Eddie Hung
1d0ac659ad
Fix OPMODE for PCIN->PCOUT cascades in xc6s, check B[01]REG too
2019-12-23 14:40:59 -08:00
Eddie Hung
75acaff6f5
Fix CEA/CEB check
2019-12-23 14:22:13 -08:00
Eddie Hung
edabe73377
Fix checking CE[AB] and for direct connections
2019-12-23 13:41:26 -08:00
Eddie Hung
71cac30309
Support unregistered cascades for A and B inputs
2019-12-23 12:38:18 -08:00
Eddie Hung
d00533eaa8
Add DSP48A* PCOUT -> PCIN cascade support
2019-12-23 11:42:46 -08:00
Marcin Kościelnicki
666c6128a9
xilinx_dsp: Initial DSP48A/DSP48A1 support.
2019-12-22 20:51:14 +01:00
Eddie Hung
36a88be609
ice40_wrapcarry -unwrap to preserve 'src' attribute
2019-12-09 14:28:54 -08:00
Eddie Hung
bbdf2452b3
-unwrap to create $lut not SB_LUT4 for opt_lut
2019-12-09 13:27:09 -08:00
Eddie Hung
500ed9b501
Sensitive to direct inst of $__ICE40_CARRY_WRAPPER; recreate SB_LUT4
2019-12-09 12:45:22 -08:00
Eddie Hung
e05372778a
ice40_wrapcarry to really preserve attributes via -unwrap option
2019-12-09 11:48:28 -08:00
Eddie Hung
946d5854c0
Drop keep=0 attributes on SB_CARRY
2019-12-06 17:27:47 -08:00
Eddie Hung
a7e0cca480
Merge SB_CARRY+SB_LUT4's attributes when creating $__ICE40_CARRY_WRAPPER
2019-12-05 07:01:18 -08:00
Eddie Hung
5897b918b3
ice40_wrapcarry to preserve SB_CARRY's attributes
2019-12-03 14:48:11 -08:00
Eddie Hung
2105ae176a
Check for either sign or zero extension for postAdd packing
2019-11-26 22:51:00 -08:00
Marcin Kościelnicki
15232a48af
Fix #1462 , #1480 .
2019-11-19 08:57:39 +01:00
Sean Cross
82f60ba938
Makefile: don't assume python is called `python3`
...
On some architectures, notably on Windows, the official name for the
Python binary from python.org is `python`. The build system assumes
that python is called `python3`, which breaks under this architecture.
There is already infrastructure in place to determine the name of the
Python binary when building PYOSYS. Since Python is now always required
to build Yosys, enable this check universally which sets the
`PYTHON_EXECUTABLE` variable.
Then, reuse this variable in other Makefiles as necessary, rather than
hardcoding `python3` everywhere.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-10-19 14:04:52 +08:00
Clifford Wolf
b8774ae849
Fix dffmux peepopt init handling
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-16 11:40:32 +02:00
Clifford Wolf
bb0851bfc5
Move GENERATE_PATTERN macro to separate utility header
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-16 11:40:01 +02:00
Clifford Wolf
af61d92441
Disable left-over log_debug in peepopt_dffmux.pmg
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-16 10:43:47 +02:00
Eddie Hung
cfc181cba9
Merge pull request #1432 from YosysHQ/eddie/fix1427
...
Refactor peepopt_dffmux and be sensitive to \init when trimming
2019-10-08 12:38:29 -07:00
Eddie Hung
472b5d33a6
Merge pull request #1438 from YosysHQ/eddie/xilinx_dsp_comments
...
Add notes and comments for xilinx_dsp
2019-10-08 10:53:30 -07:00
Clifford Wolf
4072a96663
Merge pull request #1439 from YosysHQ/eddie/fix_ice40_wrapcarry
...
Missing 'accept' at end of ice40_wrapcarry, spotted by @cliffordwolf
2019-10-06 12:11:20 +02:00
Eddie Hung
5c68da4150
Missing 'accept' at end of ice40_wrapcarry, spotted by @cliffordwolf
2019-10-05 09:27:12 -07:00
Clifford Wolf
10d0bad67e
Update README.md
2019-10-05 18:13:04 +02:00
Eddie Hung
f90a4b1e24
Missed this
2019-10-05 08:57:37 -07:00
Eddie Hung
991c2ca95b
Add comment on why we have to match for clock-enable/reset muxes
2019-10-05 08:56:37 -07:00
Eddie Hung
ebb059896a
Add note on pattern detector
2019-10-05 08:53:01 -07:00
Miodrag Milanović
7c074ef844
Merge pull request #1436 from YosysHQ/mmicko/msvc_fix
...
Fixes for MSVC build
2019-10-05 07:48:30 +02:00
Eddie Hung
792cd31052
Add comments for xilinx_dsp_cascade
2019-10-04 22:31:04 -07:00
Eddie Hung
12fd2ec4f0
Improve comments for xilinx_dsp_CREG
2019-10-04 22:31:04 -07:00
Eddie Hung
14e4aeece6
Fix comment
2019-10-04 22:31:04 -07:00
Eddie Hung
8027ebf05b
Restore optimisation for sigM.empty()
2019-10-04 22:31:04 -07:00
Eddie Hung
77d7a5c14a
Retry on fixing TODOs
2019-10-04 22:31:04 -07:00
Eddie Hung
52583ecff8
Revert "Fix TODOs"
...
This reverts commit 8674a6c68d563908014d16671567459499c6dc99.
2019-10-04 22:31:04 -07:00
Eddie Hung
6d68972619
More comments, cleanup
2019-10-04 22:31:04 -07:00
Eddie Hung
7de9c33931
Fix TODOs
2019-10-04 22:31:04 -07:00
Eddie Hung
983068103e
Consistency
2019-10-04 22:31:04 -07:00
Eddie Hung
cf82b38478
Add comments for xilinx_dsp
2019-10-04 22:31:04 -07:00
Eddie Hung
74ef8feeaf
Fix xilinx_dsp for unsigned extensions
2019-10-04 16:46:15 -07:00
Miodrag Milanovic
c0b14cfea7
Fixes for MSVC build
2019-10-04 16:29:46 +02:00
Eddie Hung
e9645c7fa7
Fix broken CI, check reset even for constants, trim rstmux
2019-10-02 21:26:26 -07:00
Eddie Hung
d99810ad8a
Refactor peepopt_dffmux and be sensitive to \init when trimming
2019-10-02 18:01:45 -07:00
Eddie Hung
aebbfffd71
Ooops AREG and BREG to default to -1
2019-09-27 11:57:53 -07:00
Eddie Hung
26657037b8
Update doc with max cascade chain of 20
2019-09-26 14:31:02 -07:00
Eddie Hung
5b9deef10d
Do not always zero out C (e.g. during cascade breaks)
2019-09-26 13:59:05 -07:00
Eddie Hung
95f0dd57df
Update doc
2019-09-26 13:44:41 -07:00
Eddie Hung
58f31096ab
Zero out ports
2019-09-26 13:40:38 -07:00
Eddie Hung
af59856ba1
xilinx_dsp_cascade to also cascade AREG and BREG
2019-09-26 13:29:18 -07:00
Eddie Hung
832216dab0
Try recursive pmgen for P cascade
2019-09-26 12:09:57 -07:00
Eddie Hung
bd8661e024
CREG to check for \keep
2019-09-26 10:32:01 -07:00
Eddie Hung
c0bb1d22e8
Remove newline
2019-09-26 10:31:55 -07:00
Eddie Hung
f1de93edf5
Do not die if DSP48E1.P has no users (would otherwise get 'clean'-ed)
2019-09-25 22:58:03 -07:00
Eddie Hung
cd8a640989
Reject if (* init *) present
2019-09-25 18:21:08 -07:00
Eddie Hung
aeb1539818
Rework xilinx_dsp postAdd for new wreduce call
2019-09-25 17:22:30 -07:00
Eddie Hung
5f8917c984
Fix memory issue since SigSpec& could be invalidated
2019-09-25 16:45:51 -07:00
Eddie Hung
486dd7c483
unextend only used in init
2019-09-25 14:05:59 -07:00
Eddie Hung
53ea5daa42
Call 'wreduce' after mul2dsp to avoid unextend()
2019-09-25 14:04:36 -07:00
Eddie Hung
e556d48d45
Set [AB]CASCREG to legal values
2019-09-23 16:00:11 -07:00
Eddie Hung
b824a56cde
Comment to explain separating CREG packing
2019-09-23 13:58:10 -07:00
Eddie Hung
15dfbc8125
Separate out CREG packing into new pattern, to avoid conflict with PREG
2019-09-23 13:27:10 -07:00
Eddie Hung
26a6c55665
Move log_debug("\n") later
2019-09-23 13:27:00 -07:00
Eddie Hung
d0dbbc2605
Move unextend initialisation later
2019-09-23 13:26:34 -07:00
Eddie Hung
a67af3d5e5
Use new port() overload once more
2019-09-23 13:00:44 -07:00
Eddie Hung
53817b8575
Use new port/param overload in pmg
2019-09-20 14:21:22 -07:00
Eddie Hung
d122083a11
Output pattern matcher items as log_debug()
2019-09-20 12:42:28 -07:00
Eddie Hung
95644b00cb
OPMODE is port not param
2019-09-20 12:37:29 -07:00
Eddie Hung
eb597431f0
Do not run xilinx_dsp_cascadeAB for now
2019-09-20 12:18:37 -07:00
Eddie Hung
0bca366bcd
WIP for xiinx_dsp_cascadeAB
2019-09-20 12:07:14 -07:00
Eddie Hung
b0ad2592be
Run until convergence
2019-09-20 12:04:16 -07:00
Eddie Hung
1b892ca1be
Cleanup ice40_dsp.pmg
2019-09-20 12:03:45 -07:00
Eddie Hung
d88903e610
Cleanup xilinx_dsp
2019-09-20 12:03:25 -07:00
Eddie Hung
1809f463fb
More exceptions
2019-09-20 12:03:10 -07:00
Eddie Hung
70c5444b25
Update doc
2019-09-20 10:07:54 -07:00
Eddie Hung
ed187ef1cf
Add a xilinx_dsp_cascade matcher for PCIN -> PCOUT
2019-09-20 10:00:09 -07:00
Eddie Hung
1844498c5f
Add an overload for port/param with default value
2019-09-20 09:59:42 -07:00
Eddie Hung
a0d3ecf8c6
Small cleanup
2019-09-20 08:41:28 -07:00
Eddie Hung
8cfcaf108e
Disable support for SB_MAC16 reset since it is async
2019-09-19 22:48:57 -07:00
Eddie Hung
a59f80834f
SB_MAC16 ffCD to not pack same as ffO
2019-09-19 22:39:47 -07:00
Eddie Hung
1b88211ec6
Clarify
2019-09-19 21:58:34 -07:00
Eddie Hung
34f9a8ceb2
Update doc for ice40_dsp
2019-09-19 21:57:11 -07:00
Eddie Hung
8a94ce7aa5
Add an index
2019-09-19 20:04:44 -07:00
Eddie Hung
c83a667555
Fix width of D
2019-09-19 18:08:46 -07:00
Eddie Hung
a8bc460805
Use ID() macro
2019-09-19 16:13:22 -07:00
Eddie Hung
37b0fc17e3
Re-enable sign extension for C input
2019-09-19 15:40:17 -07:00
Eddie Hung
64a72ed51e
Do not perform width-checks for DSP48E1 which is much more complicated
2019-09-19 14:50:11 -07:00
Eddie Hung
517ca49963
Remove TODO as check should not be necessary
2019-09-19 14:49:47 -07:00
Eddie Hung
307b2dc8e5
Revert index to select
2019-09-19 14:46:53 -07:00
Eddie Hung
ea5e5a212e
Cleanup xilinx_dsp too
2019-09-19 14:34:06 -07:00
Eddie Hung
1a0f7ed09c
Refactor ce{mux,pol} -> hold{mux,pol}
2019-09-19 14:27:25 -07:00
Eddie Hung
429c9852ce
Add HOLD/RST support for SB_MAC16
2019-09-19 14:02:55 -07:00
Eddie Hung
2766465a2b
Add support for SB_MAC16 CD and H registers
2019-09-19 12:14:33 -07:00
Eddie Hung
c8310a6e76
Refactor ice40_dsp.pmg
2019-09-19 12:00:48 -07:00