Commit Graph

231 Commits

Author SHA1 Message Date
M0stafaRady 55f6f56921 update verify_cocotb script to run iverilog inside a docker 2022-10-03 01:56:08 -07:00
M0stafaRady de2f4a3707 Add bitbang_spi_i test 2022-10-02 08:38:00 -07:00
M0stafaRady e661740208 Merge branch 'cocotb' of github.com:efabless/caravel into cocotb 2022-10-02 06:55:52 -07:00
M0stafaRady f3792b8421 merge with caravel_redesign 2022-10-02 06:55:41 -07:00
M0stafaRady 9812aedaa1
Update README.md 2022-10-02 15:50:18 +02:00
M0stafaRady f0494ef4b1 update make file to take user_project_wrapper file as input for iverilog 2022-10-02 06:48:29 -07:00
M0stafaRady 927c216a6b Merge branch 'cocotb' of github.com:efabless/caravel into cocotb 2022-10-02 06:38:32 -07:00
M0stafaRady 752d12928b fix iverlog command for the new structure 2022-10-02 06:38:22 -07:00
M0stafaRady d8a4b812e8 update script to make hex_files directory if not exists and to take argument -vcs if it will work in vcs mode 2022-10-02 06:37:12 -07:00
M0stafaRady 00a029fec3
Update README.md 2022-10-02 15:17:21 +02:00
M0stafaRady bf9b363f68
Update README.md 2022-10-02 15:01:15 +02:00
M0stafaRady 32607cc118 delete uart_rx hex 2022-10-02 05:40:44 -07:00
M0stafaRady b045977af0 merge with remote branch 2022-10-02 05:39:23 -07:00
M0stafaRady cb929cb329 Fix housekeeping spi tests 2022-10-02 05:37:27 -07:00
M0stafaRady bc9eb2eb31
Update README.md 2022-10-02 14:35:49 +02:00
M0stafaRady 928fc6a2a5
Update README.md 2022-10-02 14:27:42 +02:00
M0stafaRady a0da0fc906
add photo of cocotb structure 2022-10-02 14:10:17 +02:00
M0stafaRady ad053568e7
Create README.md
add READme in doc file
2022-10-02 14:09:49 +02:00
M0stafaRady bd712f64d4 rename cocotb.py to verify_cocotb.py 2022-10-02 04:29:48 -07:00
M0stafaRady b5fb97e5f4 rename run.py to cocotb.py 2022-10-02 04:22:44 -07:00
M0stafaRady 9e0be5473d remove hex files from directory 2022-10-02 04:20:32 -07:00
M0stafaRady 1c48f527b8 add bitbang_spi_o tests 2022-10-01 12:39:54 -07:00
M0stafaRady 199d5c0f5c fix bug assert csb before reset for the GL sim to work 2022-10-01 12:36:02 -07:00
M0stafaRady 53e868abdf add clock to the output od configuration function 2022-10-01 12:34:53 -07:00
M0stafaRady d12fac2ad1 update run script to delete vcs files before test run 2022-10-01 12:28:52 -07:00
M0stafaRady 555488c832 fix timeout values to the passing number of cycles required + 10% 2022-10-01 04:11:46 -07:00
M0stafaRady 9615629a42 fix bug bit time calculation 2022-10-01 02:53:24 -07:00
M0stafaRady 68c88b116a increase the clock period to 25ns 2022-10-01 02:52:30 -07:00
M0stafaRady 18b4f36525 add test uart_rx 2022-10-01 02:23:47 -07:00
M0stafaRady 407b0be306 Update script to return fatal error when hex generation fails 2022-10-01 01:48:55 -07:00
M0stafaRady f2ca45358b remove AN.DB folder from git hub 2022-09-30 03:52:34 -07:00
M0stafaRady 7546ce10c7 simple readme 2022-09-30 03:52:34 -07:00
M0stafaRady f8c8d831d0 Add RTL for 2 debug regs used to test and located inside user_project_wrapper 2022-09-30 03:52:34 -07:00
M0stafaRady fc8369443c fix bug move some housekeeping initialization wires and regs before they are used 2022-09-30 03:52:34 -07:00
M0stafaRady add4c5f6c8 Adding cocotb evironment with tests and scripts to run 2022-09-30 03:52:34 -07:00
R. Timothy Edwards f07958d4ec
Merge branch 'caravel_redesign' into fix_pwr_ctrl_reset_value 2022-09-29 14:10:41 -04:00
Marwan Abbas c9c7fc5533
Merge pull request #134 from efabless/fix_user_pass_thru
Fix user pass thru
2022-09-29 19:52:13 +02:00
Tim Edwards dd6088e013 Corrected the instance name of the topmost GPIO defaults block on
the left hand side of caravan from gpio_defaults_block_14 to
gpio_defaults_block_25.  Otherwise, the script that generates the
custom user configuration won't be able to change the defaults
for GPIO 25.
2022-09-28 15:36:24 -04:00
Tim Edwards aba145e0e2 Made modifications in support of changing the hard-coded default
configuration of GPIO 3 (CSB) from a standard input to a weak
pull-up input.
2022-09-27 20:58:57 -04:00
Tim Edwards 65553a5af3 Added reset values for pwr_ctrl_out in housekeeping (fixes caravel
github issue #106).
2022-09-27 11:30:02 -04:00
kareem 85f7f86c4e reharden!: gpio_control_block
- high level changes:
* add larger buffers on output ports
* add buffers on input ports
* adjust sdc file increasing output load and setting a high transition

- detailed changes:
* add interactive script for openlane where the order of events is a bit shuffled
	- to add obstruction before pdn
	- to manually insert buffers on some ports
	- to manually remove buffers inserted by synthesis on for example serial_clock_out
* change openlane config adding extra row and columns to increase the space and fit the
added buffers
* change config to enable buffering
* increase density for better placement?
* change the cell exclude list. some excluded cells didn't make sense
* ef decap cells break dynamic sims?
* add custom pdn script for to duplicate the old pdn

- misc changes:
* fix openlane makefile to properly detect interactive script

!important still need to run dynamic simulations
!important depends on some updates to openlane
2022-09-27 07:09:26 -07:00
Jeff DiCorpo 6137a23e01
Merge branch 'caravel_stanford' into fix_direct_power_connections 2022-09-21 10:36:19 -07:00
Tim Edwards 2606285b8c Flipped some lines where a wire was used before it was declared. 2022-09-20 18:23:32 -04:00
Tim Edwards 66fc0c6a06 Modified the GPIO control block to buffer the constant high/low outputs.
Corrected the pad constant connections to all be in the correct domain
(1.8V or 3.3V).  Created a new "constant_block" module that generates
a single constant 1 and 0 value in the 1.8V domain, and used 7 of these
in the chip_io (and chip_io_alt) modules to create the 1.8V domain
constant signals for the seven pads belonging to the management (clock,
reset, flash SPI, and management GPIO).
2022-09-20 17:49:08 -04:00
jeffdi e1e23857ff remove spare logic blocks in top level 2022-09-20 13:56:50 -07:00
Tim Edwards 37720ea216 Corrections to the padframe to make sure that all pad digital
inputs that are permanently tied low or high come from either
the local "TIE" pad connections (if they are in the 3.3V
domain) or from a constant one wire in the 1.8V domain that
is generated in the gpio_control_block module and exported
to the chip_io (or chip_io_alt) module.
2022-09-20 16:00:09 -04:00
kareem ac1928a45b harden: gpio_control_block with updated rtl
TODO: run full verification
2022-08-15 02:29:01 -07:00
Tim Edwards e6030f9fb3 Modified the GPIO control block verilog to remove the delay stages
from the data and replace them with a single flop clocked on the
negative edge of the serial clock.  This will completely avoid hold
violations by ensuring that the block's output data bit does not
change anywhere near the clock rising edge, so clocks do not have
to be tightly aligned among all of the GPIO blocks.
2022-07-24 16:17:56 -04:00
Tim Edwards 298ede362b Corrects an issue with the user pass-through flash programming
mode in which the data and clock are activated simultaneously,
so the first data bit after CSB goes low may or may not be
seen by the SPI flash.
2022-06-07 10:42:56 -04:00
Marwan Abbas 6cfedf89a2
fixed caravel netlist to use the 1803 defaults block (#94)
Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-05-03 10:36:11 -07:00
R. Timothy Edwards b2089fe9eb
Corrected the gpio_control_block so that the user_gpio_out signal (#89)
does not pass through an inverter, so that the input can remain
unconnected.  Rewired the existing implementation to use an
alternative gate that has an inverting input so that the
user_gpio_out signal can be left undriven when the GPIOs are in
the management enable state.  This is a simple logic refactoring
and does not change the logic function.  The manual rewiring has
been confirmed by LVS, but at least one GL simulation should be
run to confirm that the logic function remains the same as before.
2022-04-25 11:27:41 -07:00
R. Timothy Edwards ad8d168555
Corrects four signal routes which were missing from the caravan top level (#88)
* Corrects four signals which were missing from the caravan top level
(management output and output enable to GPIO 0 and 1---these errors
would have prevented the houskeeping SPI from working on caravel).
Corrected RTL verilog (source of the error), GL verilog, and layout.

* Apply automatic changes to Manifest and README.rst

Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
2022-04-25 08:50:55 -07:00
R. Timothy Edwards 99518acd15
Numerous bug fixes, ending in clean full LVS for both caravel and caravan. (#76)
* (1) Modified the .magicrc file to set a default for PDK if not set in the
environment.  (2) Fixed the user ID programming layout to not leave holes
behind when the script moves the vias around (similar to the handling of
the GPIO defaults block).  (3) Added substrate isolation to gpio_control_block
and fixed the path references to the standard cells.  (4) Fixed the four
missing routes on the Caravan top level.  (5) Reinstated the large rendered
labels for the pads on both caravel and caravan.  (6) Corrected the top
level gate-level netlist for caravan to add the missing pins to the
management core wrapper.  (7) Did the same for the caravan top level RTL.
(8) Created scripts to run full LVS including extracting the management
core wrapper and reading all gate-level verilog submodules.  (9) Moved all
of the LVS scripts to the scripts directory.

* Apply automatic changes to Manifest and README.rst

* Made the changes from pull request #73 as they did not get merged
successfully, and if merged now they will generate conflicts with
this pull request in scripts/set_user_id.py.  So it's easier to
just manually add them to this pull request.

* Apply automatic changes to Manifest and README.rst

Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
2022-04-19 19:05:27 -07:00
Kareem Farid 9ddb806293
gpio_control_block constrains fix (#69)
Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 11:50:54 -07:00
R. Timothy Edwards 71600440bc
Caravan top lvs (#67)
* - update caravan configuration
* change correct gpio_default blocks instance names
* implement powerrouting work around
* place spare logic blocks
* keep the history of runs and sym link last/final one

* - update caravan mag, def and gl views
- add fake power routing cell in the rtl as a placeholder for openlane
  to prevent routing on that cell
- fix some syntax errors in chip_io_alt
- match simple_por lef pins with mag by regenerating it

* Apply automatic changes to Manifest and README.rst

* add caravan power routing lef

* - update mag and def view of caravan
- add_macro_placement for fake cell

* Added back the power routing to Caravan, fixed DRC errors, ran LVS,
corrected placement of isolated substrate regions, and replaced the
signal routing for the analog lines.  Be aware that merging with
main may cause issues with the mgmt_protect.mag file and its
subcells mprj2_logic_high.mag and mprj_logic_high.mag.  It may be
worth cherry-picking the files to merge and exclude those layouts.

Co-authored-by: kareem <kareem.farid@efabless.com>
Co-authored-by: kareefardi <kareefardi@users.noreply.github.com>
Co-authored-by: Jeff DiCorpo <42048757+jeffdi@users.noreply.github.com>
2022-04-14 15:05:16 -07:00
Marwan Abbas 14142eb2a1
Fix syntax error in gpio_control_block (#60)
* Fix syntax error in gpio_control_block

Fixed syntax error that was only visible when running iverilog for simulation

* Apply automatic changes to Manifest and README.rst

Co-authored-by: marwaneltoukhy <marwaneltoukhy@users.noreply.github.com>
2022-04-09 00:24:51 -07:00
Kareem Farid c84e1393e7
updates to top level caravel (#59)
* REVERT ME: temporarily match simple_por pin in verilog with lef

* - update configs
- add patch file for power routing def

* - update the following caravel toplevel views
    - gl
    - mag
    - def
- add caravel power routing def

* Apply automatic changes to Manifest and README.rst

* update gl mag and def for caravel

* Revert "REVERT ME: temporarily match simple_por pin in verilog with lef"

This reverts commit b70c27c69f.

* update caravel gds

* Apply automatic changes to Manifest and README.rst

* Added text and logo cells back into the caravel top level.  Put an
isolated ground marker layer on the xres_buf layout.  Corrected
the power supply pin names on the gate level verilog netlist of
simple_por in caravel.v.  Updated the copyright block text.
Corrected DRC errors in the top level routing.

Co-authored-by: Tim Edwards <tim@opencircuitdesign.com>
2022-04-08 09:31:33 -07:00
Kareem Farid dcebeed7e7
Mgmt protect update (#58)
* - add openlane patch file to for input buffering workaround
- update configuration of mgmt protect

* mgmt_protect updated

* mgmt_protect updated

* remove some via3 to fix power shorts

Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-08 09:29:49 -07:00
Kareem Farid e3b9a99154
- update gpio_control_block config (#57)
- update gpio_control_block views
- gitignore gds/*gds
2022-04-08 09:27:51 -07:00
Marwan Abbas e9f023f9fa
Introduction of PDK variable (#39)
* added PDK_VARIENT variable

* changed variable name to PDK

* resolve issue

Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-08 09:05:58 -07:00
R. Timothy Edwards ab85f607e9
Corrected the definitions for the pullup and pulldown input modes (#51)
in "defs.h" per the github issue #15 posted by Sylvain Munaut.
2022-04-07 07:46:02 -07:00
R. Timothy Edwards 07012ce2aa
Corrected the issue reported on the github issue tracker (#34) (#50)
* Corrected the issue reported on the github issue tracker (#34)
in which the use of "clocking" as an instance name in caravel and
caravan conflicts with the system verilog keyword of the same
name.

* Apply automatic changes to Manifest and README.rst

Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
2022-04-07 07:44:57 -07:00
Kareem Farid 8e02ea79d8
fix wrong cell name
`sky130_fd_sc_hd__dlygate4sd2` is called `sky130_fd_sc_hd__dlygate4sd2_1`
2022-03-22 17:02:36 +02:00
Tim Edwards be56cb19ed Modified the GPIO control block to put additional delay on the data
output of each GPIO block to overcome any wiring delays between
GPIO blocks that could potentially cause hold violations.
2022-03-21 12:07:12 -04:00
Tim Edwards 2f6fe69b36 Corrected the gen_gpio_defaults.py script so that it behaves
correctly no matter how the "gpio_defaults_block.mag" and
"gl/gpio_defaults_block.v" are defined.  Previously it assumed
that they both defined all bits as zero, which was not the case
for the layout.  Now both define bit value 0x0402 and the script
can flip bits either direction as needed in both verilog and
layout
2021-12-29 15:42:41 -05:00
Tim Edwards 7a45a096a5 Added a testbench that exercises the SRAM 2nd (read-only) port, as
it was configured for the caravel_pico SoC, with the housekeeping
SPI able to access the upper 256-word section of the memory if the
CSB bit in the housekeeping control register is cleared.  This
testbench tests both access through housekeeping and access directly
from the SoC through the memory-mapped address.
2021-12-29 11:24:17 -05:00
manarabdelaty dc5d47c812 Merge remote-tracking branch 'origin/main' into fix_tri_state_nets 2021-12-24 22:20:11 +02:00
manarabdelaty 981043cb7b [DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells 2021-12-24 21:06:58 +02:00
Tim Edwards 1526214cc1 Modifications to some of the Makefiles to make the specific RISC-V
architecture type passed to gcc as the value to the '-march='
option an environment variable, setting that environment variable
to "rv32imc" by default, and overriding it with "rv32ic" specifically
for the new caravel_pico without the multiplier and divider option,
on testbenches "mem" and "storage" which both have multiplies in the
C code.
2021-12-24 13:42:36 -05:00
Tim Edwards 55836db2d2 Added a reference to the new file "gl/mgmt_defines.v" in the
caravel_pico repository.  The issue is that each SoC implementation
defines its own modules and therefore needs its own includes.  The
implication is that this file now needs to exist in every SoC
implementation's verilog/gl/ directory.
2021-12-24 11:46:34 -05:00
jeffdi 2bc184f5c1 Merge remote-tracking branch 'origin/main' into main 2021-12-16 12:29:44 -08:00
jeffdi d4e6ed5684 adding user_project_wrapper empty files -- gds & lef 2021-12-16 12:29:35 -08:00
Tim Edwards ec93c72d18 Modified simple_por.v RTL to avoid the wire declaration that "cvc"
doesn't like (even though it's perfectly legal).
2021-12-08 12:16:19 -05:00
Tim Edwards 489bddcf98 Two more changes: (1) Correction to chip_io_alt.v RTL verilog to
match what was done earlier on chip_io.v, and (2) Corrected a
set of four labels in chip_io_alt.mag which had been rotated,
causing an error in LVS.
2021-12-07 17:16:44 -05:00
Tim Edwards c3fc004072 Corrected an error in verilog/gl/chip_io_alt.v, which was missing
connections to the core side VCCD1 and VSSD1 on the clamped3 pads.
Also added scripts for running LVS on chip_io to the mag/ directory,
and revised the scripts so that they will only re-run extraction if
there is no netlist file in the mag/ directory.
2021-12-07 10:06:35 -05:00
Tim Edwards a6d9dbf535 Corrected an inadvertant error in caravel_netlists.v that prevents
gate-level simulations from running.  Corrected caravan_netlists.v,
which did not have the same change made yesterday to caravel_netlists.v
for the DLL.
2021-12-07 09:14:59 -05:00
manarabdelaty db8cc0580b [DATA] Update GDS views for the chip_io/chip_io_alt/mgmt_protect_hv/mgmt_protect to match the mag view 2021-12-07 14:28:29 +02:00
manarabdelaty 45f20e3a24 Fix mgmt_protect_hv gate-level netlist 2021-12-07 13:38:30 +02:00
manarabdelaty bd88221d17 [DATA] Update caravel_clocking 2021-12-07 13:36:56 +02:00
Tim Edwards d4b4b7abb8 Fixed one bad error in clock_div which had been done without my
knowledge and which went undetected since before MPW-one.  Modified
the "pll" and "sysctrl" testbenches so that they run and measure
something useful.  Both exercise the clock monitoring on GPIO
outputs functions.  The PLL test also runs the digital locked
loop (behavioral verilog).  The PLL test overlaps sysctrl, but
"pll" cannot be run on gate level verilog, whereas "sysctrl" can.
2021-12-06 21:37:51 -05:00
Tim Edwards a9bb8bcd0a A handful of changes/corrections: (1) Housekeeping signal "user_clock"
(input for monitoring) changed from being connected directly to the
user project (where it shouldn't be) to the same signal on the input
side of the management protect block (where it should be).  This is
functionally the same.  Checked for any other signals connected
directly from the user project to any block other than mgmt_protect,
didn't find any (good).  Modified the gate-level netlists and top-level
layouts for caravel and caravan with the corresponding change.  This
was the only change affecting layout.  Also:  Revised the "pll"
testbench.  This is still ongoing work.  Also:  Fixed the way the
pins on I/O pads are declared in chip_io.v, mprj_io.v, and pads.v, so
that it isn't so bizarre.  Most of this change is functionally
agnostic (just a change in the way the ifdefs work), but did fix an
incorrect ifdef that causes the whole user power domain to be broken.
2021-12-06 19:38:24 -05:00
jeffdi 7854056b0c Merge remote-tracking branch 'origin/main' into main 2021-12-05 10:12:07 -08:00
jeffdi 619163aec1 fixes for RTL testbenches with mgmt core wrapper 2021-12-05 10:11:10 -08:00
manarabdelaty 00c845525a Merge branch 'main' of https://github.com/efabless/caravel_openframe into main 2021-12-05 19:50:01 +02:00
manarabdelaty aa766f9144 [DATA] Update caravel_clocking module 2021-12-05 19:44:28 +02:00
Tim Edwards bd6af6dddc Modified all of the Makefiles to better handle the GL netlist simulations,
which is now done through setting an environment variable to point to the
location of the management SoC wrapper.  Added the missing user project
wrappers to the GL directory (copied from the original caravel repository),
and also the GL version of chip_io_alt.  Modified the caravan_netlists and
caravel_netlists files to import the correct list of gate level netlists,
which has been reduced by moving "include" statements for components of the
management SoC into the management SoC repository (e.g., caravel_pico).
2021-12-03 17:13:53 -05:00
Tim Edwards b23ec956f3 Corrected the mprj_bitbang testbench verilog (it had not been corrected for
the change in the implementation of the serial loader, which split the load
signal out as a separate bit, and therefore had a separate bit-bang entry).
2021-12-03 15:06:15 -05:00
manarabdelaty ef1019b62a [DATA] Update caravel_clocking 2021-12-02 22:50:20 +02:00
Tim Edwards 07db7f0599 Merge branch 'main' of github.com:efabless/caravel_openframe into main
Pull before push.
2021-12-02 14:28:00 -05:00
Tim Edwards 4cf7aa2983 Changed the synchronized reset to occur on the clock falling edge
to give more timing margin when reset is released (note to self:
shouldn't the ext_reset also be synchronized?).
2021-12-02 14:26:59 -05:00
manarabdelaty 0067bd5b7c [DATA] Update caravel_clocking/digital_pll/housekeeping 2021-12-02 21:09:43 +02:00
Tim Edwards e0a318d2bf Fixed the GL verilog for caravel and caravan to add the two changes
just made to the RTL verilog and layout, to separate out hk_cyc_o
and to hook up the housekeeping user_clock input.
2021-11-30 12:31:07 -05:00
Tim Edwards 1035e8b469 Updated caravel and caravan layouts to reflect the simple change
to housekeeping and the management core wrapper to separate the
wb_cyc_i signal and connect to new signal hk_cyc_o on the
management core.  Also:  Fixed a dangling input (user_clock) on
the housekeeping (minor error caused by the earlier refactoring
and unnoticed because there is no testbench covering that
function).
2021-11-30 10:05:43 -05:00
manarabdelaty c4efcec989 [DATA] Update housekeeping views 2021-11-30 13:00:33 +02:00
Tim Edwards 4c0a2303b1 Modified the GL netlists to match the layout for the GPIO defaults
blocks;  that is, there are special versions of the block for the
first 6 GPIO pins.  That should allow the GL netlists to simulate,
although the end goal is to have the gen_gpio_defaults.py script
modify the GL netlists to exactly match the configuration, as is
done for the .mag layouts.
2021-11-29 20:17:11 -05:00
Tim Edwards 84c97b74b2 Corrected the instance names in the layout so that they once again
correspond to what the script gen_gpio_defaults.py is looking for.
2021-11-29 19:57:33 -05:00
Tim Edwards cd4a052344 Made the same change to caravan as was made to caravel in the
last commit.
2021-11-29 14:27:02 -05:00
Tim Edwards 4dac106297 This (late and invasive) change modifies the housekeeping block to
add a separate signal for the houskeeping wb_cyc_i wishbone signal,
instead of combining it with the user project's wb_cyc_i.  This
change makes it compatible with the LiteX implementation of the
wishbone bus.
2021-11-29 14:23:30 -05:00
manarabdelaty 8b1c5df909 [DATA] Update caravel_clocking module (timing clean) 2021-11-25 15:23:01 +02:00
manarabdelaty 05278ec738 [DATA] Update HK views (timing clean) 2021-11-25 12:54:22 +02:00