Merge remote-tracking branch 'origin/main' into main

2021-12-05 10:12:07 -08:00 · 2021-12-05 10:12:07 -08:00 · 7854056b0c
parent 619163aec1 00c845525a
commit 7854056b0c
39 changed files with 60511 additions and 44177 deletions
--- a/1
+++ b/1
@ -720,6 +720,7 @@ caravel_timing: ./def/caravel.def ./sdc/caravel.sdc ./verilog/gl/caravel.v check
 		report_checks -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 50;\
 		report_worst_slack -max ;\
 		report_worst_slack -min ;\
+		report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -slack_max 0.18 -group_count 10;\
 		" > ./def/tmp/caravel_timing.tcl 
 	sta -exit ./def/tmp/caravel_timing.tcl | tee ./signoff/caravel/caravel_timing.log 

--- a/def/caravel_clocking.def
+++ b/def/caravel_clocking.def
--- a/def/gpio_control_block.def
+++ b/def/gpio_control_block.def
--- a/def/gpio_defaults_block_0403.def
+++ b/def/gpio_defaults_block_0403.def
--- a/def/gpio_defaults_block_1803.def
+++ b/def/gpio_defaults_block_1803.def
--- a/def/mgmt_protect_hv.def
+++ b/def/mgmt_protect_hv.def
@ -0,0 +1,344 @@
+VERSION 5.8 ;
+DIVIDERCHAR "/" ;
+BUSBITCHARS "[]" ;
+DESIGN mgmt_protect_hv ;
+UNITS DISTANCE MICRONS 1000 ;
+
+DIEAREA ( 0 0 ) ( 150000 20000 ) ;
+
+ROW ROW_0 unithv 4800 4070 FS DO 302 BY 1 STEP 480 0
+ ;
+ROW ROW_1 unithv 4800 8140 N DO 302 BY 1 STEP 480 0
+ ;
+ROW ROW_2 unithv 4800 12210 FS DO 302 BY 1 STEP 480 0
+ ;
+TRACKS X 240 DO 313 STEP 480 LAYER li1 ;
+TRACKS Y 240 DO 42 STEP 480 LAYER li1 ;
+TRACKS X 185 DO 405 STEP 370 LAYER met1 ;
+TRACKS Y 185 DO 54 STEP 370 LAYER met1 ;
+TRACKS X 240 DO 313 STEP 480 LAYER met2 ;
+TRACKS Y 240 DO 42 STEP 480 LAYER met2 ;
+TRACKS X 370 DO 203 STEP 740 LAYER met3 ;
+TRACKS Y 370 DO 27 STEP 740 LAYER met3 ;
+TRACKS X 480 DO 156 STEP 960 LAYER met4 ;
+TRACKS Y 480 DO 21 STEP 960 LAYER met4 ;
+TRACKS X 1665 DO 45 STEP 3330 LAYER met5 ;
+TRACKS Y 1665 DO 6 STEP 3330 LAYER met5 ;
+
+VIAS 4 ;
+- via2_FR 
+ RECT met2 ( -140 -185 ) ( 140 185 ) 
+ RECT via2 ( -100 -100 ) ( 100 100 ) 
+ RECT met3 ( -165 -165 ) ( 165 165 ) 
+ 
+ ;
+- via4_FR 
+ RECT met4 ( -590 -590 ) ( 590 590 ) 
+ RECT via4 ( -400 -400 ) ( 400 400 ) 
+ RECT met5 ( -710 -710 ) ( 710 710 ) 
+ 
+ ;
+- via2_300x300 
+ 
+ VIARULE M2M3_PR
+  + CUTSIZE 200 200
+  + LAYERS met2 via2 met3
+  + CUTSPACING 200 200
+  + ENCLOSURE 50 85 65 65
+ ;
+- via_300x510 
+ 
+ VIARULE M1M2_PR
+  + CUTSIZE 150 150
+  + LAYERS met1 via met2
+  + CUTSPACING 170 170
+  + ENCLOSURE 75 180 75 180
+ ;
+END VIAS
+
+COMPONENTS 116 ;
+- mprj2_logic_high_hvl sky130_fd_sc_hvl__conb_1 + PLACED ( 50400 8140 ) N ;
+- mprj2_logic_high_lv sky130_fd_sc_hvl__lsbufhv2lv_1 + PLACED ( 87360 8140 ) N ;
+- mprj_logic_high_hvl sky130_fd_sc_hvl__conb_1 + PLACED ( 84960 8140 ) N ;
+- mprj_logic_high_lv sky130_fd_sc_hvl__lsbufhv2lv_1 + PLACED ( 52800 8140 ) N ;
+- FILLER_0_0 sky130_fd_sc_hvl__decap_8 + PLACED ( 4800 4070 ) FS ;
+- FILLER_0_8 sky130_fd_sc_hvl__decap_8 + PLACED ( 8640 4070 ) FS ;
+- FILLER_0_16 sky130_fd_sc_hvl__decap_8 + PLACED ( 12480 4070 ) FS ;
+- FILLER_0_24 sky130_fd_sc_hvl__decap_8 + PLACED ( 16320 4070 ) FS ;
+- FILLER_0_32 sky130_fd_sc_hvl__decap_8 + PLACED ( 20160 4070 ) FS ;
+- FILLER_0_40 sky130_fd_sc_hvl__decap_8 + PLACED ( 24000 4070 ) FS ;
+- FILLER_0_48 sky130_fd_sc_hvl__decap_8 + PLACED ( 27840 4070 ) FS ;
+- FILLER_0_56 sky130_fd_sc_hvl__decap_8 + PLACED ( 31680 4070 ) FS ;
+- FILLER_0_64 sky130_fd_sc_hvl__decap_8 + PLACED ( 35520 4070 ) FS ;
+- FILLER_0_72 sky130_fd_sc_hvl__decap_8 + PLACED ( 39360 4070 ) FS ;
+- FILLER_0_80 sky130_fd_sc_hvl__decap_8 + PLACED ( 43200 4070 ) FS ;
+- FILLER_0_88 sky130_fd_sc_hvl__decap_8 + PLACED ( 47040 4070 ) FS ;
+- FILLER_0_96 sky130_fd_sc_hvl__decap_8 + PLACED ( 50880 4070 ) FS ;
+- FILLER_0_104 sky130_fd_sc_hvl__decap_8 + PLACED ( 54720 4070 ) FS ;
+- FILLER_0_112 sky130_fd_sc_hvl__decap_8 + PLACED ( 58560 4070 ) FS ;
+- FILLER_0_120 sky130_fd_sc_hvl__decap_8 + PLACED ( 62400 4070 ) FS ;
+- FILLER_0_128 sky130_fd_sc_hvl__decap_8 + PLACED ( 66240 4070 ) FS ;
+- FILLER_0_136 sky130_fd_sc_hvl__decap_8 + PLACED ( 70080 4070 ) FS ;
+- FILLER_0_144 sky130_fd_sc_hvl__decap_8 + PLACED ( 73920 4070 ) FS ;
+- FILLER_0_152 sky130_fd_sc_hvl__decap_8 + PLACED ( 77760 4070 ) FS ;
+- FILLER_0_160 sky130_fd_sc_hvl__decap_8 + PLACED ( 81600 4070 ) FS ;
+- FILLER_0_168 sky130_fd_sc_hvl__decap_8 + PLACED ( 85440 4070 ) FS ;
+- FILLER_0_176 sky130_fd_sc_hvl__decap_8 + PLACED ( 89280 4070 ) FS ;
+- FILLER_0_184 sky130_fd_sc_hvl__decap_8 + PLACED ( 93120 4070 ) FS ;
+- FILLER_0_192 sky130_fd_sc_hvl__decap_8 + PLACED ( 96960 4070 ) FS ;
+- FILLER_0_200 sky130_fd_sc_hvl__decap_8 + PLACED ( 100800 4070 ) FS ;
+- FILLER_0_208 sky130_fd_sc_hvl__decap_8 + PLACED ( 104640 4070 ) FS ;
+- FILLER_0_216 sky130_fd_sc_hvl__decap_8 + PLACED ( 108480 4070 ) FS ;
+- FILLER_0_224 sky130_fd_sc_hvl__decap_8 + PLACED ( 112320 4070 ) FS ;
+- FILLER_0_232 sky130_fd_sc_hvl__decap_8 + PLACED ( 116160 4070 ) FS ;
+- FILLER_0_240 sky130_fd_sc_hvl__decap_8 + PLACED ( 120000 4070 ) FS ;
+- FILLER_0_248 sky130_fd_sc_hvl__decap_8 + PLACED ( 123840 4070 ) FS ;
+- FILLER_0_256 sky130_fd_sc_hvl__decap_8 + PLACED ( 127680 4070 ) FS ;
+- FILLER_0_264 sky130_fd_sc_hvl__decap_8 + PLACED ( 131520 4070 ) FS ;
+- FILLER_0_272 sky130_fd_sc_hvl__decap_8 + PLACED ( 135360 4070 ) FS ;
+- FILLER_0_280 sky130_fd_sc_hvl__decap_8 + PLACED ( 139200 4070 ) FS ;
+- FILLER_0_288 sky130_fd_sc_hvl__decap_8 + PLACED ( 143040 4070 ) FS ;
+- FILLER_0_296 sky130_fd_sc_hvl__decap_4 + PLACED ( 146880 4070 ) FS ;
+- FILLER_0_300 sky130_fd_sc_hvl__fill_2 + PLACED ( 148800 4070 ) FS ;
+- FILLER_1_0 sky130_fd_sc_hvl__decap_8 + PLACED ( 4800 8140 ) N ;
+- FILLER_1_8 sky130_fd_sc_hvl__decap_8 + PLACED ( 8640 8140 ) N ;
+- FILLER_1_16 sky130_fd_sc_hvl__decap_8 + PLACED ( 12480 8140 ) N ;
+- FILLER_1_24 sky130_fd_sc_hvl__decap_8 + PLACED ( 16320 8140 ) N ;
+- FILLER_1_32 sky130_fd_sc_hvl__decap_8 + PLACED ( 20160 8140 ) N ;
+- FILLER_1_40 sky130_fd_sc_hvl__decap_8 + PLACED ( 24000 8140 ) N ;
+- FILLER_1_48 sky130_fd_sc_hvl__decap_8 + PLACED ( 27840 8140 ) N ;
+- FILLER_1_56 sky130_fd_sc_hvl__decap_8 + PLACED ( 31680 8140 ) N ;
+- FILLER_1_64 sky130_fd_sc_hvl__decap_8 + PLACED ( 35520 8140 ) N ;
+- FILLER_1_72 sky130_fd_sc_hvl__decap_8 + PLACED ( 39360 8140 ) N ;
+- FILLER_1_80 sky130_fd_sc_hvl__decap_8 + PLACED ( 43200 8140 ) N ;
+- FILLER_1_88 sky130_fd_sc_hvl__decap_4 + PLACED ( 47040 8140 ) N ;
+- FILLER_1_92 sky130_fd_sc_hvl__fill_2 + PLACED ( 48960 8140 ) N ;
+- FILLER_1_94 sky130_fd_sc_hvl__fill_1 + PLACED ( 49920 8140 ) N ;
+- FILLER_1_117 sky130_fd_sc_hvl__decap_8 + PLACED ( 60960 8140 ) N ;
+- FILLER_1_125 sky130_fd_sc_hvl__decap_8 + PLACED ( 64800 8140 ) N ;
+- FILLER_1_133 sky130_fd_sc_hvl__decap_8 + PLACED ( 68640 8140 ) N ;
+- FILLER_1_141 sky130_fd_sc_hvl__decap_8 + PLACED ( 72480 8140 ) N ;
+- FILLER_1_149 sky130_fd_sc_hvl__decap_8 + PLACED ( 76320 8140 ) N ;
+- FILLER_1_157 sky130_fd_sc_hvl__decap_8 + PLACED ( 80160 8140 ) N ;
+- FILLER_1_165 sky130_fd_sc_hvl__fill_2 + PLACED ( 84000 8140 ) N ;
+- FILLER_1_189 sky130_fd_sc_hvl__decap_8 + PLACED ( 95520 8140 ) N ;
+- FILLER_1_197 sky130_fd_sc_hvl__decap_8 + PLACED ( 99360 8140 ) N ;
+- FILLER_1_205 sky130_fd_sc_hvl__decap_8 + PLACED ( 103200 8140 ) N ;
+- FILLER_1_213 sky130_fd_sc_hvl__decap_8 + PLACED ( 107040 8140 ) N ;
+- FILLER_1_221 sky130_fd_sc_hvl__decap_8 + PLACED ( 110880 8140 ) N ;
+- FILLER_1_229 sky130_fd_sc_hvl__decap_8 + PLACED ( 114720 8140 ) N ;
+- FILLER_1_237 sky130_fd_sc_hvl__decap_8 + PLACED ( 118560 8140 ) N ;
+- FILLER_1_245 sky130_fd_sc_hvl__decap_8 + PLACED ( 122400 8140 ) N ;
+- FILLER_1_253 sky130_fd_sc_hvl__decap_8 + PLACED ( 126240 8140 ) N ;
+- FILLER_1_261 sky130_fd_sc_hvl__decap_8 + PLACED ( 130080 8140 ) N ;
+- FILLER_1_269 sky130_fd_sc_hvl__decap_8 + PLACED ( 133920 8140 ) N ;
+- FILLER_1_277 sky130_fd_sc_hvl__decap_8 + PLACED ( 137760 8140 ) N ;
+- FILLER_1_285 sky130_fd_sc_hvl__decap_8 + PLACED ( 141600 8140 ) N ;
+- FILLER_1_293 sky130_fd_sc_hvl__decap_8 + PLACED ( 145440 8140 ) N ;
+- FILLER_1_301 sky130_fd_sc_hvl__fill_1 + PLACED ( 149280 8140 ) N ;
+- FILLER_2_0 sky130_fd_sc_hvl__decap_8 + PLACED ( 4800 12210 ) FS ;
+- FILLER_2_8 sky130_fd_sc_hvl__decap_8 + PLACED ( 8640 12210 ) FS ;
+- FILLER_2_16 sky130_fd_sc_hvl__decap_8 + PLACED ( 12480 12210 ) FS ;
+- FILLER_2_24 sky130_fd_sc_hvl__decap_8 + PLACED ( 16320 12210 ) FS ;
+- FILLER_2_32 sky130_fd_sc_hvl__decap_8 + PLACED ( 20160 12210 ) FS ;
+- FILLER_2_40 sky130_fd_sc_hvl__decap_8 + PLACED ( 24000 12210 ) FS ;
+- FILLER_2_48 sky130_fd_sc_hvl__decap_8 + PLACED ( 27840 12210 ) FS ;
+- FILLER_2_56 sky130_fd_sc_hvl__decap_8 + PLACED ( 31680 12210 ) FS ;
+- FILLER_2_64 sky130_fd_sc_hvl__decap_8 + PLACED ( 35520 12210 ) FS ;
+- FILLER_2_72 sky130_fd_sc_hvl__decap_8 + PLACED ( 39360 12210 ) FS ;
+- FILLER_2_80 sky130_fd_sc_hvl__decap_8 + PLACED ( 43200 12210 ) FS ;
+- FILLER_2_88 sky130_fd_sc_hvl__decap_8 + PLACED ( 47040 12210 ) FS ;
+- FILLER_2_96 sky130_fd_sc_hvl__decap_4 + PLACED ( 50880 12210 ) FS ;
+- FILLER_2_117 sky130_fd_sc_hvl__decap_8 + PLACED ( 60960 12210 ) FS ;
+- FILLER_2_125 sky130_fd_sc_hvl__decap_8 + PLACED ( 64800 12210 ) FS ;
+- FILLER_2_133 sky130_fd_sc_hvl__decap_8 + PLACED ( 68640 12210 ) FS ;
+- FILLER_2_141 sky130_fd_sc_hvl__decap_8 + PLACED ( 72480 12210 ) FS ;
+- FILLER_2_149 sky130_fd_sc_hvl__decap_8 + PLACED ( 76320 12210 ) FS ;
+- FILLER_2_157 sky130_fd_sc_hvl__decap_8 + PLACED ( 80160 12210 ) FS ;
+- FILLER_2_165 sky130_fd_sc_hvl__decap_4 + PLACED ( 84000 12210 ) FS ;
+- FILLER_2_169 sky130_fd_sc_hvl__fill_2 + PLACED ( 85920 12210 ) FS ;
+- FILLER_2_171 sky130_fd_sc_hvl__fill_1 + PLACED ( 86880 12210 ) FS ;
+- FILLER_2_189 sky130_fd_sc_hvl__decap_8 + PLACED ( 95520 12210 ) FS ;
+- FILLER_2_197 sky130_fd_sc_hvl__decap_8 + PLACED ( 99360 12210 ) FS ;
+- FILLER_2_205 sky130_fd_sc_hvl__decap_8 + PLACED ( 103200 12210 ) FS ;
+- FILLER_2_213 sky130_fd_sc_hvl__decap_8 + PLACED ( 107040 12210 ) FS ;
+- FILLER_2_221 sky130_fd_sc_hvl__decap_8 + PLACED ( 110880 12210 ) FS ;
+- FILLER_2_229 sky130_fd_sc_hvl__decap_8 + PLACED ( 114720 12210 ) FS ;
+- FILLER_2_237 sky130_fd_sc_hvl__decap_8 + PLACED ( 118560 12210 ) FS ;
+- FILLER_2_245 sky130_fd_sc_hvl__decap_8 + PLACED ( 122400 12210 ) FS ;
+- FILLER_2_253 sky130_fd_sc_hvl__decap_8 + PLACED ( 126240 12210 ) FS ;
+- FILLER_2_261 sky130_fd_sc_hvl__decap_8 + PLACED ( 130080 12210 ) FS ;
+- FILLER_2_269 sky130_fd_sc_hvl__decap_8 + PLACED ( 133920 12210 ) FS ;
+- FILLER_2_277 sky130_fd_sc_hvl__decap_8 + PLACED ( 137760 12210 ) FS ;
+- FILLER_2_285 sky130_fd_sc_hvl__decap_8 + PLACED ( 141600 12210 ) FS ;
+- FILLER_2_293 sky130_fd_sc_hvl__decap_8 + PLACED ( 145440 12210 ) FS ;
+- FILLER_2_301 sky130_fd_sc_hvl__fill_1 + PLACED ( 149280 12210 ) FS ;
+END COMPONENTS
+
+PINS 21 ;
+- mprj2_vdd_logic1 + NET mprj2_vdd_logic1 + DIRECTION OUTPUT + USE SIGNAL 
+  + LAYER met3 ( -2000 -300 ) ( 2000 300 )
+  + PLACED ( 2000 4810 ) N ;
+- mprj_vdd_logic1 + NET mprj_vdd_logic1 + DIRECTION OUTPUT + USE SIGNAL 
+  + LAYER met3 ( -2000 -300 ) ( 2000 300 )
+  + PLACED ( 2000 14430 ) N ;
+- vccd + NET vccd + DIRECTION INOUT + USE POWER 
+  + LAYER met2 ( -150 -6360 ) ( 150 6360 )
+  + FIXED ( 94800 10175 ) N + SPECIAL ;
+- vccd + NET vccd + DIRECTION INOUT + USE POWER 
+  + LAYER met2 ( -150 -6360 ) ( 150 6360 )
+  + FIXED ( 14800 10175 ) N + SPECIAL ;
+- vccd + NET vccd + DIRECTION INOUT + USE POWER 
+  + LAYER met3 ( -72480 -150 ) ( 72480 150 )
+  + FIXED ( 77280 15615 ) N + SPECIAL ;
+- vccd + NET vccd + DIRECTION INOUT + USE POWER 
+  + LAYER met3 ( -72480 -150 ) ( 72480 150 )
+  + FIXED ( 77280 4815 ) N + SPECIAL ;
+- vssd + NET vssd + DIRECTION INOUT + USE GROUND 
+  + LAYER met2 ( -150 -6360 ) ( 150 6360 )
+  + FIXED ( 134800 10175 ) N + SPECIAL ;
+- vssd + NET vssd + DIRECTION INOUT + USE GROUND 
+  + LAYER met2 ( -150 -6360 ) ( 150 6360 )
+  + FIXED ( 54800 10175 ) N + SPECIAL ;
+- vssd + NET vssd + DIRECTION INOUT + USE GROUND 
+  + LAYER met3 ( -72480 -150 ) ( 72480 150 )
+  + FIXED ( 77280 10215 ) N + SPECIAL ;
+- vdda1 + NET vdda1 + DIRECTION INOUT + USE POWER 
+  + LAYER met2 ( -150 -6105 ) ( 150 6105 )
+  + FIXED ( 96800 10175 ) N + SPECIAL ;
+- vdda1 + NET vdda1 + DIRECTION INOUT + USE POWER 
+  + LAYER met2 ( -150 -6105 ) ( 150 6105 )
+  + FIXED ( 16800 10175 ) N + SPECIAL ;
+- vdda1 + NET vdda1 + DIRECTION INOUT + USE POWER 
+  + LAYER met3 ( -72480 -150 ) ( 72480 150 )
+  + FIXED ( 77280 7070 ) N + SPECIAL ;
+- vssa1 + NET vssa1 + DIRECTION INOUT + USE GROUND 
+  + LAYER met2 ( -150 -6105 ) ( 150 6105 )
+  + FIXED ( 136800 10175 ) N + SPECIAL ;
+- vssa1 + NET vssa1 + DIRECTION INOUT + USE GROUND 
+  + LAYER met2 ( -150 -6105 ) ( 150 6105 )
+  + FIXED ( 56800 10175 ) N + SPECIAL ;
+- vssa1 + NET vssa1 + DIRECTION INOUT + USE GROUND 
+  + LAYER met3 ( -72480 -150 ) ( 72480 150 )
+  + FIXED ( 77280 12470 ) N + SPECIAL ;
+- vdda2 + NET vdda2 + DIRECTION INOUT + USE POWER 
+  + LAYER met2 ( -150 -6105 ) ( 150 6105 )
+  + FIXED ( 98800 10175 ) N + SPECIAL ;
+- vdda2 + NET vdda2 + DIRECTION INOUT + USE POWER 
+  + LAYER met2 ( -150 -6105 ) ( 150 6105 )
+  + FIXED ( 18800 10175 ) N + SPECIAL ;
+- vdda2 + NET vdda2 + DIRECTION INOUT + USE POWER 
+  + LAYER met3 ( -72480 -150 ) ( 72480 150 )
+  + FIXED ( 77280 9070 ) N + SPECIAL ;
+- vssa2 + NET vssa2 + DIRECTION INOUT + USE GROUND 
+  + LAYER met2 ( -150 -6105 ) ( 150 6105 )
+  + FIXED ( 138800 10175 ) N + SPECIAL ;
+- vssa2 + NET vssa2 + DIRECTION INOUT + USE GROUND 
+  + LAYER met2 ( -150 -6105 ) ( 150 6105 )
+  + FIXED ( 58800 10175 ) N + SPECIAL ;
+- vssa2 + NET vssa2 + DIRECTION INOUT + USE GROUND 
+  + LAYER met3 ( -72480 -150 ) ( 72480 150 )
+  + FIXED ( 77280 14470 ) N + SPECIAL ;
+END PINS
+
+SPECIALNETS 6 ;
+- vccd ( PIN vccd ) 
+  + ROUTED met1 0 + SHAPE STRIPE ( 94800 12210 ) via_300x510 
+    NEW met1 0 + SHAPE STRIPE ( 14800 12210 ) via_300x510 
+    NEW met1 0 + SHAPE STRIPE ( 94800 4070 ) via_300x510 
+    NEW met1 0 + SHAPE STRIPE ( 14800 4070 ) via_300x510 
+    NEW met2 0 + SHAPE STRIPE ( 94800 15615 ) via2_300x300 
+    NEW met2 0 + SHAPE STRIPE ( 14800 15615 ) via2_300x300 
+    NEW met2 0 + SHAPE STRIPE ( 94800 4815 ) via2_300x300 
+    NEW met2 0 + SHAPE STRIPE ( 14800 4815 ) via2_300x300 
+    NEW met3 300 + SHAPE STRIPE ( 4800 15615 ) ( 149760 15615 ) 
+    NEW met3 300 + SHAPE STRIPE ( 4800 4815 ) ( 149760 4815 ) 
+    NEW met2 300 + SHAPE STRIPE ( 94800 3815 ) ( 94800 16535 ) 
+    NEW met2 300 + SHAPE STRIPE ( 14800 3815 ) ( 14800 16535 ) 
+    NEW met1 510 + SHAPE FOLLOWPIN ( 4800 12210 ) ( 149760 12210 ) 
+    NEW met1 510 + SHAPE FOLLOWPIN ( 4800 4070 ) ( 149760 4070 ) 
+  + USE POWER ;
+- vssd ( PIN vssd ) 
+  + ROUTED met1 0 + SHAPE STRIPE ( 134800 16280 ) via_300x510 
+    NEW met1 0 + SHAPE STRIPE ( 54800 16280 ) via_300x510 
+    NEW met1 0 + SHAPE STRIPE ( 134800 8140 ) via_300x510 
+    NEW met1 0 + SHAPE STRIPE ( 54800 8140 ) via_300x510 
+    NEW met2 0 + SHAPE STRIPE ( 134800 10215 ) via2_300x300 
+    NEW met2 0 + SHAPE STRIPE ( 54800 10215 ) via2_300x300 
+    NEW met3 300 + SHAPE STRIPE ( 4800 10215 ) ( 149760 10215 ) 
+    NEW met2 300 + SHAPE STRIPE ( 134800 3815 ) ( 134800 16535 ) 
+    NEW met2 300 + SHAPE STRIPE ( 54800 3815 ) ( 54800 16535 ) 
+    NEW met1 510 + SHAPE FOLLOWPIN ( 4800 16280 ) ( 149760 16280 ) 
+    NEW met1 510 + SHAPE FOLLOWPIN ( 4800 8140 ) ( 149760 8140 ) 
+  + USE GROUND ;
+- vdda1 ( PIN vdda1 ) 
+  + ROUTED met2 0 + SHAPE STRIPE ( 96800 7070 ) via2_300x300 
+    NEW met2 0 + SHAPE STRIPE ( 16800 7070 ) via2_300x300 
+    NEW met3 300 + SHAPE STRIPE ( 4800 7070 ) ( 149760 7070 ) 
+    NEW met2 300 + SHAPE STRIPE ( 96800 4070 ) ( 96800 16280 ) 
+    NEW met2 300 + SHAPE STRIPE ( 16800 4070 ) ( 16800 16280 ) 
+  + USE POWER ;
+- vssa1 ( PIN vssa1 ) 
+  + ROUTED met2 0 + SHAPE STRIPE ( 136800 12470 ) via2_300x300 
+    NEW met2 0 + SHAPE STRIPE ( 56800 12470 ) via2_300x300 
+    NEW met3 300 + SHAPE STRIPE ( 4800 12470 ) ( 149760 12470 ) 
+    NEW met2 300 + SHAPE STRIPE ( 136800 4070 ) ( 136800 16280 ) 
+    NEW met2 300 + SHAPE STRIPE ( 56800 4070 ) ( 56800 16280 ) 
+  + USE GROUND ;
+- vdda2 ( PIN vdda2 ) 
+  + ROUTED met2 0 + SHAPE STRIPE ( 98800 9070 ) via2_300x300 
+    NEW met2 0 + SHAPE STRIPE ( 18800 9070 ) via2_300x300 
+    NEW met3 300 + SHAPE STRIPE ( 4800 9070 ) ( 149760 9070 ) 
+    NEW met2 300 + SHAPE STRIPE ( 98800 4070 ) ( 98800 16280 ) 
+    NEW met2 300 + SHAPE STRIPE ( 18800 4070 ) ( 18800 16280 ) 
+  + USE POWER ;
+- vssa2 ( PIN vssa2 ) 
+  + ROUTED met2 0 + SHAPE STRIPE ( 138800 14470 ) via2_300x300 
+    NEW met2 0 + SHAPE STRIPE ( 58800 14470 ) via2_300x300 
+    NEW met3 300 + SHAPE STRIPE ( 4800 14470 ) ( 149760 14470 ) 
+    NEW met2 300 + SHAPE STRIPE ( 138800 4070 ) ( 138800 16280 ) 
+    NEW met2 300 + SHAPE STRIPE ( 58800 4070 ) ( 58800 16280 ) 
+  + USE GROUND ;
+END SPECIALNETS
+
+NETS 4 ;
+- mprj2_vdd_logic1 ( PIN mprj2_vdd_logic1 ) ( mprj2_logic_high_lv X ) 
+  + ROUTED met2 ( 90960 6845 ) ( 90960 9065 )
+    NEW met3 ( 3360 4810 0 ) ( 4080 4810 )
+    NEW met2 ( 4080 4810 ) ( 4080 6845 )
+    NEW met1 ( 4080 6845 ) ( 90960 6845 )
+    NEW met1 ( 90960 6845 ) M1M2_PR
+    NEW li1 ( 90960 9065 ) L1M1_PR_MR
+    NEW met1 ( 90960 9065 ) M1M2_PR
+    NEW met2 ( 4080 4810 ) via2_FR
+    NEW met1 ( 4080 6845 ) M1M2_PR
+    NEW met1 ( 90960 9065 ) RECT ( -355 -70 0 70 )
+ USE SIGNAL ;
+- mprj_vdd_logic1 ( PIN mprj_vdd_logic1 ) ( mprj_logic_high_lv X ) 
+  + ROUTED met3 ( 3360 14430 0 ) ( 4080 14430 )
+    NEW met2 ( 4080 9435 ) ( 4080 14430 )
+    NEW met1 ( 4080 9435 ) ( 56400 9435 )
+    NEW li1 ( 56400 9435 ) L1M1_PR_MR
+    NEW met2 ( 4080 14430 ) via2_FR
+    NEW met1 ( 4080 9435 ) M1M2_PR
+ USE SIGNAL ;
+- mprj2_vdd_logic1_h ( mprj2_logic_high_lv A ) ( mprj2_logic_high_hvl HI ) 
+  + ROUTED met2 ( 87120 10915 ) ( 87120 13135 )
+    NEW met1 ( 87120 13135 ) ( 88080 13135 )
+    NEW met1 ( 51600 10915 ) ( 87120 10915 )
+    NEW met1 ( 87120 10915 ) M1M2_PR
+    NEW met1 ( 87120 13135 ) M1M2_PR
+    NEW li1 ( 88080 13135 ) L1M1_PR_MR
+    NEW li1 ( 51600 10915 ) L1M1_PR_MR
+ USE SIGNAL ;
+- mprj_vdd_logic1_h ( mprj_logic_high_lv A ) ( mprj_logic_high_hvl HI ) 
+  + ROUTED met2 ( 86160 11285 ) ( 86160 13135 )
+    NEW met1 ( 54000 13135 ) ( 86160 13135 )
+    NEW li1 ( 86160 11285 ) L1M1_PR_MR
+    NEW met1 ( 86160 11285 ) M1M2_PR
+    NEW met1 ( 86160 13135 ) M1M2_PR
+    NEW li1 ( 54000 13135 ) L1M1_PR_MR
+    NEW met1 ( 86160 11285 ) RECT ( -355 -70 0 70 )
+ USE SIGNAL ;
+END NETS
+END DESIGN
--- a/def/xres_buf.def
+++ b/def/xres_buf.def
@ -0,0 +1,159 @@
+VERSION 5.8 ;
+DIVIDERCHAR "/" ;
+BUSBITCHARS "[]" ;
+DESIGN xres_buf ;
+UNITS DISTANCE MICRONS 1000 ;
+
+DIEAREA ( 0 0 ) ( 20000 17000 ) ;
+
+ROW ROW_0 unithv 2400 4070 FS DO 31 BY 1 STEP 480 0
+ ;
+ROW ROW_1 unithv 2400 8140 N DO 31 BY 1 STEP 480 0
+ ;
+ROW ROW_2 unithv 2400 12210 FS DO 31 BY 1 STEP 480 0
+ ;
+TRACKS X 240 DO 42 STEP 480 LAYER li1 ;
+TRACKS Y 240 DO 35 STEP 480 LAYER li1 ;
+TRACKS X 185 DO 54 STEP 370 LAYER met1 ;
+TRACKS Y 185 DO 46 STEP 370 LAYER met1 ;
+TRACKS X 240 DO 42 STEP 480 LAYER met2 ;
+TRACKS Y 240 DO 35 STEP 480 LAYER met2 ;
+TRACKS X 370 DO 27 STEP 740 LAYER met3 ;
+TRACKS Y 370 DO 23 STEP 740 LAYER met3 ;
+TRACKS X 480 DO 21 STEP 960 LAYER met4 ;
+TRACKS Y 480 DO 18 STEP 960 LAYER met4 ;
+TRACKS X 1665 DO 6 STEP 3330 LAYER met5 ;
+TRACKS Y 1665 DO 5 STEP 3330 LAYER met5 ;
+
+VIAS 5 ;
+- via2_FR 
+ RECT met2 ( -140 -185 ) ( 140 185 ) 
+ RECT via2 ( -100 -100 ) ( 100 100 ) 
+ RECT met3 ( -165 -165 ) ( 165 165 ) 
+ 
+ ;
+- via4_FR 
+ RECT met4 ( -590 -590 ) ( 590 590 ) 
+ RECT via4 ( -400 -400 ) ( 400 400 ) 
+ RECT met5 ( -710 -710 ) ( 710 710 ) 
+ 
+ ;
+- via_900x510 
+ 
+ VIARULE M1M2_PR
+  + CUTSIZE 150 150
+  + LAYERS met1 via met2
+  + CUTSPACING 170 170
+  + ENCLOSURE 215 180 55 180
+  + ROWCOL 1 2
+ ;
+- via2_900x510 
+ 
+ VIARULE M2M3_PR
+  + CUTSIZE 200 200
+  + LAYERS met2 via2 met3
+  + CUTSPACING 200 200
+  + ENCLOSURE 40 155 150 65
+  + ROWCOL 1 2
+ ;
+- via3_900x510 
+ 
+ VIARULE M3M4_PR
+  + CUTSIZE 200 200
+  + LAYERS met3 via3 met4
+  + CUTSPACING 200 200
+  + ENCLOSURE 150 60 150 155
+  + ROWCOL 1 2
+ ;
+END VIAS
+
+COMPONENTS 16 ;
+- lvlshiftdown sky130_fd_sc_hvl__lsbufhv2lv_1 + PLACED ( 8640 8140 ) N ;
+- ANTENNA_lvlshiftdown_A sky130_fd_sc_hvl__diode_2 + PLACED ( 7680 12210 ) FS ;
+- FILLER_0_0 sky130_fd_sc_hvl__decap_8 + PLACED ( 2400 4070 ) FS ;
+- FILLER_0_8 sky130_fd_sc_hvl__decap_8 + PLACED ( 6240 4070 ) FS ;
+- FILLER_0_16 sky130_fd_sc_hvl__decap_8 + PLACED ( 10080 4070 ) FS ;
+- FILLER_0_24 sky130_fd_sc_hvl__decap_4 + PLACED ( 13920 4070 ) FS ;
+- FILLER_0_28 sky130_fd_sc_hvl__fill_2 + PLACED ( 15840 4070 ) FS ;
+- FILLER_0_30 sky130_fd_sc_hvl__fill_1 + PLACED ( 16800 4070 ) FS ;
+- FILLER_1_0 sky130_fd_sc_hvl__decap_8 + PLACED ( 2400 8140 ) N ;
+- FILLER_1_8 sky130_fd_sc_hvl__decap_4 + PLACED ( 6240 8140 ) N ;
+- FILLER_1_12 sky130_fd_sc_hvl__fill_1 + PLACED ( 8160 8140 ) N ;
+- FILLER_1_30 sky130_fd_sc_hvl__fill_1 + PLACED ( 16800 8140 ) N ;
+- FILLER_2_0 sky130_fd_sc_hvl__decap_8 + PLACED ( 2400 12210 ) FS ;
+- FILLER_2_8 sky130_fd_sc_hvl__fill_2 + PLACED ( 6240 12210 ) FS ;
+- FILLER_2_10 sky130_fd_sc_hvl__fill_1 + PLACED ( 7200 12210 ) FS ;
+- FILLER_2_30 sky130_fd_sc_hvl__fill_1 + PLACED ( 16800 12210 ) FS ;
+END COMPONENTS
+
+PINS 6 ;
+- A + NET A + DIRECTION INPUT + USE SIGNAL 
+  + LAYER met2 ( -140 -3000 ) ( 140 3000 )
+  + PLACED ( 16560 16000 ) N ;
+- X + NET X + DIRECTION OUTPUT + USE SIGNAL 
+  + LAYER met2 ( -140 -3000 ) ( 140 3000 )
+  + PLACED ( 3120 1000 ) N ;
+- VPWR + NET VPWR + DIRECTION INOUT + USE POWER 
+  + LAYER met4 ( -450 -6360 ) ( 450 6360 )
+  + FIXED ( 4400 10175 ) N + SPECIAL ;
+- VGND + NET VGND + DIRECTION INOUT + USE GROUND 
+  + LAYER met4 ( -450 -6360 ) ( 450 6360 )
+  + FIXED ( 10900 10175 ) N + SPECIAL ;
+- LVPWR + NET LVPWR + DIRECTION INOUT + USE POWER 
+  + LAYER met4 ( -450 -6105 ) ( 450 6105 )
+  + FIXED ( 8800 10175 ) N + SPECIAL ;
+- LVGND + NET LVGND + DIRECTION INOUT + USE GROUND 
+  + LAYER met4 ( -450 -6105 ) ( 450 6105 )
+  + FIXED ( 15300 10175 ) N + SPECIAL ;
+END PINS
+
+SPECIALNETS 4 ;
+- VPWR ( PIN VPWR ) 
+  + ROUTED met3 0 + SHAPE STRIPE ( 4400 12210 ) via3_900x510 
+    NEW met2 0 + SHAPE STRIPE ( 4400 12210 ) via2_900x510 
+    NEW met1 0 + SHAPE STRIPE ( 4400 12210 ) via_900x510 
+    NEW met3 0 + SHAPE STRIPE ( 4400 4070 ) via3_900x510 
+    NEW met2 0 + SHAPE STRIPE ( 4400 4070 ) via2_900x510 
+    NEW met1 0 + SHAPE STRIPE ( 4400 4070 ) via_900x510 
+    NEW met4 900 + SHAPE STRIPE ( 4400 3815 ) ( 4400 16535 ) 
+    NEW met1 510 + SHAPE FOLLOWPIN ( 2400 12210 ) ( 17280 12210 ) 
+    NEW met1 510 + SHAPE FOLLOWPIN ( 2400 4070 ) ( 17280 4070 ) 
+  + USE POWER ;
+- VGND ( PIN VGND ) 
+  + ROUTED met3 0 + SHAPE STRIPE ( 10900 16280 ) via3_900x510 
+    NEW met2 0 + SHAPE STRIPE ( 10900 16280 ) via2_900x510 
+    NEW met1 0 + SHAPE STRIPE ( 10900 16280 ) via_900x510 
+    NEW met3 0 + SHAPE STRIPE ( 10900 8140 ) via3_900x510 
+    NEW met2 0 + SHAPE STRIPE ( 10900 8140 ) via2_900x510 
+    NEW met1 0 + SHAPE STRIPE ( 10900 8140 ) via_900x510 
+    NEW met4 900 + SHAPE STRIPE ( 10900 3815 ) ( 10900 16535 ) 
+    NEW met1 510 + SHAPE FOLLOWPIN ( 2400 16280 ) ( 17280 16280 ) 
+    NEW met1 510 + SHAPE FOLLOWPIN ( 2400 8140 ) ( 17280 8140 ) 
+  + USE GROUND ;
+- LVPWR ( PIN LVPWR ) 
+  + ROUTED met4 900 + SHAPE STRIPE ( 8800 4070 ) ( 8800 16280 ) 
+  + USE POWER ;
+- LVGND ( PIN LVGND ) 
+  + ROUTED met4 900 + SHAPE STRIPE ( 15300 4070 ) ( 15300 16280 ) 
+  + USE GROUND ;
+END SPECIALNETS
+
+NETS 2 ;
+- A ( PIN A ) ( ANTENNA_lvlshiftdown_A DIODE ) ( lvlshiftdown A ) 
+  + ROUTED met1 ( 9840 13135 ) ( 16080 13135 )
+    NEW met2 ( 16080 12950 ) ( 16080 13135 )
+    NEW met2 ( 16080 12950 ) ( 16560 12950 )
+    NEW met2 ( 16560 12950 ) ( 16560 13690 0 )
+    NEW met1 ( 8400 13135 ) ( 9840 13135 )
+    NEW li1 ( 9840 13135 ) L1M1_PR_MR
+    NEW met1 ( 16080 13135 ) M1M2_PR
+    NEW li1 ( 8400 13135 ) L1M1_PR_MR
+ USE SIGNAL ;
+- X ( PIN X ) ( lvlshiftdown X ) 
+  + ROUTED met2 ( 3120 3330 0 ) ( 3120 9805 )
+    NEW met1 ( 3120 9805 ) ( 12240 9805 )
+    NEW met1 ( 3120 9805 ) M1M2_PR
+    NEW li1 ( 12240 9805 ) L1M1_PR_MR
+ USE SIGNAL ;
+END NETS
+END DESIGN
--- a/gds/caravel_clocking.gds.gz
+++ b/gds/caravel_clocking.gds.gz
--- a/lef/caravel_clocking.lef
+++ b/lef/caravel_clocking.lef
@ -213,35 +213,34 @@ MACRO caravel_clocking
        RECT 5.215 -0.050 5.375 0.060 ;
        RECT 6.585 -0.085 6.755 0.085 ;
        RECT 12.565 -0.085 12.735 0.085 ;
-        RECT 16.700 -0.085 16.870 0.085 ;
-        RECT 17.175 -0.050 17.335 0.060 ;
-        RECT 19.470 -0.085 19.640 0.085 ;
-        RECT 19.925 -0.085 20.095 0.085 ;
-        RECT 23.600 -0.055 23.720 0.055 ;
+        RECT 18.545 -0.085 18.715 0.085 ;
        RECT 24.525 -0.085 24.695 0.085 ;
-        RECT 26.365 -0.085 26.535 0.085 ;
-        RECT 29.580 -0.055 29.700 0.055 ;
-        RECT 30.780 -0.085 30.950 0.085 ;
-        RECT 34.645 -0.085 34.815 0.085 ;
+        RECT 26.360 -0.055 26.480 0.055 ;
+        RECT 29.585 -0.085 29.755 0.085 ;
+        RECT 30.500 -0.085 30.670 0.085 ;
+        RECT 31.885 -0.085 32.055 0.085 ;
+        RECT 35.560 -0.055 35.680 0.055 ;
        RECT 36.485 -0.085 36.655 0.085 ;
-        RECT 45.685 -0.085 45.855 0.085 ;
-        RECT 46.145 -0.085 46.315 0.085 ;
+        RECT 42.465 -0.085 42.635 0.085 ;
+        RECT 45.220 -0.055 45.340 0.055 ;
+        RECT 47.060 -0.085 47.230 0.085 ;
+        RECT 47.520 -0.055 47.640 0.055 ;
        RECT 48.445 -0.085 48.615 0.085 ;
-        RECT 50.285 -0.085 50.455 0.085 ;
-        RECT 53.500 -0.055 53.620 0.055 ;
        RECT 54.425 -0.085 54.595 0.085 ;
-        RECT 60.400 -0.055 60.520 0.055 ;
-        RECT 60.865 -0.085 61.035 0.085 ;
-        RECT 64.545 -0.085 64.715 0.085 ;
-        RECT 66.385 -0.085 66.555 0.085 ;
-        RECT 72.375 -0.050 72.535 0.060 ;
-        RECT 75.585 -0.085 75.755 0.085 ;
-        RECT 76.045 -0.085 76.215 0.085 ;
-        RECT 78.345 -0.085 78.515 0.085 ;
+        RECT 61.780 -0.085 61.950 0.085 ;
+        RECT 62.245 -0.085 62.415 0.085 ;
+        RECT 67.300 -0.085 67.470 0.085 ;
+        RECT 67.770 -0.085 67.940 0.085 ;
+        RECT 69.145 -0.085 69.315 0.085 ;
+        RECT 72.365 -0.085 72.535 0.085 ;
+        RECT 78.805 -0.085 78.975 0.085 ;
+        RECT 79.260 -0.085 79.430 0.085 ;
+        RECT 82.485 -0.085 82.655 0.085 ;
+        RECT 82.955 -0.050 83.115 0.060 ;
        RECT 84.325 -0.085 84.495 0.085 ;
-        RECT 86.170 -0.085 86.340 0.085 ;
-        RECT 88.935 -0.050 89.095 0.060 ;
-        RECT 90.310 -0.085 90.480 0.085 ;
+        RECT 87.545 -0.085 87.715 0.085 ;
+        RECT 89.380 -0.055 89.500 0.055 ;
+        RECT 90.305 -0.085 90.475 0.085 ;
        RECT 93.985 -0.085 94.155 0.085 ;
      LAYER li1 ;
        RECT 0.000 0.085 94.300 54.485 ;
@ -265,22 +264,22 @@ MACRO caravel_clocking
        RECT 69.800 -0.240 71.340 0.000 ;
        RECT 85.300 -0.240 86.840 0.000 ;
      LAYER met3 ;
-        RECT 12.025 55.400 95.600 56.265 ;
-        RECT 12.025 49.320 96.000 55.400 ;
-        RECT 12.025 47.920 95.600 49.320 ;
-        RECT 12.025 41.840 96.000 47.920 ;
-        RECT 12.025 40.440 95.600 41.840 ;
-        RECT 12.025 34.360 96.000 40.440 ;
-        RECT 12.025 32.960 95.600 34.360 ;
-        RECT 12.025 26.880 96.000 32.960 ;
-        RECT 12.025 25.480 95.600 26.880 ;
-        RECT 12.025 19.400 96.000 25.480 ;
-        RECT 12.025 18.000 95.600 19.400 ;
-        RECT 12.025 11.920 96.000 18.000 ;
-        RECT 12.025 10.520 95.600 11.920 ;
-        RECT 12.025 4.440 96.000 10.520 ;
-        RECT 12.025 3.040 95.600 4.440 ;
-        RECT 12.025 0.000 96.000 3.040 ;
+        RECT 12.485 55.400 95.600 56.265 ;
+        RECT 12.485 49.320 96.000 55.400 ;
+        RECT 12.485 47.920 95.600 49.320 ;
+        RECT 12.485 41.840 96.000 47.920 ;
+        RECT 12.485 40.440 95.600 41.840 ;
+        RECT 12.485 34.360 96.000 40.440 ;
+        RECT 12.485 32.960 95.600 34.360 ;
+        RECT 12.485 26.880 96.000 32.960 ;
+        RECT 12.485 25.480 95.600 26.880 ;
+        RECT 12.485 19.400 96.000 25.480 ;
+        RECT 12.485 18.000 95.600 19.400 ;
+        RECT 12.485 11.920 96.000 18.000 ;
+        RECT 12.485 10.520 95.600 11.920 ;
+        RECT 12.485 4.440 96.000 10.520 ;
+        RECT 12.485 3.040 95.600 4.440 ;
+        RECT 12.485 0.000 96.000 3.040 ;
        RECT 23.270 -0.165 24.870 0.000 ;
        RECT 38.770 -0.165 40.370 0.000 ;
        RECT 54.270 -0.165 55.870 0.000 ;
--- a/mag/caravel_clocking.mag
+++ b/mag/caravel_clocking.mag
--- a/maglef/caravel_clocking.mag
+++ b/maglef/caravel_clocking.mag
@ -1,7 +1,7 @@
 magic
 tech sky130A
 magscale 1 2
-timestamp 1638477074
+timestamp 1638662846
 << nwell >>
 rect -38 10053 18898 10619
 rect -38 8965 18898 9531
@ -19,35 +19,34 @@ rect 305 -17 339 17
 rect 1043 -10 1075 12
 rect 1317 -17 1351 17
 rect 2513 -17 2547 17
-rect 3340 -17 3374 17
-rect 3435 -10 3467 12
-rect 3894 -17 3928 17
-rect 3985 -17 4019 17
-rect 4720 -11 4744 11
+rect 3709 -17 3743 17
 rect 4905 -17 4939 17
-rect 5273 -17 5307 17
-rect 5916 -11 5940 11
-rect 6156 -17 6190 17
-rect 6929 -17 6963 17
+rect 5272 -11 5296 11
+rect 5917 -17 5951 17
+rect 6100 -17 6134 17
+rect 6377 -17 6411 17
+rect 7112 -11 7136 11
 rect 7297 -17 7331 17
-rect 9137 -17 9171 17
-rect 9229 -17 9263 17
+rect 8493 -17 8527 17
+rect 9044 -11 9068 11
+rect 9412 -17 9446 17
+rect 9504 -11 9528 11
 rect 9689 -17 9723 17
-rect 10057 -17 10091 17
-rect 10700 -11 10724 11
 rect 10885 -17 10919 17
-rect 12080 -11 12104 11
-rect 12173 -17 12207 17
-rect 12909 -17 12943 17
-rect 13277 -17 13311 17
-rect 14475 -10 14507 12
-rect 15117 -17 15151 17
-rect 15209 -17 15243 17
-rect 15669 -17 15703 17
+rect 12356 -17 12390 17
+rect 12449 -17 12483 17
+rect 13460 -17 13494 17
+rect 13554 -17 13588 17
+rect 13829 -17 13863 17
+rect 14473 -17 14507 17
+rect 15761 -17 15795 17
+rect 15852 -17 15886 17
+rect 16497 -17 16531 17
+rect 16591 -10 16623 12
 rect 16865 -17 16899 17
-rect 17234 -17 17268 17
-rect 17787 -10 17819 12
-rect 18062 -17 18096 17
+rect 17509 -17 17543 17
+rect 17876 -11 17900 11
+rect 18061 -17 18095 17
 rect 18797 -17 18831 17
 << obsli1 >>
 rect 0 -17 18860 10897
@ -86,22 +85,22 @@ rect 19200 3680 20000 3800
 rect 19200 2184 20000 2304
 rect 19200 688 20000 808
 << obsm3 >>
-rect 2405 11080 19120 11253
-rect 2405 9864 19200 11080
-rect 2405 9584 19120 9864
-rect 2405 8368 19200 9584
-rect 2405 8088 19120 8368
-rect 2405 6872 19200 8088
-rect 2405 6592 19120 6872
-rect 2405 5376 19200 6592
-rect 2405 5096 19120 5376
-rect 2405 3880 19200 5096
-rect 2405 3600 19120 3880
-rect 2405 2384 19200 3600
-rect 2405 2104 19120 2384
-rect 2405 888 19200 2104
-rect 2405 608 19120 888
-rect 2405 0 19200 608
+rect 2497 11080 19120 11253
+rect 2497 9864 19200 11080
+rect 2497 9584 19120 9864
+rect 2497 8368 19200 9584
+rect 2497 8088 19120 8368
+rect 2497 6872 19200 8088
+rect 2497 6592 19120 6872
+rect 2497 5376 19200 6592
+rect 2497 5096 19120 5376
+rect 2497 3880 19200 5096
+rect 2497 3600 19120 3880
+rect 2497 2384 19200 3600
+rect 2497 2104 19120 2384
+rect 2497 888 19200 2104
+rect 2497 608 19120 888
+rect 2497 0 19200 608
 rect 4654 -33 4974 0
 rect 7754 -33 8074 0
 rect 10854 -33 11174 0
@ -190,7 +189,7 @@ string LEFclass BLOCK
 string FIXED_BBOX 0 0 20000 12000
 string LEFview TRUE
 string GDS_FILE ../gds/caravel_clocking.gds
-string GDS_END 1127518
-string GDS_START 370986
+string GDS_END 1197054
+string GDS_START 422960
 << end >>

--- a/openlane/caravel_clocking/base.sdc
+++ b/openlane/caravel_clocking/base.sdc
@ -5,20 +5,20 @@ create_clock [get_ports {"pll_clk90"} ] -name "pll_clk90"  -period 6.66666666666

 ## GENERATED CLOCKS
 # divided PLL clocks
-create_generated_clock -name pll_clk_divided -source [get_ports pll_clk] -divide_by 2 [get_pins _357_/Y] 
-create_generated_clock -name pll_clk90_divided -source [get_ports pll_clk90] -divide_by 2 [get_pins _360_/Y] 
+create_generated_clock -name pll_clk_divided -source [get_ports pll_clk] -divide_by 2 [get_pins _351_/Y] 
+create_generated_clock -name pll_clk90_divided -source [get_ports pll_clk90] -divide_by 2 [get_pins _354_/Y] 

 #  assign core_ext_clk = (use_pll_first) ? ext_clk_syncd : ext_clk;
-create_generated_clock -name core_ext_clk -source [get_ports ext_clk] -divide_by 1 [get_pins _418_/X] 
-create_generated_clock -name core_ext_clk_syncd -source [get_pins _432_/Q] -divide_by 1 [get_pins _418_/X] 
+create_generated_clock -name core_ext_clk -source [get_ports ext_clk] -divide_by 1 [get_pins _343_/X] 
+create_generated_clock -name core_ext_clk_syncd -source [get_pins _420_/Q] -divide_by 1 [get_pins _343_/X] 

 # assign core_clk = (use_pll_second) ? pll_clk_divided : core_ext_clk;
-create_generated_clock -name core_clk -source [get_pins _418_/X]  -divide_by 1 [get_pins _399_/X] 
-create_generated_clock -name core_clk_pll -source [get_pins _357_/Y]   -divide_by 1 [get_pins _399_/X] 
+create_generated_clock -name core_clk -source [get_pins _343_/X]  -divide_by 1 [get_ports core_clk] 
+create_generated_clock -name core_clk_pll -source [get_pins _351_/Y]   -divide_by 1 [get_ports core_clk] 

 # assign user_clk = (use_pll_second) ? pll_clk90_divided : core_ext_clk;
-create_generated_clock -name user_clk -source [get_pins _418_/X]  -divide_by 1 [get_pins _400_/X] 
-create_generated_clock -name user_clk_pll -source [get_pins _360_/Y]   -divide_by 1 [get_pins _400_/X] 
+create_generated_clock -name user_clk -source [get_pins _343_/X]  -divide_by 1 [get_ports user_clk] 
+create_generated_clock -name user_clk_pll -source [get_pins _354_/Y]   -divide_by 1 [get_ports user_clk]  

 # logically exclusive clocks, the generated pll clocks and the ext core clk
 set_clock_groups -logically_exclusive -group core_ext_clk -group core_ext_clk_syncd
--- a/openlane/caravel_clocking/config.tcl
+++ b/openlane/caravel_clocking/config.tcl
@ -56,10 +56,11 @@ set ::env(FP_PDN_HPITCH) 16.9
 set ::env(FP_PDN_VPITCH) 15.5

 ## Placement
-set ::env(PL_TARGET_DENSITY) 0.70
+set ::env(PL_TARGET_DENSITY) 0.715

 set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 1
 set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 1
+set ::env(GLB_RESIZER_HOLD_SLACK_MARGIN) 0.25

 ## Routing
 set ::env(GLB_RT_ADJUSTMENT) 0
--- a/openlane/caravel_clocking/no_synth.list
+++ b/openlane/caravel_clocking/no_synth.list
@ -1,3 +1,4 @@
+sky130_fd_sc_hd__inv_2
 sky130_fd_sc_hd__clkbuf_1
 sky130_fd_sc_hd__clkbuf_16
 sky130_fd_sc_hd__clkbuf_2
--- a/sdc/caravel.sdc
+++ b/sdc/caravel.sdc
@ -1,15 +1,13 @@
 set ::env(IO_PCT) "0.2"
-set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_1"
-set ::env(SYNTH_DRIVING_CELL_PIN) "Y"
 set ::env(SYNTH_MAX_FANOUT) "5"
-set ::env(SYNTH_CAP_LOAD) "33.442"
+set ::env(SYNTH_CAP_LOAD) "1"
 set ::env(SYNTH_TIMING_DERATE) 0.05
 set ::env(SYNTH_CLOCK_UNCERTAINITY) 0.25
 set ::env(SYNTH_CLOCK_TRANSITION) 0.15

 ## MASTER CLOCKS
 create_clock [get_ports {"clock"} ] -name "clock"  -period 25
-create_clock -name __VIRTUAL_CLK__ -period 25
+set_propagated_clock [get_clocks {"clock"}]

 ## INPUT/OUTPUT DELAYS
 set input_delay_value 1
@ -57,7 +55,6 @@ set_input_delay $input_delay_value  -clock [get_clocks {clock}] -add_delay [get_
 set_input_delay $input_delay_value  -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[36]}]
 set_input_delay $input_delay_value  -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[37]}]

-
 set_output_delay $output_delay_value  -clock [get_clocks {clock}] -add_delay [get_ports {flash_csb}]
 set_output_delay $output_delay_value  -clock [get_clocks {clock}] -add_delay [get_ports {flash_clk}]
 set_output_delay $output_delay_value  -clock [get_clocks {clock}] -add_delay [get_ports {flash_io0}]
@ -65,8 +62,16 @@ set_output_delay $output_delay_value  -clock [get_clocks {clock}] -add_delay [ge

 set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]

+## Set system monitoring mux select to zero so that the clock/user_clk monitoring is disabled 
+set_case_analysis 0 [get_pins housekeeping/_4449_/S]
+set_case_analysis 0 [get_pins housekeeping/_4450_/S]
+
+## FALSE PATHS (ASYNCHRONOUS INPUTS)
+set_false_path -from [get_ports {resetb}]
+set_false_path -from [get_ports mprj_io[*]]
+set_false_path -from [get_ports gpio]
+
 # TODO set this as parameter
-set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
 set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
 puts "\[INFO\]: Setting load to: $cap_load"
 set_load  $cap_load [all_outputs]
--- a/sdc/caravel_clocking.sdc
+++ b/sdc/caravel_clocking.sdc
@ -1,6 +1,6 @@
 ###############################################################################
 # Created by write_sdc
-# Thu Dec  2 20:30:29 2021
+# Sun Dec  5 00:06:34 2021
 ###############################################################################
 current_design caravel_clocking
 ###############################################################################
@ -18,15 +18,15 @@ create_clock -name pll_clk90 -period 6.6667 [get_ports {pll_clk90}]
 set_clock_transition 0.1500 [get_clocks {pll_clk90}]
 set_clock_uncertainty 0.2500 pll_clk90
 set_propagated_clock [get_clocks {pll_clk90}]
-create_generated_clock -name pll_clk_divided -source [get_ports {pll_clk}] -divide_by 2 [get_pins {_357_/Y}]
+create_generated_clock -name pll_clk_divided -source [get_ports {pll_clk}] -divide_by 2 [get_pins {_351_/Y}]
 set_propagated_clock [get_clocks {pll_clk_divided}]
-create_generated_clock -name pll_clk90_divided -source [get_ports {pll_clk90}] -divide_by 2 [get_pins {_360_/Y}]
+create_generated_clock -name pll_clk90_divided -source [get_ports {pll_clk90}] -divide_by 2 [get_pins {_354_/Y}]
 set_propagated_clock [get_clocks {pll_clk90_divided}]
-create_generated_clock -name core_ext_clk_syncd -source [get_pins {_432_/Q}] -divide_by 1 [get_pins {_418_/X}]
+create_generated_clock -name core_ext_clk_syncd -source [get_pins {_420_/Q}] -divide_by 1 [get_pins {_343_/X}]
 set_propagated_clock [get_clocks {core_ext_clk_syncd}]
-create_generated_clock -name core_clk_pll -source [get_pins {_357_/Y}] -divide_by 1 [get_pins {_399_/X}]
+create_generated_clock -name core_clk_pll -source [get_pins {_351_/Y}] -divide_by 1 [get_ports {core_clk}]
 set_propagated_clock [get_clocks {core_clk_pll}]
-create_generated_clock -name user_clk_pll -source [get_pins {_360_/Y}] -divide_by 1 [get_pins {_400_/X}]
+create_generated_clock -name user_clk_pll -source [get_pins {_354_/Y}] -divide_by 1 [get_ports {user_clk}]
 set_propagated_clock [get_clocks {user_clk_pll}]
 set_clock_groups -name group1 -logically_exclusive \
 -group [get_clocks {core_ext_clk_syncd}]
--- a/sdc/chip_io.sdc
+++ b/sdc/chip_io.sdc
@ -0,0 +1,10 @@
+###############################################################################
+# Created by write_sdc
+# Fri Nov  5 09:51:10 2021
+###############################################################################
+current_design chip_io
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name __VIRTUAL_CLK__ -period 10.0000 
+set_clock_uncertainty 0.2500 __VIRTUAL_CLK__
--- a/sdc/gpio_defaults_block_0403.sdc
+++ b/sdc/gpio_defaults_block_0403.sdc
@ -0,0 +1,10 @@
+###############################################################################
+# Created by write_sdc
+# Fri Nov  5 09:51:10 2021
+###############################################################################
+current_design gpio_defaults_block_0403
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name __VIRTUAL_CLK__ -period 10.0000 
+set_clock_uncertainty 0.2500 __VIRTUAL_CLK__
--- a/sdc/gpio_defaults_block_1803.sdc
+++ b/sdc/gpio_defaults_block_1803.sdc
@ -0,0 +1,10 @@
+###############################################################################
+# Created by write_sdc
+# Fri Nov  5 09:51:10 2021
+###############################################################################
+current_design gpio_defaults_block_0403
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name __VIRTUAL_CLK__ -period 10.0000 
+set_clock_uncertainty 0.2500 __VIRTUAL_CLK__
--- a/sdc/mgmt_protect_hv.sdc
+++ b/sdc/mgmt_protect_hv.sdc
@ -0,0 +1,6 @@
+current_design mgmt_protect_hv
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name __VIRTUAL_CLK__ -period 8.0000 
+set_clock_uncertainty 0.2500 __VIRTUAL_CLK__
--- a/sdc/simple_por.sdc
+++ b/sdc/simple_por.sdc
@ -0,0 +1,19 @@
+###############################################################################
+# Created by write_sdc
+# Fri Nov  5 09:51:10 2021
+###############################################################################
+current_design simple_por
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name __VIRTUAL_CLK__ -period 10.0000 
+set_clock_uncertainty 0.2500 __VIRTUAL_CLK__
+###############################################################################
+# Environment
+###############################################################################
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_fanout 5.0000 [current_design]
--- a/sdc/xres_buf.sdc
+++ b/sdc/xres_buf.sdc
@ -0,0 +1,17 @@
+current_design xres_buf
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name __VIRTUAL_CLK__ -period 10.0000 
+set_clock_uncertainty 0.2500 __VIRTUAL_CLK__
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {X}]
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {X}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_fanout 5.0000 [current_design]
--- a/sdf/caravel_clocking.sdf
+++ b/sdf/caravel_clocking.sdf
--- a/sdf/chip_io.sdf
+++ b/sdf/chip_io.sdf
@ -0,0 +1,21 @@
+(DELAYFILE
+ (SDFVERSION "3.0")
+ (DESIGN "chip_io")
+ (DATE "Wed Dec  1 18:01:36 2021")
+ (VENDOR "Parallax")
+ (PROGRAM "STA")
+ (VERSION "2.3.0")
+ (DIVIDER /)
+ (VOLTAGE 1.800::1.800)
+ (PROCESS "1.000::1.000")
+ (TEMPERATURE 25.000::25.000)
+ (TIMESCALE 1ns)
+ (CELL
+  (CELLTYPE "chip_io")
+  (INSTANCE)
+  (DELAY
+   (ABSOLUTE
+   )
+  )
+ )
+)
--- a/sdf/gpio_control_block.sdf
+++ b/sdf/gpio_control_block.sdf
--- a/sdf/mgmt_protect.sdf
+++ b/sdf/mgmt_protect.sdf
@ -1,7 +1,7 @@
 (DELAYFILE
 (SDFVERSION "3.0")
 (DESIGN "mgmt_protect")
- (DATE "Sun Nov 28 13:25:24 2021")
+ (DATE "Tue Nov 30 17:41:08 2021")
 (VENDOR "Parallax")
 (PROGRAM "STA")
 (VERSION "2.3.0")
--- a/sdf/mgmt_protect_hv.sdf
+++ b/sdf/mgmt_protect_hv.sdf
@ -0,0 +1,25 @@
+(DELAYFILE
+ (SDFVERSION "3.0")
+ (DESIGN "mgmt_protect_hv")
+ (DATE "Tue Nov 30 17:37:28 2021")
+ (VENDOR "Parallax")
+ (PROGRAM "STA")
+ (VERSION "2.3.0")
+ (DIVIDER /)
+ (VOLTAGE 1.800::1.800)
+ (PROCESS "1.000::1.000")
+ (TEMPERATURE 25.000::25.000)
+ (TIMESCALE 1ns)
+ (CELL
+  (CELLTYPE "mgmt_protect_hv")
+  (INSTANCE)
+  (DELAY
+   (ABSOLUTE
+    (INTERCONNECT mprj2_logic_high_hvl/HI mprj2_logic_high_lv/A (0.000::0.000))
+    (INTERCONNECT mprj2_logic_high_lv/X mprj2_vdd_logic1 (0.000::0.000))
+    (INTERCONNECT mprj_logic_high_hvl/HI mprj_logic_high_lv/A (0.000::0.000))
+    (INTERCONNECT mprj_logic_high_lv/X mprj_vdd_logic1 (0.000::0.000))
+   )
+  )
+ )
+)
--- a/sdf/xres_buf.sdf
+++ b/sdf/xres_buf.sdf
@ -0,0 +1,24 @@
+(DELAYFILE
+ (SDFVERSION "3.0")
+ (DESIGN "xres_buf")
+ (DATE "Tue Nov 30 15:47:21 2021")
+ (VENDOR "Parallax")
+ (PROGRAM "STA")
+ (VERSION "2.3.0")
+ (DIVIDER /)
+ (VOLTAGE 1.800::1.800)
+ (PROCESS "1.000::1.000")
+ (TEMPERATURE 25.000::25.000)
+ (TIMESCALE 1ns)
+ (CELL
+  (CELLTYPE "xres_buf")
+  (INSTANCE)
+  (DELAY
+   (ABSOLUTE
+    (INTERCONNECT A lvlshiftdown/A (0.000::0.000))
+    (INTERCONNECT A ANTENNA_lvlshiftdown_A/DIODE (0.000::0.000))
+    (INTERCONNECT lvlshiftdown/X X (0.001::0.001))
+   )
+  )
+ )
+)
--- a/signoff/caravel_clocking/OPENLANE_VERSION
+++ b/signoff/caravel_clocking/OPENLANE_VERSION
@ -1 +1 @@
-openlane 2021.11.23_01.42.34-9-gc3ec957
+openlane 2021.11.23_01.42.34-10-g445acc6
--- a/signoff/caravel_clocking/final_summary_report.csv
+++ b/signoff/caravel_clocking/final_summary_report.csv
@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/home/ma/ef/caravel_openframe/openlane/caravel_clocking,caravel_clocking,caravel_clocking,flow completed,0h1m51s0ms,0h1m36s0ms,90000.0,0.006,45000.0,68.96,668.83,270,0,0,0,0,0,0,0,0,0,0,-1,5326,1956,0.0,0.0,-1,-0.06,-1,0.0,0.0,-1,-0.15,-1,3312107.0,0.0,31.15,16.61,4.43,0.0,0.0,202,252,67,117,0,0,0,200,0,0,0,0,0,0,0,4,73,74,6,40,165,0,205,90.9090909090909,11.0,10.0,DELAY 0,5,50,1,15.5,16.9,0.7,0,sky130_fd_sc_hd,0,4
+0,/home/ma/ef/caravel_openframe/openlane/caravel_clocking,caravel_clocking,caravel_clocking,flow completed,0h2m8s0ms,0h1m50s0ms,89000.0,0.006,44500.0,70.54,647.01,267,0,0,0,0,0,0,0,0,0,0,-1,5503,2015,0.0,0.0,-1,-0.11,-1,0.0,0.0,-1,-0.34,-1,3392030.0,0.0,32.92,17.74,4.07,0.0,0.0,202,252,67,117,0,0,0,200,0,3,4,15,20,14,10,35,73,74,5,40,165,0,205,90.9090909090909,11.0,10.0,DELAY 0,5,50,1,15.5,16.9,0.715,0,sky130_fd_sc_hd,0,4
--- a/spef/caravel_clocking.spef
+++ b/spef/caravel_clocking.spef
--- a/spef/chip_io.spef
+++ b/spef/chip_io.spef
--- a/spef/gpio_control_block.spef
+++ b/spef/gpio_control_block.spef
--- a/spef/gpio_defaults_block_0403.spef
+++ b/spef/gpio_defaults_block_0403.spef
@ -0,0 +1,273 @@
+*SPEF "ieee 1481-1999"
+*DESIGN "gpio_defaults_block_0403"
+*DATE "11:11:11 Fri 11 11, 1111"
+*VENDOR "OpenRCX"
+*PROGRAM "Parallel Extraction"
+*VERSION "1.0"
+*DESIGN_FLOW "NAME_SCOPE LOCAL" "PIN_CAP NONE"
+*DIVIDER /
+*DELIMITER :
+*BUS_DELIMITER []
+*T_UNIT 1 NS
+*C_UNIT 1 PF
+*R_UNIT 1 OHM
+*L_UNIT 1 HENRY
+
+*NAME_MAP
+*3 gpio_defaults_low\[0\]
+*4 gpio_defaults_high\[10\]
+*5 gpio_defaults_low\[11\]
+*6 gpio_defaults_low\[12\]
+*7 gpio_defaults_high\[1\]
+*8 gpio_defaults_low\[2\]
+*9 gpio_defaults_low\[3\]
+*10 gpio_defaults_low\[4\]
+*11 gpio_defaults_low\[5\]
+*12 gpio_defaults_low\[6\]
+*13 gpio_defaults_low\[7\]
+*14 gpio_defaults_low\[8\]
+*15 gpio_defaults_low\[9\]
+*16 gpio_defaults_high\[0\]
+*17 gpio_defaults_high\[11\]
+*18 gpio_defaults_high\[12\]
+*19 gpio_defaults_high\[2\]
+*20 gpio_defaults_high\[3\]
+*21 gpio_defaults_high\[4\]
+*22 gpio_defaults_high\[5\]
+*23 gpio_defaults_high\[6\]
+*24 gpio_defaults_high\[7\]
+*25 gpio_defaults_high\[8\]
+*26 gpio_defaults_high\[9\]
+*27 gpio_defaults_low\[10\]
+*28 gpio_defaults_low\[1\]
+*29 FILLER_0_29
+*30 FILLER_0_3
+*31 FILLER_0_33
+*32 FILLER_0_38
+*33 FILLER_0_43
+*34 FILLER_0_48
+*35 FILLER_0_55
+*36 FILLER_0_60
+*37 FILLER_0_9
+*38 FILLER_1_15
+*39 FILLER_1_27
+*40 FILLER_1_3
+*41 FILLER_1_39
+*42 FILLER_1_51
+*43 FILLER_1_55
+*44 FILLER_1_57
+*45 FILLER_1_61
+*46 FILLER_2_15
+*47 FILLER_2_27
+*48 FILLER_2_29
+*49 FILLER_2_3
+*50 FILLER_2_41
+*51 FILLER_2_53
+*52 FILLER_2_57
+*53 FILLER_2_61
+*54 PHY_0
+*55 PHY_1
+*56 PHY_2
+*57 PHY_3
+*58 PHY_4
+*59 PHY_5
+*60 TAP_10
+*61 TAP_6
+*62 TAP_7
+*63 TAP_8
+*64 TAP_9
+*65 gpio_default_value\[0\]
+*66 gpio_default_value\[10\]
+*67 gpio_default_value\[11\]
+*68 gpio_default_value\[12\]
+*69 gpio_default_value\[1\]
+*70 gpio_default_value\[2\]
+*71 gpio_default_value\[3\]
+*72 gpio_default_value\[4\]
+*73 gpio_default_value\[5\]
+*74 gpio_default_value\[6\]
+*75 gpio_default_value\[7\]
+*76 gpio_default_value\[8\]
+*77 gpio_default_value\[9\]
+
+*PORTS
+gpio_defaults[0] O
+gpio_defaults[10] O
+gpio_defaults[11] O
+gpio_defaults[12] O
+gpio_defaults[1] O
+gpio_defaults[2] O
+gpio_defaults[3] O
+gpio_defaults[4] O
+gpio_defaults[5] O
+gpio_defaults[6] O
+gpio_defaults[7] O
+gpio_defaults[8] O
+gpio_defaults[9] O
+
+*D_NET *3 0.000662868
+*CONN
+*P gpio_defaults[0] O
+*I *65:LO O *D sky130_fd_sc_hd__conb_1
+*CAP
+1 gpio_defaults[0] 0.000295589
+2 *65:LO 0.000295589
+3 gpio_defaults[0] gpio_defaults[1] 7.16893e-05
+*RES
+1 *65:LO gpio_defaults[0] 21.1394 
+*END
+
+*D_NET *4 0.000169932
+*CONN
+*P gpio_defaults[10] O
+*I *66:HI O *D sky130_fd_sc_hd__conb_1
+*CAP
+1 gpio_defaults[10] 8.49658e-05
+2 *66:HI 8.49658e-05
+3 gpio_defaults[10] gpio_defaults[11] 0
+4 gpio_defaults[10] gpio_defaults[9] 0
+*RES
+1 *66:HI gpio_defaults[10] 15.7033 
+*END
+
+*D_NET *5 0.000230895
+*CONN
+*P gpio_defaults[11] O
+*I *67:LO O *D sky130_fd_sc_hd__conb_1
+*CAP
+1 gpio_defaults[11] 0.000115448
+2 *67:LO 0.000115448
+3 gpio_defaults[11] gpio_defaults[12] 0
+4 gpio_defaults[10] gpio_defaults[11] 0
+*RES
+1 *67:LO gpio_defaults[11] 16.5338 
+*END
+
+*D_NET *6 0.000822209
+*CONN
+*P gpio_defaults[12] O
+*I *68:LO O *D sky130_fd_sc_hd__conb_1
+*CAP
+1 gpio_defaults[12] 0.000411104
+2 *68:LO 0.000411104
+3 gpio_defaults[11] gpio_defaults[12] 0
+*RES
+1 *68:LO gpio_defaults[12] 23.2185 
+*END
+
+*D_NET *7 0.00071336
+*CONN
+*P gpio_defaults[1] O
+*I *69:HI O *D sky130_fd_sc_hd__conb_1
+*CAP
+1 gpio_defaults[1] 0.000307544
+2 *69:HI 0.000307544
+3 gpio_defaults[1] gpio_defaults[2] 2.65831e-05
+4 gpio_defaults[0] gpio_defaults[1] 7.16893e-05
+*RES
+1 *69:HI gpio_defaults[1] 19.1997 
+*END
+
+*D_NET *8 0.000464143
+*CONN
+*P gpio_defaults[2] O
+*I *70:LO O *D sky130_fd_sc_hd__conb_1
+*CAP
+1 gpio_defaults[2] 0.00021878
+2 *70:LO 0.00021878
+3 gpio_defaults[2] gpio_defaults[3] 0
+4 gpio_defaults[1] gpio_defaults[2] 2.65831e-05
+*RES
+1 *70:LO gpio_defaults[2] 18.921 
+*END
+
+*D_NET *9 0.000363376
+*CONN
+*P gpio_defaults[3] O
+*I *71:LO O *D sky130_fd_sc_hd__conb_1
+*CAP
+1 gpio_defaults[3] 0.000181688
+2 *71:LO 0.000181688
+3 gpio_defaults[3] gpio_defaults[4] 0
+4 gpio_defaults[2] gpio_defaults[3] 0
+*RES
+1 *71:LO gpio_defaults[3] 17.8118 
+*END
+
+*D_NET *10 0.000236028
+*CONN
+*P gpio_defaults[4] O
+*I *72:LO O *D sky130_fd_sc_hd__conb_1
+*CAP
+1 gpio_defaults[4] 0.000118014
+2 *72:LO 0.000118014
+3 gpio_defaults[4] gpio_defaults[5] 0
+4 gpio_defaults[3] gpio_defaults[4] 0
+*RES
+1 *72:LO gpio_defaults[4] 16.5338 
+*END
+
+*D_NET *11 0.000230895
+*CONN
+*P gpio_defaults[5] O
+*I *73:LO O *D sky130_fd_sc_hd__conb_1
+*CAP
+1 gpio_defaults[5] 0.000115448
+2 *73:LO 0.000115448
+3 gpio_defaults[5] gpio_defaults[6] 0
+4 gpio_defaults[4] gpio_defaults[5] 0
+*RES
+1 *73:LO gpio_defaults[5] 16.5338 
+*END
+
+*D_NET *12 0.000230895
+*CONN
+*P gpio_defaults[6] O
+*I *74:LO O *D sky130_fd_sc_hd__conb_1
+*CAP
+1 gpio_defaults[6] 0.000115448
+2 *74:LO 0.000115448
+3 gpio_defaults[6] gpio_defaults[7] 0
+4 gpio_defaults[5] gpio_defaults[6] 0
+*RES
+1 *74:LO gpio_defaults[6] 16.5338 
+*END
+
+*D_NET *13 0.00022764
+*CONN
+*P gpio_defaults[7] O
+*I *75:LO O *D sky130_fd_sc_hd__conb_1
+*CAP
+1 gpio_defaults[7] 0.00011382
+2 *75:LO 0.00011382
+3 gpio_defaults[7] gpio_defaults[8] 0
+4 gpio_defaults[6] gpio_defaults[7] 0
+*RES
+1 *75:LO gpio_defaults[7] 16.5338 
+*END
+
+*D_NET *14 0.000224385
+*CONN
+*P gpio_defaults[8] O
+*I *76:LO O *D sky130_fd_sc_hd__conb_1
+*CAP
+1 gpio_defaults[8] 0.000112192
+2 *76:LO 0.000112192
+3 gpio_defaults[8] gpio_defaults[9] 0
+4 gpio_defaults[7] gpio_defaults[8] 0
+*RES
+1 *76:LO gpio_defaults[8] 16.5338 
+*END
+
+*D_NET *15 0.00022764
+*CONN
+*P gpio_defaults[9] O
+*I *77:LO O *D sky130_fd_sc_hd__conb_1
+*CAP
+1 gpio_defaults[9] 0.00011382
+2 *77:LO 0.00011382
+3 gpio_defaults[10] gpio_defaults[9] 0
+4 gpio_defaults[8] gpio_defaults[9] 0
+*RES
+1 *77:LO gpio_defaults[9] 16.5338 
+*END
--- a/spef/gpio_defaults_block_1803.spef
+++ b/spef/gpio_defaults_block_1803.spef
@ -0,0 +1,273 @@
+*SPEF "ieee 1481-1999"
+*DESIGN "gpio_defaults_block_1803"
+*DATE "11:11:11 Fri 11 11, 1111"
+*VENDOR "OpenRCX"
+*PROGRAM "Parallel Extraction"
+*VERSION "1.0"
+*DESIGN_FLOW "NAME_SCOPE LOCAL" "PIN_CAP NONE"
+*DIVIDER /
+*DELIMITER :
+*BUS_DELIMITER []
+*T_UNIT 1 NS
+*C_UNIT 1 PF
+*R_UNIT 1 OHM
+*L_UNIT 1 HENRY
+
+*NAME_MAP
+*3 gpio_defaults_low\[0\]
+*4 gpio_defaults_high\[10\]
+*5 gpio_defaults_low\[11\]
+*6 gpio_defaults_low\[12\]
+*7 gpio_defaults_high\[1\]
+*8 gpio_defaults_low\[2\]
+*9 gpio_defaults_low\[3\]
+*10 gpio_defaults_low\[4\]
+*11 gpio_defaults_low\[5\]
+*12 gpio_defaults_low\[6\]
+*13 gpio_defaults_low\[7\]
+*14 gpio_defaults_low\[8\]
+*15 gpio_defaults_low\[9\]
+*16 gpio_defaults_high\[0\]
+*17 gpio_defaults_high\[11\]
+*18 gpio_defaults_high\[12\]
+*19 gpio_defaults_high\[2\]
+*20 gpio_defaults_high\[3\]
+*21 gpio_defaults_high\[4\]
+*22 gpio_defaults_high\[5\]
+*23 gpio_defaults_high\[6\]
+*24 gpio_defaults_high\[7\]
+*25 gpio_defaults_high\[8\]
+*26 gpio_defaults_high\[9\]
+*27 gpio_defaults_low\[10\]
+*28 gpio_defaults_low\[1\]
+*29 FILLER_0_29
+*30 FILLER_0_3
+*31 FILLER_0_33
+*32 FILLER_0_38
+*33 FILLER_0_43
+*34 FILLER_0_48
+*35 FILLER_0_55
+*36 FILLER_0_60
+*37 FILLER_0_9
+*38 FILLER_1_15
+*39 FILLER_1_27
+*40 FILLER_1_3
+*41 FILLER_1_39
+*42 FILLER_1_51
+*43 FILLER_1_55
+*44 FILLER_1_57
+*45 FILLER_1_61
+*46 FILLER_2_15
+*47 FILLER_2_27
+*48 FILLER_2_29
+*49 FILLER_2_3
+*50 FILLER_2_41
+*51 FILLER_2_53
+*52 FILLER_2_57
+*53 FILLER_2_61
+*54 PHY_0
+*55 PHY_1
+*56 PHY_2
+*57 PHY_3
+*58 PHY_4
+*59 PHY_5
+*60 TAP_10
+*61 TAP_6
+*62 TAP_7
+*63 TAP_8
+*64 TAP_9
+*65 gpio_default_value\[0\]
+*66 gpio_default_value\[10\]
+*67 gpio_default_value\[11\]
+*68 gpio_default_value\[12\]
+*69 gpio_default_value\[1\]
+*70 gpio_default_value\[2\]
+*71 gpio_default_value\[3\]
+*72 gpio_default_value\[4\]
+*73 gpio_default_value\[5\]
+*74 gpio_default_value\[6\]
+*75 gpio_default_value\[7\]
+*76 gpio_default_value\[8\]
+*77 gpio_default_value\[9\]
+
+*PORTS
+gpio_defaults[0] O
+gpio_defaults[10] O
+gpio_defaults[11] O
+gpio_defaults[12] O
+gpio_defaults[1] O
+gpio_defaults[2] O
+gpio_defaults[3] O
+gpio_defaults[4] O
+gpio_defaults[5] O
+gpio_defaults[6] O
+gpio_defaults[7] O
+gpio_defaults[8] O
+gpio_defaults[9] O
+
+*D_NET *3 0.000662868
+*CONN
+*P gpio_defaults[0] O
+*I *65:LO O *D sky130_fd_sc_hd__conb_1
+*CAP
+1 gpio_defaults[0] 0.000295589
+2 *65:LO 0.000295589
+3 gpio_defaults[0] gpio_defaults[1] 7.16893e-05
+*RES
+1 *65:LO gpio_defaults[0] 21.1394 
+*END
+
+*D_NET *4 0.000169932
+*CONN
+*P gpio_defaults[10] O
+*I *66:HI O *D sky130_fd_sc_hd__conb_1
+*CAP
+1 gpio_defaults[10] 8.49658e-05
+2 *66:HI 8.49658e-05
+3 gpio_defaults[10] gpio_defaults[11] 0
+4 gpio_defaults[10] gpio_defaults[9] 0
+*RES
+1 *66:HI gpio_defaults[10] 15.7033 
+*END
+
+*D_NET *5 0.000230895
+*CONN
+*P gpio_defaults[11] O
+*I *67:LO O *D sky130_fd_sc_hd__conb_1
+*CAP
+1 gpio_defaults[11] 0.000115448
+2 *67:LO 0.000115448
+3 gpio_defaults[11] gpio_defaults[12] 0
+4 gpio_defaults[10] gpio_defaults[11] 0
+*RES
+1 *67:LO gpio_defaults[11] 16.5338 
+*END
+
+*D_NET *6 0.000822209
+*CONN
+*P gpio_defaults[12] O
+*I *68:LO O *D sky130_fd_sc_hd__conb_1
+*CAP
+1 gpio_defaults[12] 0.000411104
+2 *68:LO 0.000411104
+3 gpio_defaults[11] gpio_defaults[12] 0
+*RES
+1 *68:LO gpio_defaults[12] 23.2185 
+*END
+
+*D_NET *7 0.00071336
+*CONN
+*P gpio_defaults[1] O
+*I *69:HI O *D sky130_fd_sc_hd__conb_1
+*CAP
+1 gpio_defaults[1] 0.000307544
+2 *69:HI 0.000307544
+3 gpio_defaults[1] gpio_defaults[2] 2.65831e-05
+4 gpio_defaults[0] gpio_defaults[1] 7.16893e-05
+*RES
+1 *69:HI gpio_defaults[1] 19.1997 
+*END
+
+*D_NET *8 0.000464143
+*CONN
+*P gpio_defaults[2] O
+*I *70:LO O *D sky130_fd_sc_hd__conb_1
+*CAP
+1 gpio_defaults[2] 0.00021878
+2 *70:LO 0.00021878
+3 gpio_defaults[2] gpio_defaults[3] 0
+4 gpio_defaults[1] gpio_defaults[2] 2.65831e-05
+*RES
+1 *70:LO gpio_defaults[2] 18.921 
+*END
+
+*D_NET *9 0.000363376
+*CONN
+*P gpio_defaults[3] O
+*I *71:LO O *D sky130_fd_sc_hd__conb_1
+*CAP
+1 gpio_defaults[3] 0.000181688
+2 *71:LO 0.000181688
+3 gpio_defaults[3] gpio_defaults[4] 0
+4 gpio_defaults[2] gpio_defaults[3] 0
+*RES
+1 *71:LO gpio_defaults[3] 17.8118 
+*END
+
+*D_NET *10 0.000236028
+*CONN
+*P gpio_defaults[4] O
+*I *72:LO O *D sky130_fd_sc_hd__conb_1
+*CAP
+1 gpio_defaults[4] 0.000118014
+2 *72:LO 0.000118014
+3 gpio_defaults[4] gpio_defaults[5] 0
+4 gpio_defaults[3] gpio_defaults[4] 0
+*RES
+1 *72:LO gpio_defaults[4] 16.5338 
+*END
+
+*D_NET *11 0.000230895
+*CONN
+*P gpio_defaults[5] O
+*I *73:LO O *D sky130_fd_sc_hd__conb_1
+*CAP
+1 gpio_defaults[5] 0.000115448
+2 *73:LO 0.000115448
+3 gpio_defaults[5] gpio_defaults[6] 0
+4 gpio_defaults[4] gpio_defaults[5] 0
+*RES
+1 *73:LO gpio_defaults[5] 16.5338 
+*END
+
+*D_NET *12 0.000230895
+*CONN
+*P gpio_defaults[6] O
+*I *74:LO O *D sky130_fd_sc_hd__conb_1
+*CAP
+1 gpio_defaults[6] 0.000115448
+2 *74:LO 0.000115448
+3 gpio_defaults[6] gpio_defaults[7] 0
+4 gpio_defaults[5] gpio_defaults[6] 0
+*RES
+1 *74:LO gpio_defaults[6] 16.5338 
+*END
+
+*D_NET *13 0.00022764
+*CONN
+*P gpio_defaults[7] O
+*I *75:LO O *D sky130_fd_sc_hd__conb_1
+*CAP
+1 gpio_defaults[7] 0.00011382
+2 *75:LO 0.00011382
+3 gpio_defaults[7] gpio_defaults[8] 0
+4 gpio_defaults[6] gpio_defaults[7] 0
+*RES
+1 *75:LO gpio_defaults[7] 16.5338 
+*END
+
+*D_NET *14 0.000224385
+*CONN
+*P gpio_defaults[8] O
+*I *76:LO O *D sky130_fd_sc_hd__conb_1
+*CAP
+1 gpio_defaults[8] 0.000112192
+2 *76:LO 0.000112192
+3 gpio_defaults[8] gpio_defaults[9] 0
+4 gpio_defaults[7] gpio_defaults[8] 0
+*RES
+1 *76:LO gpio_defaults[8] 16.5338 
+*END
+
+*D_NET *15 0.00022764
+*CONN
+*P gpio_defaults[9] O
+*I *77:LO O *D sky130_fd_sc_hd__conb_1
+*CAP
+1 gpio_defaults[9] 0.00011382
+2 *77:LO 0.00011382
+3 gpio_defaults[10] gpio_defaults[9] 0
+4 gpio_defaults[8] gpio_defaults[9] 0
+*RES
+1 *77:LO gpio_defaults[9] 16.5338 
+*END
--- a/spef/mgmt_protect_hv.spef
+++ b/spef/mgmt_protect_hv.spef
@ -0,0 +1,204 @@
+*SPEF "ieee 1481-1999"
+*DESIGN "mgmt_protect_hv"
+*DATE "11:11:11 Fri 11 11, 1111"
+*VENDOR "OpenRCX"
+*PROGRAM "Parallel Extraction"
+*VERSION "1.0"
+*DESIGN_FLOW "NAME_SCOPE LOCAL" "PIN_CAP NONE"
+*DIVIDER /
+*DELIMITER :
+*BUS_DELIMITER []
+*T_UNIT 1 NS
+*C_UNIT 1 PF
+*R_UNIT 1 OHM
+*L_UNIT 1 HENRY
+
+*NAME_MAP
+*1 mprj2_vdd_logic1
+*2 mprj_vdd_logic1
+*9 mprj2_vdd_logic1_h
+*10 mprj_vdd_logic1_h
+*11 mprj2_logic_high_hvl
+*12 mprj2_logic_high_lv
+*13 mprj_logic_high_hvl
+*14 mprj_logic_high_lv
+*15 FILLER_0_0
+*16 FILLER_0_8
+*17 FILLER_0_16
+*18 FILLER_0_24
+*19 FILLER_0_32
+*20 FILLER_0_40
+*21 FILLER_0_48
+*22 FILLER_0_56
+*23 FILLER_0_64
+*24 FILLER_0_72
+*25 FILLER_0_80
+*26 FILLER_0_88
+*27 FILLER_0_96
+*28 FILLER_0_104
+*29 FILLER_0_112
+*30 FILLER_0_120
+*31 FILLER_0_128
+*32 FILLER_0_136
+*33 FILLER_0_144
+*34 FILLER_0_152
+*35 FILLER_0_160
+*36 FILLER_0_168
+*37 FILLER_0_176
+*38 FILLER_0_184
+*39 FILLER_0_192
+*40 FILLER_0_200
+*41 FILLER_0_208
+*42 FILLER_0_216
+*43 FILLER_0_224
+*44 FILLER_0_232
+*45 FILLER_0_240
+*46 FILLER_0_248
+*47 FILLER_0_256
+*48 FILLER_0_264
+*49 FILLER_0_272
+*50 FILLER_0_280
+*51 FILLER_0_288
+*52 FILLER_0_296
+*53 FILLER_0_300
+*54 FILLER_1_0
+*55 FILLER_1_8
+*56 FILLER_1_16
+*57 FILLER_1_24
+*58 FILLER_1_32
+*59 FILLER_1_40
+*60 FILLER_1_48
+*61 FILLER_1_56
+*62 FILLER_1_64
+*63 FILLER_1_72
+*64 FILLER_1_80
+*65 FILLER_1_88
+*66 FILLER_1_92
+*67 FILLER_1_94
+*68 FILLER_1_117
+*69 FILLER_1_125
+*70 FILLER_1_133
+*71 FILLER_1_141
+*72 FILLER_1_149
+*73 FILLER_1_157
+*74 FILLER_1_165
+*75 FILLER_1_189
+*76 FILLER_1_197
+*77 FILLER_1_205
+*78 FILLER_1_213
+*79 FILLER_1_221
+*80 FILLER_1_229
+*81 FILLER_1_237
+*82 FILLER_1_245
+*83 FILLER_1_253
+*84 FILLER_1_261
+*85 FILLER_1_269
+*86 FILLER_1_277
+*87 FILLER_1_285
+*88 FILLER_1_293
+*89 FILLER_1_301
+*90 FILLER_2_0
+*91 FILLER_2_8
+*92 FILLER_2_16
+*93 FILLER_2_24
+*94 FILLER_2_32
+*95 FILLER_2_40
+*96 FILLER_2_48
+*97 FILLER_2_56
+*98 FILLER_2_64
+*99 FILLER_2_72
+*100 FILLER_2_80
+*101 FILLER_2_88
+*102 FILLER_2_96
+*103 FILLER_2_117
+*104 FILLER_2_125
+*105 FILLER_2_133
+*106 FILLER_2_141
+*107 FILLER_2_149
+*108 FILLER_2_157
+*109 FILLER_2_165
+*110 FILLER_2_169
+*111 FILLER_2_171
+*112 FILLER_2_189
+*113 FILLER_2_197
+*114 FILLER_2_205
+*115 FILLER_2_213
+*116 FILLER_2_221
+*117 FILLER_2_229
+*118 FILLER_2_237
+*119 FILLER_2_245
+*120 FILLER_2_253
+*121 FILLER_2_261
+*122 FILLER_2_269
+*123 FILLER_2_277
+*124 FILLER_2_285
+*125 FILLER_2_293
+*126 FILLER_2_301
+
+*PORTS
+mprj2_vdd_logic1 O
+mprj_vdd_logic1 O
+
+*D_NET *1 0.00894054
+*CONN
+*P mprj2_vdd_logic1 O
+*I *12:X O *D sky130_fd_sc_hvl__lsbufhv2lv_1
+*CAP
+1 mprj2_vdd_logic1 0.000164685
+2 *12:X 0.000136495
+3 *1:9 0.00433377
+4 *1:8 0.00430558
+5 *1:9 *2:5 0
+*RES
+1 *12:X *1:8 21.1315 
+2 *1:8 *1:9 104.917 
+3 *1:9 mprj2_vdd_logic1 10.6698 
+*END
+
+*D_NET *2 0.005901
+*CONN
+*P mprj_vdd_logic1 O
+*I *14:X O *D sky130_fd_sc_hvl__lsbufhv2lv_1
+*CAP
+1 mprj_vdd_logic1 0.000279428
+2 *14:X 0
+3 *2:5 0.00291451
+4 *2:4 0.00263509
+5 *2:5 *9:7 7.19686e-05
+6 *1:9 *2:5 0
+*RES
+1 *14:X *2:4 9.24915 
+2 *2:4 *2:5 63.2489 
+3 *2:5 mprj_vdd_logic1 14.285 
+*END
+
+*D_NET *9 0.00401189
+*CONN
+*I *12:A I *D sky130_fd_sc_hvl__lsbufhv2lv_1
+*I *11:HI O *D sky130_fd_sc_hvl__conb_1
+*CAP
+1 *12:A 0.000185088
+2 *11:HI 0
+3 *9:7 0.00194467
+4 *9:4 0.00175958
+5 *12:A *10:8 5.05783e-05
+6 *2:5 *9:7 7.19686e-05
+*RES
+1 *11:HI *9:4 9.24915 
+2 *9:4 *9:7 47.4938 
+3 *9:7 *12:A 17.9577 
+*END
+
+*D_NET *10 0.00370034
+*CONN
+*I *14:A I *D sky130_fd_sc_hvl__lsbufhv2lv_1
+*I *13:HI O *D sky130_fd_sc_hvl__conb_1
+*CAP
+1 *14:A 0.00172779
+2 *13:HI 9.70922e-05
+3 *10:8 0.00182488
+4 *12:A *10:8 5.05783e-05
+*RES
+1 *13:HI *10:8 20.6796 
+2 *10:8 *14:A 48.192 
+*END
--- a/spef/xres_buf.spef
+++ b/spef/xres_buf.spef
@ -0,0 +1,65 @@
+*SPEF "ieee 1481-1999"
+*DESIGN "xres_buf"
+*DATE "11:11:11 Fri 11 11, 1111"
+*VENDOR "OpenRCX"
+*PROGRAM "Parallel Extraction"
+*VERSION "1.0"
+*DESIGN_FLOW "NAME_SCOPE LOCAL" "PIN_CAP NONE"
+*DIVIDER /
+*DELIMITER :
+*BUS_DELIMITER []
+*T_UNIT 1 NS
+*C_UNIT 1 PF
+*R_UNIT 1 OHM
+*L_UNIT 1 HENRY
+
+*NAME_MAP
+*1 A
+*2 X
+*3 lvlshiftdown
+*4 ANTENNA_lvlshiftdown_A
+*5 FILLER_0_0
+*6 FILLER_0_8
+*7 FILLER_0_16
+*8 FILLER_0_24
+*9 FILLER_0_28
+*10 FILLER_0_30
+*11 FILLER_1_0
+*12 FILLER_1_8
+*13 FILLER_1_12
+*14 FILLER_1_30
+*15 FILLER_2_0
+*16 FILLER_2_8
+*17 FILLER_2_10
+*18 FILLER_2_30
+
+*PORTS
+A I
+X O
+
+*D_NET *1 0.000990495
+*CONN
+*P A I
+*I *3:A I *D sky130_fd_sc_hvl__lsbufhv2lv_1
+*I *4:DIODE I *D sky130_fd_sc_hvl__diode_2
+*CAP
+1 A 0.000411399
+2 *3:A 0
+3 *4:DIODE 8.38483e-05
+4 *1:12 0.000495247
+*RES
+1 A *1:12 14.3355 
+2 *1:12 *4:DIODE 11.1541 
+3 *1:12 *3:A 9.24915 
+*END
+
+*D_NET *2 0.00147572
+*CONN
+*P X O
+*I *3:X O *D sky130_fd_sc_hvl__lsbufhv2lv_1
+*CAP
+1 X 0.00073786
+2 *3:X 0.00073786
+*RES
+1 *3:X X 32.9072 
+*END
--- a/spi/lvs/caravel_clocking.spice
+++ b/spi/lvs/caravel_clocking.spice
--- a/verilog/gl/caravel_clocking.v
+++ b/verilog/gl/caravel_clocking.v