mirror of https://github.com/efabless/caravel.git
Merge branch 'main' of https://github.com/efabless/caravel_openframe into main
This commit is contained in:
manarabdelaty
commit
00c845525a
1167
mag/caravan.mag
1167
mag/caravan.mag
File diff suppressed because it is too large
Load Diff
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@ -1,7 +1,7 @@
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|||
magic
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||||
tech sky130A
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||||
magscale 1 2
|
||||
timestamp 1637791793
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||||
timestamp 1638483672
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||||
<< error_p >>
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<< metal5 >>
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<< comment >>
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||||
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|
@ -1826,8 +1787,6 @@ flabel metal5 664092 267180 666518 267904 0 FreeSans 3200 0 0 0 vssa1_core
|
|||
flabel metal5 667280 263142 669706 263866 0 FreeSans 3200 0 0 0 vdda1_core
|
||||
flabel metal5 634330 96284 638114 98514 0 FreeSans 16000 0 0 0 vssd_core
|
||||
flabel metal5 633452 78554 637236 80784 0 FreeSans 16000 0 0 0 vccd_core
|
||||
flabel metal5 206106 18628 207168 19326 0 FreeSans 4800 0 0 0 vccd_core
|
||||
flabel metal5 206018 17180 207080 17878 0 FreeSans 4800 0 0 0 vssd_core
|
||||
flabel metal5 182024 250550 190042 253308 0 FreeSans 16000 0 0 0 vssd1_core
|
||||
flabel metal5 182160 246638 190178 249396 0 FreeSans 16000 0 0 0 vccd1_core
|
||||
flabel metal5 181852 266620 189870 269378 0 FreeSans 16000 0 0 0 vssa1_core
|
||||
|
|
@ -1838,4 +1797,6 @@ flabel metal5 621512 258708 630212 261250 0 FreeSans 16000 0 0 0 vssa2_core
|
|||
flabel metal5 621598 254668 630298 257210 0 FreeSans 16000 0 0 0 vdda2_core
|
||||
flabel metal5 621936 242776 630636 245318 0 FreeSans 16000 0 0 0 vssd2_core
|
||||
flabel metal5 621794 238736 630494 241278 0 FreeSans 16000 0 0 0 vccd2_core
|
||||
flabel metal5 621956 75300 623018 75998 0 FreeSans 4800 0 0 0 vssd_core
|
||||
flabel metal5 639514 76786 640576 77484 0 FreeSans 4800 0 0 0 vccd_core
|
||||
<< end >>
|
||||
|
|
|
|||
1074
mag/caravel.mag
1074
mag/caravel.mag
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@ -1,7 +1,7 @@
|
|||
magic
|
||||
tech sky130A
|
||||
magscale 1 2
|
||||
timestamp 1636495793
|
||||
timestamp 1638586901
|
||||
<< metal4 >>
|
||||
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||||
<< metal5 >>
|
||||
|
|
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|
||||
tri 5490 14420 5630 14560 se
|
||||
rect 5630 14490 7140 14630
|
||||
tri 7140 14490 7280 14630 nw
|
||||
rect 5670 14420 5950 14490
|
||||
rect 5630 14420 5950 14490
|
||||
tri 5950 14420 6020 14490 nw
|
||||
rect 5040 14210 5950 14420
|
||||
rect 7840 14350 8190 14840
|
||||
|
|
@ -45,19 +45,21 @@ tri 9380 11900 9660 12180 sw
|
|||
rect 5880 11760 7280 11900
|
||||
tri 7280 11760 7420 11900 nw
|
||||
rect 7840 11760 9660 11900
|
||||
rect 5880 11620 6650 11760
|
||||
rect 5880 11622 6792 11760
|
||||
tri 6792 11622 6930 11760 nw
|
||||
rect 5880 11620 6713 11622
|
||||
rect 2380 11200 3500 11620
|
||||
tri 2380 11060 2520 11200 ne
|
||||
rect 2520 10780 3360 11200
|
||||
tri 3360 11060 3500 11200 nw
|
||||
tri 5880 11107 6393 11620 ne
|
||||
rect 6393 11107 6650 11620
|
||||
tri 6650 11480 6930 11760 nw
|
||||
rect 6393 11107 6713 11620
|
||||
tri 6713 11543 6792 11622 nw
|
||||
rect 7840 10990 8260 11760
|
||||
tri 8960 11480 9240 11760 ne
|
||||
rect 9240 11480 9660 11760
|
||||
tri 13580 11620 14000 12040 se
|
||||
rect 14000 11620 14280 12040
|
||||
rect 14000 11620 14320 12040
|
||||
tri 13160 11200 13580 11620 se
|
||||
rect 7840 10920 10640 10990
|
||||
tri 7280 10780 7420 10920 se
|
||||
|
|
@ -132,20 +134,21 @@ tri 2380 6580 2520 6720 ne
|
|||
rect 2520 6580 13160 6720
|
||||
rect 560 6440 1400 6580
|
||||
rect -980 6300 -140 6440
|
||||
tri -700 6160 -560 6300 ne
|
||||
rect -560 6160 -140 6300
|
||||
tri -700 6120 -520 6300 ne
|
||||
rect -520 6160 -140 6300
|
||||
tri -140 6160 140 6440 sw
|
||||
rect 700 6160 1400 6440
|
||||
tri 1400 6300 1680 6580 nw
|
||||
rect 2800 6440 13160 6580
|
||||
tri -420 5880 -140 6160 ne
|
||||
rect -140 6090 280 6160
|
||||
rect -520 6120 280 6160
|
||||
tri -380 5840 -100 6120 ne
|
||||
rect -100 6090 280 6120
|
||||
tri 280 6090 350 6160 sw
|
||||
rect 700 6090 1330 6160
|
||||
tri 1330 6090 1400 6160 nw
|
||||
rect -140 5880 1330 6090
|
||||
tri 0 5740 140 5880 ne
|
||||
rect 140 5740 1330 5880
|
||||
rect -100 5840 1330 6090
|
||||
tri 40 5740 140 5840 ne
|
||||
rect 140 5740 1330 5840
|
||||
tri 280 5600 420 5740 ne
|
||||
rect 420 5600 2160 5740
|
||||
tri 560 5460 700 5600 ne
|
||||
|
|
@ -162,9 +165,9 @@ tri 10500 5880 10640 6020 nw
|
|||
rect 4060 5740 10080 5880
|
||||
tri 10080 5740 10220 5880 nw
|
||||
tri 4060 5180 4620 5740 ne
|
||||
rect 4620 5320 10080 5740
|
||||
tri 10080 5320 10360 5600 sw
|
||||
rect 4620 5180 10360 5320
|
||||
rect 4620 5220 10080 5740
|
||||
tri 10080 5220 10360 5500 sw
|
||||
rect 4620 5180 10360 5220
|
||||
rect 980 5040 3220 5180
|
||||
tri 3220 5040 3360 5180 sw
|
||||
rect 4620 5040 7140 5180
|
||||
|
|
@ -203,8 +206,8 @@ rect 11340 4480 11760 6020
|
|||
tri 12180 5880 12320 6020 ne
|
||||
rect 12320 5880 13160 6020
|
||||
tri 13160 5880 13440 6160 sw
|
||||
tri 12600 5320 13160 5880 ne
|
||||
rect 13160 5320 13440 5880
|
||||
tri 12560 5320 13120 5880 ne
|
||||
rect 13120 5320 13440 5880
|
||||
tri 12460 4620 12740 4900 se
|
||||
rect 12740 4760 14000 4900
|
||||
tri 14000 4760 14140 4900 sw
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
magic
|
||||
tech sky130A
|
||||
magscale 1 2
|
||||
timestamp 1637790566
|
||||
timestamp 1638492834
|
||||
<< error_p >>
|
||||
rect 111554 1006757 112632 1006758
|
||||
rect 111554 1006005 111555 1006757
|
||||
|
|
@ -789,10 +789,6 @@ rect 679466 134863 680228 134864
|
|||
rect 679466 133781 679467 134863
|
||||
rect 680227 133781 680228 134863
|
||||
rect 679466 133780 680228 133781
|
||||
rect 234842 38177 237788 38178
|
||||
rect 234842 37337 234843 38177
|
||||
rect 237787 37337 237788 38177
|
||||
rect 234842 37336 237788 37337
|
||||
rect 149632 35995 150436 35996
|
||||
rect 149632 35167 149633 35995
|
||||
rect 150435 35167 150436 35995
|
||||
|
|
@ -805,10 +801,6 @@ rect 642026 33989 642027 34759
|
|||
rect 643633 33989 643634 34759
|
||||
rect 642026 33988 643634 33989
|
||||
rect 148098 33958 148902 33959
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||||
rect 204996 31645 207928 31646
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||||
rect 204996 30787 204997 31645
|
||||
rect 207927 30787 207928 31645
|
||||
rect 204996 30786 207928 30787
|
||||
<< error_s >>
|
||||
rect 41068 950418 41092 951330
|
||||
rect 43500 950418 43524 951330
|
||||
|
|
@ -1418,17 +1410,9 @@ rect 643660 42198 643694 43988
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|||
rect 149600 35166 149632 35996
|
||||
rect 150436 35166 150458 35996
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rect 149600 35114 150458 35166
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rect 234814 38178 237814 38242
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rect 237788 37336 237814 38178
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rect 148068 33958 148098 34788
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||||
rect 148902 33958 148926 34788
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rect 148068 33900 148926 33958
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rect 204958 31646 207958 31734
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rect 204958 30786 204996 31646
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rect 207928 30786 207958 31646
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rect 204958 18004 207958 30786
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||||
rect 234814 19380 237814 37336
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||||
rect 641954 34760 643694 42198
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||||
rect 653462 42634 653578 45026
|
||||
rect 656772 42634 656910 45026
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||||
|
|
@ -1436,12 +1420,6 @@ rect 653462 35808 656910 42634
|
|||
rect 641954 33988 642026 34760
|
||||
rect 643634 33988 643694 34760
|
||||
rect 641954 33920 643694 33988
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||||
rect 234814 18544 234884 19380
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||||
rect 237754 18544 237814 19380
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||||
rect 234814 18466 237814 18544
|
||||
rect 204958 17128 205020 18004
|
||||
rect 207872 17128 207958 18004
|
||||
rect 204958 17038 207958 17128
|
||||
<< via3 >>
|
||||
rect 575788 995134 580384 997056
|
||||
rect 585758 995140 590354 997062
|
||||
|
|
@ -1566,13 +1544,9 @@ rect 251392 42856 255638 46630
|
|||
rect 648166 46660 649608 47124
|
||||
rect 641994 42198 643660 43988
|
||||
rect 149632 35166 150436 35996
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||||
rect 234842 37336 237788 38178
|
||||
rect 148098 33958 148902 34788
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||||
rect 204996 30786 207928 31646
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||||
rect 653578 42634 656772 45026
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||||
rect 642026 33988 643634 34760
|
||||
rect 234884 18544 237754 19380
|
||||
rect 205020 17128 207872 18004
|
||||
<< metal4 >>
|
||||
rect 575680 997056 580478 997130
|
||||
rect 575680 995134 575788 997056
|
||||
|
|
@ -2343,6 +2317,46 @@ rect 640098 80900 640922 81016
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|||
rect 640098 78256 640210 80900
|
||||
rect 640810 78256 640922 80900
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||||
rect 640098 78134 640922 78256
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||||
rect 629888 77208 630208 77374
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||||
rect 629888 76302 629906 77208
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rect 630168 76302 630208 77208
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rect 629888 74104 630208 76302
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rect 631438 75806 631758 77374
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rect 631438 74900 631458 75806
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rect 631438 74104 631758 74900
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rect 633280 76316 633308 77222
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rect 634538 74104 634858 74904
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rect 637922 74908 637958 75814
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rect 639188 76312 639202 77218
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rect 641026 74900 641058 75806
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rect 41858 72802 45772 72890
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rect 41858 68338 41922 72802
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rect 45648 68338 45772 72802
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|
@ -2407,54 +2421,6 @@ rect 143440 40752 148940 40762
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rect 143440 40592 148086 40752
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||||
rect 148908 40592 148940 40752
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rect 143440 40582 148940 40592
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rect 213776 17108 213820 18014
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rect 213500 16308 213820 17108
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rect 215332 18516 215370 19422
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rect 215050 16308 215370 18516
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||||
rect 216600 18018 216920 19578
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||||
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||||
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||||
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||||
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||||
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||||
rect 218150 16308 218470 18516
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||||
rect 219700 18010 220020 19578
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||||
rect 219700 17104 219726 18010
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rect 219988 17104 220020 18010
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||||
rect 219700 16308 220020 17104
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||||
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||||
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||||
rect 221534 18528 221570 19434
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||||
rect 221250 16308 221570 18528
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||||
rect 222800 18036 223120 19578
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||||
rect 234818 19380 237824 19480
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||||
rect 234818 18544 234884 19380
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||||
rect 237754 18544 237824 19380
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||||
rect 234818 18470 237824 18544
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||||
rect 222800 17130 222828 18036
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||||
rect 223090 17130 223120 18036
|
||||
rect 222800 16308 223120 17130
|
||||
<< via4 >>
|
||||
rect 575762 990884 580384 993314
|
||||
rect 670928 995628 676500 996584
|
||||
|
|
@ -2651,6 +2617,16 @@ rect 594120 79916 596852 80456
|
|||
rect 602454 79938 605324 80438
|
||||
rect 632200 78326 632864 80776
|
||||
rect 640210 78256 640810 80900
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||||
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||||
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||||
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||||
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||||
rect 41936 66902 45690 67438
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||||
rect 51444 66916 52306 67436
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||||
|
|
@ -2662,18 +2638,6 @@ rect 241740 42842 245986 46616
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|||
rect 251392 42856 255638 46630
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||||
rect 648166 46660 649608 47124
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||||
rect 666460 47030 669380 47282
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||||
rect 219726 17104 219988 18010
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||||
rect 221272 18528 221534 19434
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||||
rect 234884 18544 237754 19380
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||||
rect 222828 17130 223090 18036
|
||||
<< metal5 >>
|
||||
rect 52598 996584 676660 996702
|
||||
rect 52598 995628 670928 996584
|
||||
|
|
@ -3195,6 +3159,10 @@ rect 643544 93474 646544 93588
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|||
rect 641906 93154 646544 93474
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rect 624824 89154 629362 89474
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rect 624824 89012 627824 89154
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rect 602390 79938 602454 80438
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rect 605324 79938 605390 80438
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rect 602390 47188 605390 79938
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rect 643544 85474 646544 93154
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rect 650994 92590 653994 95956
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rect 666426 93406 669426 105300
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|
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rect 641968 85154 646544 85474
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rect 643544 81082 646544 85154
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rect 666426 81082 669426 89822
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rect 602390 47188 605390 79938
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rect 632002 78326 632200 80776
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|
@ -3220,6 +3185,46 @@ rect 632864 78326 640210 80776
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|||
rect 632002 78256 640210 78326
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rect 640810 78256 669426 80900
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rect 632002 78082 669426 78256
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rect 219988 17130 222828 18010
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rect 223090 17130 224806 18036
|
||||
rect 219988 17104 224806 17130
|
||||
rect 204580 17072 224806 17104
|
||||
rect 204580 14000 205380 17072
|
||||
rect 225246 15690 226046 18472
|
||||
rect 224498 15370 226046 15690
|
||||
rect 204580 13680 205930 14000
|
||||
rect 204580 10620 205380 13680
|
||||
rect 225246 12310 226046 15370
|
||||
rect 224464 11990 226046 12310
|
||||
rect 204580 10300 205808 10620
|
||||
rect 204580 8096 205380 10300
|
||||
rect 225246 8930 226046 11990
|
||||
rect 224586 8610 226046 8930
|
||||
rect 225246 7838 226046 8610
|
||||
<< comment >>
|
||||
rect 0 1037400 717600 1037600
|
||||
rect 0 200 200 1037400
|
||||
|
|
@ -3464,8 +3422,6 @@ flabel metal5 664092 267180 666518 267904 0 FreeSans 3200 0 0 0 vssa1_core
|
|||
flabel metal5 667280 263142 669706 263866 0 FreeSans 3200 0 0 0 vdda1_core
|
||||
flabel metal5 634330 96284 638114 98514 0 FreeSans 16000 0 0 0 vssd_core
|
||||
flabel metal5 633452 78554 637236 80784 0 FreeSans 16000 0 0 0 vccd_core
|
||||
flabel metal5 206106 18628 207168 19326 0 FreeSans 4800 0 0 0 vccd_core
|
||||
flabel metal5 206018 17180 207080 17878 0 FreeSans 4800 0 0 0 vssd_core
|
||||
flabel metal5 182024 250550 190042 253308 0 FreeSans 16000 0 0 0 vssd1_core
|
||||
flabel metal5 182160 246638 190178 249396 0 FreeSans 16000 0 0 0 vccd1_core
|
||||
flabel metal5 181852 266620 189870 269378 0 FreeSans 16000 0 0 0 vssa1_core
|
||||
|
|
@ -3476,4 +3432,6 @@ flabel metal5 621512 258708 630212 261250 0 FreeSans 16000 0 0 0 vssa2_core
|
|||
flabel metal5 621598 254668 630298 257210 0 FreeSans 16000 0 0 0 vdda2_core
|
||||
flabel metal5 621936 242776 630636 245318 0 FreeSans 16000 0 0 0 vssd2_core
|
||||
flabel metal5 621794 238736 630494 241278 0 FreeSans 16000 0 0 0 vccd2_core
|
||||
flabel metal5 627056 74976 628118 75674 0 FreeSans 4800 0 0 0 vssd_core
|
||||
flabel metal5 644752 76466 645814 77164 0 FreeSans 4800 0 0 0 vccd_core
|
||||
<< end >>
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
magic
|
||||
tech sky130A
|
||||
magscale 1 2
|
||||
timestamp 1638030917
|
||||
timestamp 1638587925
|
||||
<< viali >>
|
||||
rect 1087 833 1121 867
|
||||
rect 1639 833 1673 867
|
||||
|
|
@ -77,79 +77,57 @@ rect 0 1040 5980 1062
|
|||
rect 198 824 204 876
|
||||
rect 256 864 262 876
|
||||
rect 937 864 995 873
|
||||
rect 1075 867 1133 873
|
||||
rect 1075 864 1087 867
|
||||
rect 256 836 1087 864
|
||||
rect 256 824 262 836
|
||||
rect 937 827 995 836
|
||||
rect 1075 833 1087 836
|
||||
rect 1121 833 1133 867
|
||||
rect 1075 864 1133 873
|
||||
rect 1256 864 1262 916
|
||||
rect 1314 904 1320 916
|
||||
rect 1314 876 1450 904
|
||||
rect 1314 864 1320 876
|
||||
rect 1422 864 1450 876
|
||||
rect 1489 864 1547 873
|
||||
rect 1627 867 1685 873
|
||||
rect 1627 864 1639 867
|
||||
rect 1422 836 1639 864
|
||||
rect 1075 827 1133 833
|
||||
rect 1627 864 1685 873
|
||||
rect 256 836 1133 864
|
||||
rect 1422 836 1685 864
|
||||
rect 256 824 262 836
|
||||
rect 937 827 995 836
|
||||
rect 1075 827 1133 836
|
||||
rect 1489 827 1547 836
|
||||
rect 1627 833 1639 836
|
||||
rect 1673 833 1685 867
|
||||
rect 1627 827 1685 833
|
||||
rect 1627 827 1685 836
|
||||
rect 4571 864 4629 873
|
||||
rect 4709 867 4767 873
|
||||
rect 4709 864 4721 867
|
||||
rect 4571 836 4721 864
|
||||
rect 4571 827 4629 836
|
||||
rect 4709 833 4721 836
|
||||
rect 4755 864 4767 867
|
||||
rect 4709 864 4767 873
|
||||
rect 5718 864 5724 876
|
||||
rect 4755 836 5724 864
|
||||
rect 4755 833 4767 836
|
||||
rect 4709 827 4767 833
|
||||
rect 4571 836 5724 864
|
||||
rect 4571 827 4629 836
|
||||
rect 4709 827 4767 836
|
||||
rect 5718 824 5724 836
|
||||
rect 5776 824 5782 876
|
||||
rect 1213 799 1271 805
|
||||
rect 1213 796 1225 799
|
||||
rect 1038 768 1225 796
|
||||
rect 1213 796 1271 805
|
||||
rect 1351 796 1409 805
|
||||
rect 1765 796 1823 805
|
||||
rect 1903 796 1961 805
|
||||
rect 2038 796 2044 808
|
||||
rect 1038 768 1409 796
|
||||
rect 1694 768 1961 796
|
||||
rect 2035 768 2044 796
|
||||
rect 658 688 664 740
|
||||
rect 716 728 722 740
|
||||
rect 1038 728 1066 768
|
||||
rect 1213 765 1225 768
|
||||
rect 1259 796 1271 799
|
||||
rect 1351 796 1409 805
|
||||
rect 1765 796 1823 805
|
||||
rect 1903 799 1961 805
|
||||
rect 1903 796 1915 799
|
||||
rect 1259 768 1409 796
|
||||
rect 1694 768 1915 796
|
||||
rect 1259 765 1271 768
|
||||
rect 1213 759 1271 765
|
||||
rect 1213 759 1271 768
|
||||
rect 1351 759 1409 768
|
||||
rect 716 700 1066 728
|
||||
rect 1578 716 1584 768
|
||||
rect 1636 756 1642 768
|
||||
rect 1694 756 1722 768
|
||||
rect 1765 759 1823 768
|
||||
rect 1903 765 1915 768
|
||||
rect 1949 765 1961 799
|
||||
rect 2038 796 2044 808
|
||||
rect 2035 768 2044 796
|
||||
rect 1903 759 1961 765
|
||||
rect 1903 759 1961 768
|
||||
rect 2038 756 2044 768
|
||||
rect 2096 796 2102 808
|
||||
rect 2176 799 2240 808
|
||||
rect 2176 796 2191 799
|
||||
rect 2096 768 2191 796
|
||||
rect 2096 756 2102 768
|
||||
rect 2176 765 2191 768
|
||||
rect 2225 765 2240 799
|
||||
rect 2176 796 2240 808
|
||||
rect 2360 796 2424 808
|
||||
rect 2498 796 2504 808
|
||||
rect 2096 768 2240 796
|
||||
rect 2358 768 2504 796
|
||||
rect 2176 756 2240 765
|
||||
rect 2096 756 2102 768
|
||||
rect 2176 756 2240 768
|
||||
rect 2360 756 2424 768
|
||||
rect 2498 756 2504 768
|
||||
rect 2556 756 2562 808
|
||||
|
|
@ -189,13 +167,10 @@ rect 4856 756 4862 768
|
|||
rect 4936 756 5000 768
|
||||
rect 5258 756 5264 768
|
||||
rect 5316 796 5322 808
|
||||
rect 5396 799 5460 808
|
||||
rect 5396 796 5411 799
|
||||
rect 5316 768 5411 796
|
||||
rect 5396 796 5460 808
|
||||
rect 5316 768 5460 796
|
||||
rect 5316 756 5322 768
|
||||
rect 5396 765 5411 768
|
||||
rect 5445 765 5460 799
|
||||
rect 5396 756 5460 765
|
||||
rect 5396 756 5460 768
|
||||
rect 1636 728 1722 756
|
||||
rect 1636 716 1642 728
|
||||
rect 716 688 722 700
|
||||
|
|
@ -273,36 +248,12 @@ rect 5724 824 5776 876
|
|||
rect 664 688 716 740
|
||||
rect 1584 716 1636 768
|
||||
rect 2044 756 2096 808
|
||||
rect 2504 799 2556 808
|
||||
rect 2504 765 2513 799
|
||||
rect 2513 765 2547 799
|
||||
rect 2547 765 2556 799
|
||||
rect 2504 756 2556 765
|
||||
rect 2964 799 3016 808
|
||||
rect 2964 765 2973 799
|
||||
rect 2973 765 3007 799
|
||||
rect 3007 765 3016 799
|
||||
rect 2964 756 3016 765
|
||||
rect 3424 799 3476 808
|
||||
rect 3424 765 3433 799
|
||||
rect 3433 765 3467 799
|
||||
rect 3467 765 3476 799
|
||||
rect 3424 756 3476 765
|
||||
rect 3884 799 3936 808
|
||||
rect 3884 765 3893 799
|
||||
rect 3893 765 3927 799
|
||||
rect 3927 765 3936 799
|
||||
rect 3884 756 3936 765
|
||||
rect 4344 799 4396 808
|
||||
rect 4344 765 4353 799
|
||||
rect 4353 765 4387 799
|
||||
rect 4387 765 4396 799
|
||||
rect 4344 756 4396 765
|
||||
rect 4804 799 4856 808
|
||||
rect 4804 765 4813 799
|
||||
rect 4813 765 4847 799
|
||||
rect 4847 765 4856 799
|
||||
rect 4804 756 4856 765
|
||||
rect 2504 756 2556 808
|
||||
rect 2964 756 3016 808
|
||||
rect 3424 756 3476 808
|
||||
rect 3884 756 3936 808
|
||||
rect 4344 756 4396 808
|
||||
rect 4804 756 4856 808
|
||||
rect 5264 756 5316 808
|
||||
rect 778 518 830 570
|
||||
rect 842 518 894 570
|
||||
|
|
@ -1263,201 +1214,201 @@ rect 3118 778 4282 1014
|
|||
rect 4518 778 5980 1014
|
||||
rect 0 736 5980 778
|
||||
use sky130_fd_sc_hd__fill_1 FILLER_0_9 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
|
||||
timestamp 1638025753
|
||||
timestamp 1638322937
|
||||
transform 1 0 828 0 1 544
|
||||
box -38 -48 130 592
|
||||
use sky130_fd_sc_hd__decap_3 PHY_2 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
|
||||
timestamp 1638025753
|
||||
timestamp 1638322937
|
||||
transform 1 0 0 0 -1 1632
|
||||
box -38 -48 314 592
|
||||
use sky130_fd_sc_hd__decap_3 PHY_0
|
||||
timestamp 1638025753
|
||||
timestamp 1638322937
|
||||
transform 1 0 0 0 1 544
|
||||
box -38 -48 314 592
|
||||
use sky130_fd_sc_hd__decap_12 FILLER_1_3 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
|
||||
timestamp 1638025753
|
||||
timestamp 1638322937
|
||||
transform 1 0 276 0 -1 1632
|
||||
box -38 -48 1142 592
|
||||
use sky130_fd_sc_hd__conb_1 gpio_default_value\[0\] $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
|
||||
timestamp 1638025753
|
||||
transform 1 0 920 0 1 544
|
||||
box -38 -48 314 592
|
||||
use sky130_fd_sc_hd__decap_6 FILLER_0_3 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
|
||||
timestamp 1638025753
|
||||
timestamp 1638322937
|
||||
transform 1 0 276 0 1 544
|
||||
box -38 -48 590 592
|
||||
use sky130_fd_sc_hd__conb_1 gpio_default_value\[0\] $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
|
||||
timestamp 1638322937
|
||||
transform 1 0 920 0 1 544
|
||||
box -38 -48 314 592
|
||||
use sky130_fd_sc_hd__decap_12 FILLER_1_15
|
||||
timestamp 1638025753
|
||||
timestamp 1638322937
|
||||
transform 1 0 1380 0 -1 1632
|
||||
box -38 -48 1142 592
|
||||
use sky130_fd_sc_hd__conb_1 gpio_default_value\[5\]
|
||||
timestamp 1638025753
|
||||
timestamp 1638322937
|
||||
transform 1 0 2300 0 1 544
|
||||
box -38 -48 314 592
|
||||
use sky130_fd_sc_hd__conb_1 gpio_default_value\[1\]
|
||||
timestamp 1638025753
|
||||
timestamp 1638322937
|
||||
transform 1 0 1196 0 1 544
|
||||
box -38 -48 314 592
|
||||
use sky130_fd_sc_hd__conb_1 gpio_default_value\[4\]
|
||||
timestamp 1638025753
|
||||
timestamp 1638322937
|
||||
transform 1 0 2024 0 1 544
|
||||
box -38 -48 314 592
|
||||
use sky130_fd_sc_hd__conb_1 gpio_default_value\[3\]
|
||||
timestamp 1638025753
|
||||
timestamp 1638322937
|
||||
transform 1 0 1748 0 1 544
|
||||
box -38 -48 314 592
|
||||
use sky130_fd_sc_hd__conb_1 gpio_default_value\[2\]
|
||||
timestamp 1638025753
|
||||
timestamp 1638322937
|
||||
transform 1 0 1472 0 1 544
|
||||
box -38 -48 314 592
|
||||
use sky130_fd_sc_hd__fill_1 FILLER_0_29
|
||||
timestamp 1638025753
|
||||
transform 1 0 2668 0 1 544
|
||||
box -38 -48 130 592
|
||||
use sky130_fd_sc_hd__decap_12 FILLER_1_27
|
||||
timestamp 1638025753
|
||||
transform 1 0 2484 0 -1 1632
|
||||
box -38 -48 1142 592
|
||||
use sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_6 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
|
||||
timestamp 1638025753
|
||||
timestamp 1638322937
|
||||
transform 1 0 2576 0 1 544
|
||||
box -38 -48 130 592
|
||||
use sky130_fd_sc_hd__conb_1 gpio_default_value\[7\]
|
||||
timestamp 1638025753
|
||||
transform 1 0 3220 0 1 544
|
||||
box -38 -48 314 592
|
||||
use sky130_fd_sc_hd__conb_1 gpio_default_value\[6\]
|
||||
timestamp 1638025753
|
||||
transform 1 0 2760 0 1 544
|
||||
box -38 -48 314 592
|
||||
use sky130_fd_sc_hd__fill_2 FILLER_0_38 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
|
||||
timestamp 1638025753
|
||||
timestamp 1638322937
|
||||
transform 1 0 3496 0 1 544
|
||||
box -38 -48 222 592
|
||||
use sky130_fd_sc_hd__fill_2 FILLER_0_33
|
||||
timestamp 1638025753
|
||||
timestamp 1638322937
|
||||
transform 1 0 3036 0 1 544
|
||||
box -38 -48 222 592
|
||||
use sky130_fd_sc_hd__fill_1 FILLER_0_48
|
||||
timestamp 1638025753
|
||||
transform 1 0 4416 0 1 544
|
||||
use sky130_fd_sc_hd__fill_1 FILLER_0_29
|
||||
timestamp 1638322937
|
||||
transform 1 0 2668 0 1 544
|
||||
box -38 -48 130 592
|
||||
use sky130_fd_sc_hd__decap_12 FILLER_1_27
|
||||
timestamp 1638322937
|
||||
transform 1 0 2484 0 -1 1632
|
||||
box -38 -48 1142 592
|
||||
use sky130_fd_sc_hd__conb_1 gpio_default_value\[7\]
|
||||
timestamp 1638322937
|
||||
transform 1 0 3220 0 1 544
|
||||
box -38 -48 314 592
|
||||
use sky130_fd_sc_hd__conb_1 gpio_default_value\[6\]
|
||||
timestamp 1638322937
|
||||
transform 1 0 2760 0 1 544
|
||||
box -38 -48 314 592
|
||||
use sky130_fd_sc_hd__fill_2 FILLER_0_43
|
||||
timestamp 1638322937
|
||||
transform 1 0 3956 0 1 544
|
||||
box -38 -48 222 592
|
||||
use sky130_fd_sc_hd__decap_4 FILLER_1_51 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
|
||||
timestamp 1638025753
|
||||
timestamp 1638322937
|
||||
transform 1 0 4692 0 -1 1632
|
||||
box -38 -48 406 592
|
||||
use sky130_fd_sc_hd__fill_1 FILLER_0_48
|
||||
timestamp 1638322937
|
||||
transform 1 0 4416 0 1 544
|
||||
box -38 -48 130 592
|
||||
use sky130_fd_sc_hd__decap_12 FILLER_1_39
|
||||
timestamp 1638025753
|
||||
timestamp 1638322937
|
||||
transform 1 0 3588 0 -1 1632
|
||||
box -38 -48 1142 592
|
||||
use sky130_fd_sc_hd__conb_1 gpio_default_value\[9\]
|
||||
timestamp 1638025753
|
||||
timestamp 1638322937
|
||||
transform 1 0 4140 0 1 544
|
||||
box -38 -48 314 592
|
||||
use sky130_fd_sc_hd__conb_1 gpio_default_value\[8\]
|
||||
timestamp 1638025753
|
||||
timestamp 1638322937
|
||||
transform 1 0 3680 0 1 544
|
||||
box -38 -48 314 592
|
||||
use sky130_fd_sc_hd__conb_1 gpio_default_value\[12\]
|
||||
timestamp 1638025753
|
||||
timestamp 1638322937
|
||||
transform 1 0 4508 0 1 544
|
||||
box -38 -48 314 592
|
||||
use sky130_fd_sc_hd__fill_2 FILLER_0_43
|
||||
timestamp 1638025753
|
||||
transform 1 0 3956 0 1 544
|
||||
box -38 -48 222 592
|
||||
use sky130_fd_sc_hd__conb_1 gpio_default_value\[10\]
|
||||
timestamp 1638025753
|
||||
transform 1 0 4784 0 1 544
|
||||
box -38 -48 314 592
|
||||
use sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_8
|
||||
timestamp 1638025753
|
||||
timestamp 1638322937
|
||||
transform 1 0 5152 0 -1 1632
|
||||
box -38 -48 130 592
|
||||
use sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_7
|
||||
timestamp 1638025753
|
||||
timestamp 1638322937
|
||||
transform 1 0 5152 0 1 544
|
||||
box -38 -48 130 592
|
||||
use sky130_fd_sc_hd__fill_1 FILLER_1_55
|
||||
timestamp 1638025753
|
||||
timestamp 1638322937
|
||||
transform 1 0 5060 0 -1 1632
|
||||
box -38 -48 130 592
|
||||
use sky130_fd_sc_hd__fill_1 FILLER_0_55
|
||||
timestamp 1638025753
|
||||
timestamp 1638322937
|
||||
transform 1 0 5060 0 1 544
|
||||
box -38 -48 130 592
|
||||
use sky130_fd_sc_hd__conb_1 gpio_default_value\[10\]
|
||||
timestamp 1638322937
|
||||
transform 1 0 4784 0 1 544
|
||||
box -38 -48 314 592
|
||||
use sky130_fd_sc_hd__fill_2 FILLER_0_60
|
||||
timestamp 1638025753
|
||||
timestamp 1638322937
|
||||
transform 1 0 5520 0 1 544
|
||||
box -38 -48 222 592
|
||||
use sky130_fd_sc_hd__conb_1 gpio_default_value\[11\]
|
||||
timestamp 1638025753
|
||||
transform 1 0 5244 0 1 544
|
||||
box -38 -48 314 592
|
||||
use sky130_fd_sc_hd__decap_4 FILLER_1_57
|
||||
timestamp 1638025753
|
||||
timestamp 1638322937
|
||||
transform 1 0 5244 0 -1 1632
|
||||
box -38 -48 406 592
|
||||
use sky130_fd_sc_hd__fill_1 FILLER_1_61
|
||||
timestamp 1638025753
|
||||
timestamp 1638322937
|
||||
transform 1 0 5612 0 -1 1632
|
||||
box -38 -48 130 592
|
||||
use sky130_fd_sc_hd__conb_1 gpio_default_value\[11\]
|
||||
timestamp 1638322937
|
||||
transform 1 0 5244 0 1 544
|
||||
box -38 -48 314 592
|
||||
use sky130_fd_sc_hd__decap_3 PHY_3
|
||||
timestamp 1638025753
|
||||
timestamp 1638322937
|
||||
transform -1 0 5980 0 -1 1632
|
||||
box -38 -48 314 592
|
||||
use sky130_fd_sc_hd__decap_3 PHY_1
|
||||
timestamp 1638025753
|
||||
timestamp 1638322937
|
||||
transform -1 0 5980 0 1 544
|
||||
box -38 -48 314 592
|
||||
use sky130_fd_sc_hd__decap_3 PHY_4
|
||||
timestamp 1638025753
|
||||
timestamp 1638322937
|
||||
transform 1 0 0 0 1 1632
|
||||
box -38 -48 314 592
|
||||
use sky130_fd_sc_hd__decap_12 FILLER_2_3
|
||||
timestamp 1638025753
|
||||
timestamp 1638322937
|
||||
transform 1 0 276 0 1 1632
|
||||
box -38 -48 1142 592
|
||||
use sky130_fd_sc_hd__decap_12 FILLER_2_15
|
||||
timestamp 1638025753
|
||||
timestamp 1638322937
|
||||
transform 1 0 1380 0 1 1632
|
||||
box -38 -48 1142 592
|
||||
use sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_9
|
||||
timestamp 1638322937
|
||||
transform 1 0 2576 0 1 1632
|
||||
box -38 -48 130 592
|
||||
use sky130_fd_sc_hd__fill_1 FILLER_2_27
|
||||
timestamp 1638025753
|
||||
timestamp 1638322937
|
||||
transform 1 0 2484 0 1 1632
|
||||
box -38 -48 130 592
|
||||
use sky130_fd_sc_hd__decap_12 FILLER_2_29
|
||||
timestamp 1638025753
|
||||
timestamp 1638322937
|
||||
transform 1 0 2668 0 1 1632
|
||||
box -38 -48 1142 592
|
||||
use sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_9
|
||||
timestamp 1638025753
|
||||
transform 1 0 2576 0 1 1632
|
||||
box -38 -48 130 592
|
||||
use sky130_fd_sc_hd__decap_12 FILLER_2_41
|
||||
timestamp 1638025753
|
||||
timestamp 1638322937
|
||||
transform 1 0 3772 0 1 1632
|
||||
box -38 -48 1142 592
|
||||
use sky130_fd_sc_hd__fill_1 FILLER_2_61
|
||||
timestamp 1638025753
|
||||
transform 1 0 5612 0 1 1632
|
||||
use sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_10
|
||||
timestamp 1638322937
|
||||
transform 1 0 5152 0 1 1632
|
||||
box -38 -48 130 592
|
||||
use sky130_fd_sc_hd__decap_4 FILLER_2_57
|
||||
timestamp 1638025753
|
||||
timestamp 1638322937
|
||||
transform 1 0 5244 0 1 1632
|
||||
box -38 -48 406 592
|
||||
use sky130_fd_sc_hd__fill_1 FILLER_2_61
|
||||
timestamp 1638322937
|
||||
transform 1 0 5612 0 1 1632
|
||||
box -38 -48 130 592
|
||||
use sky130_fd_sc_hd__decap_3 PHY_5
|
||||
timestamp 1638025753
|
||||
timestamp 1638322937
|
||||
transform -1 0 5980 0 1 1632
|
||||
box -38 -48 314 592
|
||||
use sky130_fd_sc_hd__decap_3 FILLER_2_53
|
||||
timestamp 1638025753
|
||||
timestamp 1638322937
|
||||
transform 1 0 4876 0 1 1632
|
||||
box -38 -48 314 592
|
||||
use sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_10
|
||||
timestamp 1638025753
|
||||
transform 1 0 5152 0 1 1632
|
||||
box -38 -48 130 592
|
||||
<< labels >>
|
||||
rlabel metal5 s 0 1436 5980 1756 6 VGND
|
||||
port 0 nsew ground input
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
magic
|
||||
tech sky130A
|
||||
timestamp 1635801696
|
||||
timestamp 1638586442
|
||||
<< metal5 >>
|
||||
tri 2970 7740 3060 7830 se
|
||||
rect 3060 7740 3960 8010
|
||||
|
|
@ -240,22 +240,25 @@ rect 4320 3420 5760 3510
|
|||
tri 5760 3420 5940 3600 sw
|
||||
tri 1080 2880 1620 3420 ne
|
||||
rect 1620 3330 2700 3420
|
||||
rect 1620 3240 2610 3330
|
||||
tri 2610 3240 2700 3330 nw
|
||||
rect 1620 3264 2634 3330
|
||||
tri 2634 3264 2700 3330 nw
|
||||
rect 4320 3330 5400 3420
|
||||
tri 4320 3240 4410 3330 ne
|
||||
rect 4410 3240 5400 3330
|
||||
tri 4320 3295 4355 3330 ne
|
||||
rect 4355 3295 5400 3330
|
||||
tri 4355 3264 4386 3295 ne
|
||||
rect 1620 3240 2634 3264
|
||||
rect 1620 3150 2160 3240
|
||||
tri 2160 3150 2250 3240 nw
|
||||
rect 1620 3060 1980 3150
|
||||
tri 1980 3060 2070 3150 nw
|
||||
tri 2315 3060 2495 3240 ne
|
||||
rect 2495 3150 2610 3240
|
||||
rect 2495 3060 2520 3150
|
||||
tri 2520 3060 2610 3150 nw
|
||||
rect 4410 3150 4525 3240
|
||||
tri 4410 3060 4500 3150 ne
|
||||
rect 4500 3060 4525 3150
|
||||
rect 2495 3174 2634 3240
|
||||
rect 2495 3060 2520 3174
|
||||
tri 2520 3060 2634 3174 nw
|
||||
rect 4386 3240 5400 3295
|
||||
rect 4386 3174 4525 3240
|
||||
tri 4386 3060 4500 3174 ne
|
||||
rect 4500 3060 4525 3174
|
||||
tri 4525 3060 4705 3240 nw
|
||||
tri 4770 3150 4860 3240 ne
|
||||
rect 4860 3150 5400 3240
|
||||
|
|
|
|||
|
|
@ -1,4 +1,18 @@
|
|||
#!/bin/sh
|
||||
#
|
||||
magic -dnull -noconsole -rcfile /usr/share/pdk/sky130A/libs.tech/magic/sky130A.magicrc << EOF
|
||||
drc off
|
||||
crashbackups stop
|
||||
load caravan
|
||||
select top cell
|
||||
expand
|
||||
extract do local
|
||||
extract all
|
||||
ext2spice lvs
|
||||
ext2spice
|
||||
EOF
|
||||
|
||||
rm *.ext
|
||||
|
||||
export NETGEN_COLUMNS=60
|
||||
netgen -batch lvs "caravan.spice caravan" "../verilog/gl/caravan.v caravan" ./sky130A_setup.tcl comp.out
|
||||
|
|
|
|||
|
|
@ -1,4 +1,18 @@
|
|||
#!/bin/sh
|
||||
#
|
||||
magic -dnull -noconsole -rcfile /usr/share/pdk/sky130A/libs.tech/magic/sky130A.magicrc << EOF
|
||||
drc off
|
||||
crashbackups stop
|
||||
load caravel
|
||||
select top cell
|
||||
expand
|
||||
extract do local
|
||||
extract all
|
||||
ext2spice lvs
|
||||
ext2spice
|
||||
EOF
|
||||
|
||||
rm *.ext
|
||||
|
||||
export NETGEN_COLUMNS=60
|
||||
netgen -batch lvs "caravel.spice caravel" "../verilog/gl/caravel.v caravel" ./sky130A_setup.tcl comp.out
|
||||
|
|
|
|||
|
|
@ -69,7 +69,7 @@ import re
|
|||
|
||||
def usage():
|
||||
print('Usage:')
|
||||
print('gen_gpio_defaults.py [<path_to_project>]')
|
||||
print('gen_gpio_defaults.py [<path_to_project>] [-test]')
|
||||
print('')
|
||||
print('where:')
|
||||
print(' <path_to_project> is the path to the project top level directory.')
|
||||
|
|
@ -123,7 +123,13 @@ if __name__ == '__main__':
|
|||
magpath = user_project_path + '/mag'
|
||||
gdspath = user_project_path + '/gds'
|
||||
vpath = user_project_path + '/verilog'
|
||||
caravel_path = os.environ['CARAVEL_ROOT']
|
||||
glpath = vpath + '/gl'
|
||||
|
||||
try:
|
||||
caravel_path = os.environ['CARAVEL_ROOT']
|
||||
except:
|
||||
print('Warning: CARAVEL_ROOT not set; assuming the cwd.')
|
||||
caravel_path = os.getcwd()
|
||||
|
||||
# Check paths
|
||||
if not os.path.isdir(gdspath):
|
||||
|
|
@ -134,6 +140,10 @@ if __name__ == '__main__':
|
|||
print('No directory ' + vpath + ' found (path to verilog).')
|
||||
sys.exit(1)
|
||||
|
||||
if not os.path.isdir(glpath):
|
||||
print('No directory ' + glpath + ' found (path to gate-level verilog).')
|
||||
sys.exit(1)
|
||||
|
||||
if not os.path.isdir(magpath):
|
||||
print('No directory ' + magpath + ' found (path to magic databases).')
|
||||
sys.exit(1)
|
||||
|
|
@ -221,17 +231,17 @@ if __name__ == '__main__':
|
|||
mag_file = magpath + '/' + cell_name + '.mag'
|
||||
cellsused[i] = cell_name
|
||||
|
||||
# Record which bits need to be set for this binval
|
||||
bitflips = []
|
||||
for j in range(0, 13):
|
||||
if binval[12 - j] == '1':
|
||||
bitflips.append(j)
|
||||
|
||||
if not os.path.isfile(mag_file):
|
||||
# A cell with this set of defaults doesn't exist, so make it
|
||||
# First read the 0000 cell, then write to mag_path while
|
||||
# changing the position of vias on the "1" bits
|
||||
|
||||
# Record which bits need to be set
|
||||
bitflips = []
|
||||
for j in range(0, 13):
|
||||
if binval[12 - j] == '1':
|
||||
bitflips.append(j)
|
||||
|
||||
with open(caravel_path + '/mag/gpio_defaults_block.mag', 'r') as ifile:
|
||||
maglines = ifile.read().splitlines()
|
||||
outlines = []
|
||||
|
|
@ -256,6 +266,42 @@ if __name__ == '__main__':
|
|||
else:
|
||||
print('Layout file ' + mag_file + ' already exists and does not need to be generated.')
|
||||
|
||||
gl_file = glpath + '/' + cell_name + '.v'
|
||||
|
||||
defrex = re.compile('[ \t]*assign[ \t]+gpio_defaults\[([0-9]+)\]')
|
||||
|
||||
if not os.path.isfile(gl_file):
|
||||
# A cell with this set of defaults doesn't exist, so make it
|
||||
# First read the default cell, then write to gl_path while
|
||||
# changing the assignment statements at the bottom of each file.
|
||||
|
||||
with open(caravel_path + '/verilog/gl/gpio_defaults_block.v', 'r') as ifile:
|
||||
vlines = ifile.read().splitlines()
|
||||
outlines = []
|
||||
for vline in vlines:
|
||||
is_flipped = False
|
||||
dmatch = defrex.match(vline)
|
||||
if dmatch:
|
||||
bitidx = int(dmatch.group(1))
|
||||
if bitidx in bitflips:
|
||||
is_flipped = True
|
||||
if is_flipped:
|
||||
outlines.append(re.sub('_low', '_high', vline))
|
||||
elif 'gpio_defaults_block' in vline:
|
||||
outlines.append(re.sub('gpio_defaults_block', cell_name, vline))
|
||||
else:
|
||||
outlines.append(vline)
|
||||
|
||||
print('Creating new gate-level verilog file ' + gl_file)
|
||||
if testmode:
|
||||
print('(Test only)')
|
||||
else:
|
||||
with open(gl_file, 'w') as ofile:
|
||||
for outline in outlines:
|
||||
print(outline, file=ofile)
|
||||
else:
|
||||
print('Gate-level verilog file ' + gl_file + ' already exists and does not need to be generated.')
|
||||
|
||||
print('Step 2: Modify top-level layouts to use the specified defaults.')
|
||||
|
||||
# Create a backup of the caravan and caravel layouts
|
||||
|
|
@ -291,6 +337,36 @@ if __name__ == '__main__':
|
|||
for outline in outlines:
|
||||
print(outline, file=ofile)
|
||||
|
||||
# Do the same to the top gate-level verilog
|
||||
|
||||
instrex = re.compile('[ \t]*(gpio_defaults_block_?[0-9]*)[ \t]+gpio_defaults_block_([0-9]+)')
|
||||
|
||||
if testmode:
|
||||
print('Test only: Caravel top gate-level verilog:')
|
||||
with open(caravel_path + '/verilog/gl/caravel.v', 'r') as ifile:
|
||||
vlines = ifile.read().splitlines()
|
||||
outlines = []
|
||||
for vline in vlines:
|
||||
imatch = instrex.match(vline)
|
||||
if imatch:
|
||||
gpioname = imatch.group(1)
|
||||
gpioidx = int(imatch.group(2))
|
||||
cellname = cellsused[int(gpioidx)]
|
||||
if cellname:
|
||||
outlines.append(re.sub(gpioname, cellname, vline, 1))
|
||||
if testmode:
|
||||
print('Replacing line: ' + vline)
|
||||
print('With: ' + outlines[-1])
|
||||
else:
|
||||
outlines.append(vline)
|
||||
else:
|
||||
outlines.append(vline)
|
||||
|
||||
if not testmode:
|
||||
with open(glpath + '/caravel.v', 'w') as ofile:
|
||||
for outline in outlines:
|
||||
print(outline, file=ofile)
|
||||
|
||||
if testmode:
|
||||
print('Test only: Caravan layout:')
|
||||
with open(caravel_path + '/mag/caravan.mag', 'r') as ifile:
|
||||
|
|
@ -319,5 +395,33 @@ if __name__ == '__main__':
|
|||
for outline in outlines:
|
||||
print(outline, file=ofile)
|
||||
|
||||
# Do the same to the top gate-level verilog
|
||||
|
||||
if testmode:
|
||||
print('Test only: Caravan top gate-level verilog:')
|
||||
with open(caravel_path + '/verilog/gl/caravan.v', 'r') as ifile:
|
||||
vlines = ifile.read().splitlines()
|
||||
outlines = []
|
||||
for vline in vlines:
|
||||
imatch = instrex.match(vline)
|
||||
if imatch:
|
||||
gpioname = imatch.group(1)
|
||||
gpioidx = int(imatch.group(2))
|
||||
cellname = cellsused[int(gpioidx)]
|
||||
if cellname:
|
||||
outlines.append(re.sub(gpioname, cellname, vline, 1))
|
||||
if testmode:
|
||||
print('Replacing line: ' + vline)
|
||||
print('With: ' + outlines[-1])
|
||||
else:
|
||||
outlines.append(vline)
|
||||
else:
|
||||
outlines.append(vline)
|
||||
|
||||
if not testmode:
|
||||
with open(glpath + '/caravan.v', 'w') as ofile:
|
||||
for outline in outlines:
|
||||
print(outline, file=ofile)
|
||||
|
||||
print('Done.')
|
||||
sys.exit(0)
|
||||
|
|
|
|||
|
|
@ -19,9 +19,6 @@ VERILOG_PATH = ../../../..
|
|||
RTL_PATH = $(VERILOG_PATH)/rtl
|
||||
BEHAVIOURAL_MODELS = ../../
|
||||
|
||||
# Temporary: Path to management SoC wrapper repository
|
||||
MGMT_WRAPPER_PATH = ~/gits/caravel_pico/verilog/rtl
|
||||
|
||||
FIRMWARE_PATH = ../..
|
||||
GCC_PATH?=/ef/apps/bin
|
||||
GCC_PREFIX?=riscv32-unknown-elf
|
||||
|
|
@ -34,6 +31,14 @@ SIM?=RTL
|
|||
|
||||
PATTERN = caravan
|
||||
|
||||
# Path to management SoC wrapper repository
|
||||
MGMT_CORE_PATH ?= ~/gits/caravel_pico
|
||||
ifeq ($(SIM),RTL)
|
||||
MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
|
||||
else
|
||||
MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
|
||||
endif
|
||||
|
||||
all: ${PATTERN:=.vcd}
|
||||
|
||||
hex: ${PATTERN:=.hex}
|
||||
|
|
@ -45,7 +50,7 @@ ifeq ($(SIM),RTL)
|
|||
$< -o $@
|
||||
else
|
||||
iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
|
||||
-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
|
||||
-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
|
||||
$< -o $@
|
||||
endif
|
||||
|
||||
|
|
|
|||
|
|
@ -19,9 +19,6 @@ VERILOG_PATH = ../../../..
|
|||
RTL_PATH = $(VERILOG_PATH)/rtl
|
||||
BEHAVIOURAL_MODELS = ../../
|
||||
|
||||
# Temporary: Path to management SoC wrapper repository
|
||||
MGMT_WRAPPER_PATH = ~/gits/caravel_pico/verilog/rtl
|
||||
|
||||
FIRMWARE_PATH = ../..
|
||||
GCC_PATH?=/ef/apps/bin
|
||||
GCC_PREFIX?=riscv32-unknown-elf
|
||||
|
|
@ -34,6 +31,14 @@ SIM?=RTL
|
|||
|
||||
PATTERN = gpio
|
||||
|
||||
# Path to management SoC wrapper repository
|
||||
MGMT_CORE_PATH ?= ~/gits/caravel_pico
|
||||
ifeq ($(SIM),RTL)
|
||||
MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
|
||||
else
|
||||
MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
|
||||
endif
|
||||
|
||||
all: ${PATTERN:=.vcd}
|
||||
|
||||
hex: ${PATTERN:=.hex}
|
||||
|
|
@ -45,7 +50,7 @@ ifeq ($(SIM),RTL)
|
|||
$< -o $@
|
||||
else
|
||||
iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
|
||||
-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
|
||||
-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
|
||||
$< -o $@
|
||||
endif
|
||||
|
||||
|
|
|
|||
|
|
@ -28,10 +28,6 @@
|
|||
`include "caravel_netlists.v"
|
||||
`include "spiflash.v"
|
||||
|
||||
// NOTE: Temporary location of management SoC wrapper is a symbolic link
|
||||
// to the caravel_pico repository verilog/rtl/mgmt_core_wrapper.v
|
||||
`include "mgmt_core_wrapper.v"
|
||||
|
||||
module gpio_tb;
|
||||
|
||||
reg clock;
|
||||
|
|
|
|||
|
|
@ -19,9 +19,6 @@ VERILOG_PATH = ../../../..
|
|||
RTL_PATH = $(VERILOG_PATH)/rtl
|
||||
BEHAVIOURAL_MODELS = ../../
|
||||
|
||||
# Temporary: Path to management SoC wrapper repository
|
||||
MGMT_WRAPPER_PATH = ~/gits/caravel_pico/verilog/rtl
|
||||
|
||||
FIRMWARE_PATH = ../..
|
||||
GCC_PATH?=/ef/apps/bin
|
||||
GCC_PREFIX?=riscv32-unknown-elf
|
||||
|
|
@ -34,6 +31,14 @@ SIM?=RTL
|
|||
|
||||
PATTERN = gpio_mgmt
|
||||
|
||||
# Path to management SoC wrapper repository
|
||||
MGMT_CORE_PATH ?= ~/gits/caravel_pico
|
||||
ifeq ($(SIM),RTL)
|
||||
MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
|
||||
else
|
||||
MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
|
||||
endif
|
||||
|
||||
all: ${PATTERN:=.vcd}
|
||||
|
||||
hex: ${PATTERN:=.hex}
|
||||
|
|
@ -45,7 +50,7 @@ ifeq ($(SIM),RTL)
|
|||
$< -o $@
|
||||
else
|
||||
iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
|
||||
-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
|
||||
-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
|
||||
$< -o $@
|
||||
endif
|
||||
|
||||
|
|
|
|||
|
|
@ -19,9 +19,6 @@ VERILOG_PATH = ../../../..
|
|||
RTL_PATH = $(VERILOG_PATH)/rtl
|
||||
BEHAVIOURAL_MODELS = ../../
|
||||
|
||||
# Temporary: Path to management SoC wrapper repository
|
||||
MGMT_WRAPPER_PATH = ~/gits/caravel_pico/verilog/rtl
|
||||
|
||||
FIRMWARE_PATH = ../..
|
||||
GCC_PATH?=/ef/apps/bin
|
||||
GCC_PREFIX?=riscv32-unknown-elf
|
||||
|
|
@ -34,6 +31,14 @@ SIM?=RTL
|
|||
|
||||
PATTERN = hkspi
|
||||
|
||||
# Path to management SoC wrapper repository
|
||||
MGMT_CORE_PATH ?= ~/gits/caravel_pico
|
||||
ifeq ($(SIM),RTL)
|
||||
MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
|
||||
else
|
||||
MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
|
||||
endif
|
||||
|
||||
all: ${PATTERN:=.vcd}
|
||||
|
||||
hex: ${PATTERN:=.hex}
|
||||
|
|
@ -45,7 +50,7 @@ ifeq ($(SIM),RTL)
|
|||
$< -o $@
|
||||
else
|
||||
iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
|
||||
-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
|
||||
-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
|
||||
$< -o $@
|
||||
endif
|
||||
|
||||
|
|
|
|||
|
|
@ -19,9 +19,6 @@ VERILOG_PATH = ../../../..
|
|||
RTL_PATH = $(VERILOG_PATH)/rtl
|
||||
BEHAVIOURAL_MODELS = ../../
|
||||
|
||||
# Temporary: Path to management SoC wrapper repository
|
||||
MGMT_WRAPPER_PATH = ~/gits/caravel_pico/verilog/rtl
|
||||
|
||||
FIRMWARE_PATH = ../..
|
||||
GCC_PATH?=/ef/apps/bin
|
||||
GCC_PREFIX?=riscv32-unknown-elf
|
||||
|
|
@ -34,6 +31,14 @@ SIM?=RTL
|
|||
|
||||
PATTERN = hkspi_power
|
||||
|
||||
# Path to management SoC wrapper repository
|
||||
MGMT_CORE_PATH ?= ~/gits/caravel_pico
|
||||
ifeq ($(SIM),RTL)
|
||||
MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
|
||||
else
|
||||
MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
|
||||
endif
|
||||
|
||||
all: ${PATTERN:=.vcd}
|
||||
|
||||
hex: ${PATTERN:=.hex}
|
||||
|
|
@ -45,7 +50,7 @@ ifeq ($(SIM),RTL)
|
|||
$< -o $@
|
||||
else
|
||||
iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
|
||||
-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
|
||||
-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
|
||||
$< -o $@
|
||||
endif
|
||||
|
||||
|
|
|
|||
|
|
@ -19,9 +19,6 @@ VERILOG_PATH = ../../../..
|
|||
RTL_PATH = $(VERILOG_PATH)/rtl
|
||||
BEHAVIOURAL_MODELS = ../../
|
||||
|
||||
# Temporary: Path to management SoC wrapper repository
|
||||
MGMT_WRAPPER_PATH = ~/gits/caravel_pico/verilog/rtl
|
||||
|
||||
FIRMWARE_PATH = ../..
|
||||
GCC_PATH?=/ef/apps/bin
|
||||
GCC_PREFIX?=riscv32-unknown-elf
|
||||
|
|
@ -34,6 +31,14 @@ SIM?=RTL
|
|||
|
||||
PATTERN = irq
|
||||
|
||||
# Path to management SoC wrapper repository
|
||||
MGMT_CORE_PATH ?= ~/gits/caravel_pico
|
||||
ifeq ($(SIM),RTL)
|
||||
MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
|
||||
else
|
||||
MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
|
||||
endif
|
||||
|
||||
all: ${PATTERN:=.vcd}
|
||||
|
||||
hex: ${PATTERN:=.hex}
|
||||
|
|
@ -45,7 +50,7 @@ ifeq ($(SIM),RTL)
|
|||
$< -o $@
|
||||
else
|
||||
iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
|
||||
-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
|
||||
-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
|
||||
$< -o $@
|
||||
endif
|
||||
|
||||
|
|
|
|||
|
|
@ -19,9 +19,6 @@ VERILOG_PATH = ../../../..
|
|||
RTL_PATH = $(VERILOG_PATH)/rtl
|
||||
BEHAVIOURAL_MODELS = ../../
|
||||
|
||||
# Temporary: Path to management SoC wrapper repository
|
||||
MGMT_WRAPPER_PATH = ~/gits/caravel_pico/verilog/rtl
|
||||
|
||||
FIRMWARE_PATH = ../..
|
||||
GCC_PATH?=/ef/apps/bin
|
||||
GCC_PREFIX?=riscv32-unknown-elf
|
||||
|
|
@ -34,6 +31,14 @@ SIM?=RTL
|
|||
|
||||
PATTERN = mem
|
||||
|
||||
# Path to management SoC wrapper repository
|
||||
MGMT_CORE_PATH ?= ~/gits/caravel_pico
|
||||
ifeq ($(SIM),RTL)
|
||||
MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
|
||||
else
|
||||
MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
|
||||
endif
|
||||
|
||||
all: ${PATTERN:=.vcd}
|
||||
|
||||
hex: ${PATTERN:=.hex}
|
||||
|
|
@ -45,7 +50,7 @@ ifeq ($(SIM),RTL)
|
|||
$< -o $@
|
||||
else
|
||||
iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
|
||||
-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
|
||||
-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
|
||||
$< -o $@
|
||||
endif
|
||||
|
||||
|
|
|
|||
|
|
@ -19,9 +19,6 @@ VERILOG_PATH = ../../../..
|
|||
RTL_PATH = $(VERILOG_PATH)/rtl
|
||||
BEHAVIOURAL_MODELS = ../../
|
||||
|
||||
# Temporary: Path to management SoC wrapper repository
|
||||
MGMT_WRAPPER_PATH = ~/gits/caravel_pico/verilog/rtl
|
||||
|
||||
FIRMWARE_PATH = ../..
|
||||
GCC_PATH?=/ef/apps/bin
|
||||
GCC_PREFIX?=riscv32-unknown-elf
|
||||
|
|
@ -34,6 +31,14 @@ SIM?=RTL
|
|||
|
||||
PATTERN = mprj_bitbang
|
||||
|
||||
# Path to management SoC wrapper repository
|
||||
MGMT_CORE_PATH ?= ~/gits/caravel_pico
|
||||
ifeq ($(SIM),RTL)
|
||||
MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
|
||||
else
|
||||
MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
|
||||
endif
|
||||
|
||||
all: ${PATTERN:=.vcd}
|
||||
|
||||
hex: ${PATTERN:=.hex}
|
||||
|
|
@ -45,7 +50,7 @@ ifeq ($(SIM),RTL)
|
|||
$< -o $@
|
||||
else
|
||||
iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
|
||||
-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
|
||||
-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
|
||||
$< -o $@
|
||||
endif
|
||||
|
||||
|
|
|
|||
|
|
@ -136,41 +136,29 @@ module mprj_bitbang_tb;
|
|||
start_csb();
|
||||
write_byte(8'h80);
|
||||
write_byte(8'h13);
|
||||
write_byte(8'h07 << 1);
|
||||
write_byte(8'h16);
|
||||
end_csb();
|
||||
|
||||
start_csb();
|
||||
write_byte(8'h80);
|
||||
write_byte(8'h13);
|
||||
write_byte(8'h03 << 1);
|
||||
write_byte(8'h06);
|
||||
end_csb();
|
||||
end
|
||||
endtask
|
||||
|
||||
task bitbang_one_clock_and_reset;
|
||||
task bitbang_load;
|
||||
begin
|
||||
start_csb();
|
||||
write_byte(8'h80);
|
||||
write_byte(8'h13);
|
||||
write_byte(8'h07 << 1);
|
||||
write_byte(8'h0e);
|
||||
end_csb();
|
||||
|
||||
start_csb();
|
||||
write_byte(8'h80);
|
||||
write_byte(8'h13);
|
||||
write_byte(8'h05 << 1);
|
||||
end_csb();
|
||||
|
||||
start_csb();
|
||||
write_byte(8'h80);
|
||||
write_byte(8'h13);
|
||||
write_byte(8'h07 << 1);
|
||||
end_csb();
|
||||
|
||||
start_csb();
|
||||
write_byte(8'h80);
|
||||
write_byte(8'h13);
|
||||
write_byte(8'h03 << 1);
|
||||
write_byte(8'h06);
|
||||
end_csb();
|
||||
end
|
||||
endtask
|
||||
|
|
@ -193,24 +181,6 @@ module mprj_bitbang_tb;
|
|||
end
|
||||
endtask
|
||||
|
||||
task bitbang_thirteen_clocks_and_reset;
|
||||
begin
|
||||
bitbang_one_clock();
|
||||
bitbang_one_clock();
|
||||
bitbang_one_clock();
|
||||
bitbang_one_clock();
|
||||
bitbang_one_clock();
|
||||
bitbang_one_clock();
|
||||
bitbang_one_clock();
|
||||
bitbang_one_clock();
|
||||
bitbang_one_clock();
|
||||
bitbang_one_clock();
|
||||
bitbang_one_clock();
|
||||
bitbang_one_clock();
|
||||
bitbang_one_clock_and_reset();
|
||||
end
|
||||
endtask
|
||||
|
||||
integer i;
|
||||
|
||||
// Now drive the digital signals on the housekeeping SPI
|
||||
|
|
@ -243,7 +213,7 @@ module mprj_bitbang_tb;
|
|||
start_csb();
|
||||
write_byte(8'h80); // Write stream command
|
||||
write_byte(8'h13); // Address (register 19 = GPIO bit-bang control)
|
||||
write_byte(8'h1b << 1); // Data = 0x01 (enable bit-bang mode)
|
||||
write_byte(8'h66); // Data = 0x01 (enable bit-bang mode)
|
||||
end_csb();
|
||||
|
||||
// Clock 12 times. Set data when clock is zero.
|
||||
|
|
@ -252,9 +222,10 @@ module mprj_bitbang_tb;
|
|||
// Bits: (0 = serial xfer)
|
||||
// 1 = bit-bang enable
|
||||
// 2 = bit-bang resetn
|
||||
// 3 = bit-bang clock
|
||||
// 4 = bit-bang data user 1
|
||||
// 5 = bit-bang data user 2
|
||||
// 3 = bit-bang load
|
||||
// 4 = bit-bang clock
|
||||
// 5 = bit-bang data user 1
|
||||
// 6 = bit-bang data user 2
|
||||
|
||||
// Apply data 0x1809 (management standard output) to
|
||||
// first block of user 1 and user 2 (GPIO 0 and 37)
|
||||
|
|
@ -263,164 +234,165 @@ module mprj_bitbang_tb;
|
|||
start_csb();
|
||||
write_byte(8'h80);
|
||||
write_byte(8'h13);
|
||||
write_byte(8'h1f << 1); // bit 0
|
||||
write_byte(8'h76); // bit 0
|
||||
end_csb();
|
||||
|
||||
start_csb();
|
||||
write_byte(8'h80);
|
||||
write_byte(8'h13);
|
||||
write_byte(8'h1b << 1);
|
||||
write_byte(8'h66);
|
||||
end_csb();
|
||||
|
||||
start_csb();
|
||||
write_byte(8'h80);
|
||||
write_byte(8'h13);
|
||||
write_byte(8'h1f << 1); // bit 1
|
||||
write_byte(8'h76); // bit 1
|
||||
end_csb();
|
||||
|
||||
start_csb();
|
||||
write_byte(8'h80);
|
||||
write_byte(8'h13);
|
||||
write_byte(8'h03 << 1);
|
||||
write_byte(8'h06);
|
||||
end_csb();
|
||||
|
||||
start_csb();
|
||||
write_byte(8'h80);
|
||||
write_byte(8'h13);
|
||||
write_byte(8'h07 << 1); // bit 2
|
||||
write_byte(8'h16); // bit 2
|
||||
end_csb();
|
||||
|
||||
start_csb();
|
||||
write_byte(8'h80);
|
||||
write_byte(8'h13);
|
||||
write_byte(8'h03 << 1);
|
||||
write_byte(8'h06);
|
||||
end_csb();
|
||||
|
||||
start_csb();
|
||||
write_byte(8'h80);
|
||||
write_byte(8'h13);
|
||||
write_byte(8'h07 << 1); // bit 3
|
||||
write_byte(8'h16); // bit 3
|
||||
end_csb();
|
||||
|
||||
start_csb();
|
||||
write_byte(8'h80);
|
||||
write_byte(8'h13);
|
||||
write_byte(8'h03 << 1);
|
||||
write_byte(8'h06);
|
||||
end_csb();
|
||||
|
||||
start_csb();
|
||||
write_byte(8'h80);
|
||||
write_byte(8'h13);
|
||||
write_byte(8'h07 << 1); // bit 4
|
||||
write_byte(8'h16); // bit 4
|
||||
end_csb();
|
||||
|
||||
start_csb();
|
||||
write_byte(8'h80);
|
||||
write_byte(8'h13);
|
||||
write_byte(8'h03 << 1);
|
||||
write_byte(8'h06);
|
||||
end_csb();
|
||||
|
||||
start_csb();
|
||||
write_byte(8'h80);
|
||||
write_byte(8'h13);
|
||||
write_byte(8'h07 << 1); // bit 5
|
||||
write_byte(8'h16); // bit 5
|
||||
end_csb();
|
||||
|
||||
start_csb();
|
||||
write_byte(8'h80);
|
||||
write_byte(8'h13);
|
||||
write_byte(8'h03 << 1);
|
||||
write_byte(8'h06);
|
||||
end_csb();
|
||||
|
||||
start_csb();
|
||||
write_byte(8'h80);
|
||||
write_byte(8'h13);
|
||||
write_byte(8'h07 << 1); // bit 6
|
||||
write_byte(8'h16); // bit 6
|
||||
end_csb();
|
||||
|
||||
start_csb();
|
||||
write_byte(8'h80);
|
||||
write_byte(8'h13);
|
||||
write_byte(8'h03 << 1);
|
||||
write_byte(8'h06);
|
||||
end_csb();
|
||||
|
||||
start_csb();
|
||||
write_byte(8'h80);
|
||||
write_byte(8'h13);
|
||||
write_byte(8'h07 << 1); // bit 7
|
||||
write_byte(8'h16); // bit 7
|
||||
end_csb();
|
||||
|
||||
start_csb();
|
||||
write_byte(8'h80);
|
||||
write_byte(8'h13);
|
||||
write_byte(8'h03 << 1);
|
||||
write_byte(8'h06);
|
||||
end_csb();
|
||||
|
||||
start_csb();
|
||||
write_byte(8'h80);
|
||||
write_byte(8'h13);
|
||||
write_byte(8'h07 << 1); // bit 8
|
||||
write_byte(8'h16); // bit 8
|
||||
end_csb();
|
||||
|
||||
start_csb();
|
||||
write_byte(8'h80);
|
||||
write_byte(8'h13);
|
||||
write_byte(8'h1b << 1);
|
||||
write_byte(8'h66);
|
||||
end_csb();
|
||||
|
||||
start_csb();
|
||||
write_byte(8'h80);
|
||||
write_byte(8'h13);
|
||||
write_byte(8'h1f << 1); // bit 9
|
||||
write_byte(8'h76); // bit 9
|
||||
end_csb();
|
||||
|
||||
start_csb();
|
||||
write_byte(8'h80);
|
||||
write_byte(8'h13);
|
||||
write_byte(8'h03 << 1);
|
||||
write_byte(8'h06);
|
||||
end_csb();
|
||||
|
||||
start_csb();
|
||||
write_byte(8'h80);
|
||||
write_byte(8'h13);
|
||||
write_byte(8'h07 << 1); // bit 10
|
||||
write_byte(8'h16); // bit 10
|
||||
end_csb();
|
||||
|
||||
start_csb();
|
||||
write_byte(8'h80);
|
||||
write_byte(8'h13);
|
||||
write_byte(8'h03 << 1);
|
||||
write_byte(8'h06);
|
||||
end_csb();
|
||||
|
||||
start_csb();
|
||||
write_byte(8'h80);
|
||||
write_byte(8'h13);
|
||||
write_byte(8'h07 << 1); // bit 11
|
||||
write_byte(8'h16); // bit 11
|
||||
end_csb();
|
||||
|
||||
start_csb();
|
||||
write_byte(8'h80);
|
||||
write_byte(8'h13);
|
||||
write_byte(8'h1b << 1);
|
||||
write_byte(8'h66);
|
||||
end_csb();
|
||||
|
||||
start_csb();
|
||||
write_byte(8'h80);
|
||||
write_byte(8'h13);
|
||||
write_byte(8'h1f << 1); // bit 12
|
||||
write_byte(8'h76); // bit 12
|
||||
end_csb();
|
||||
|
||||
start_csb();
|
||||
write_byte(8'h80);
|
||||
write_byte(8'h13);
|
||||
write_byte(8'h03 << 1);
|
||||
write_byte(8'h06);
|
||||
end_csb();
|
||||
|
||||
|
||||
// Toggle GPIO external control enable and clock forward 2 registers
|
||||
// This moves ahead of the bidirectional registers at the front.
|
||||
bitbang_thirteen_clocks();
|
||||
bitbang_thirteen_clocks_and_reset();
|
||||
bitbang_thirteen_clocks();
|
||||
bitbang_load();
|
||||
|
||||
// There is no point in resetting bit bang mode because at
|
||||
// this point the SPI pins just got disabled by loading zeros.
|
||||
|
|
|
|||
|
|
@ -19,9 +19,6 @@ VERILOG_PATH = ../../../..
|
|||
RTL_PATH = $(VERILOG_PATH)/rtl
|
||||
BEHAVIOURAL_MODELS = ../../
|
||||
|
||||
# Temporary: Path to management SoC wrapper repository
|
||||
MGMT_WRAPPER_PATH = ~/gits/caravel_pico/verilog/rtl
|
||||
|
||||
FIRMWARE_PATH = ../..
|
||||
GCC_PATH?=/ef/apps/bin
|
||||
GCC_PREFIX?=riscv32-unknown-elf
|
||||
|
|
@ -34,6 +31,14 @@ SIM?=RTL
|
|||
|
||||
PATTERN = mprj_ctrl
|
||||
|
||||
# Path to management SoC wrapper repository
|
||||
MGMT_CORE_PATH ?= ~/gits/caravel_pico
|
||||
ifeq ($(SIM),RTL)
|
||||
MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
|
||||
else
|
||||
MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
|
||||
endif
|
||||
|
||||
all: ${PATTERN:=.vcd}
|
||||
|
||||
hex: ${PATTERN:=.hex}
|
||||
|
|
@ -45,7 +50,7 @@ ifeq ($(SIM),RTL)
|
|||
$< -o $@
|
||||
else
|
||||
iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
|
||||
-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
|
||||
-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
|
||||
$< -o $@
|
||||
endif
|
||||
|
||||
|
|
|
|||
|
|
@ -19,9 +19,6 @@ VERILOG_PATH = ../../../..
|
|||
RTL_PATH = $(VERILOG_PATH)/rtl
|
||||
BEHAVIOURAL_MODELS = ../../
|
||||
|
||||
# Temporary: Path to management SoC wrapper repository
|
||||
MGMT_WRAPPER_PATH = ~/gits/caravel_pico/verilog/rtl
|
||||
|
||||
FIRMWARE_PATH = ../..
|
||||
GCC_PATH?=/ef/apps/bin
|
||||
GCC_PREFIX?=riscv32-unknown-elf
|
||||
|
|
@ -34,6 +31,14 @@ SIM?=RTL
|
|||
|
||||
PATTERN = pass_thru
|
||||
|
||||
# Path to management SoC wrapper repository
|
||||
MGMT_CORE_PATH ?= ~/gits/caravel_pico
|
||||
ifeq ($(SIM),RTL)
|
||||
MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
|
||||
else
|
||||
MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
|
||||
endif
|
||||
|
||||
all: ${PATTERN:=.vcd}
|
||||
|
||||
hex: ${PATTERN:=.hex}
|
||||
|
|
@ -45,7 +50,7 @@ ifeq ($(SIM),RTL)
|
|||
$< -o $@
|
||||
else
|
||||
iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
|
||||
-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
|
||||
-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
|
||||
$< -o $@
|
||||
endif
|
||||
|
||||
|
|
|
|||
|
|
@ -19,9 +19,6 @@ VERILOG_PATH = ../../../..
|
|||
RTL_PATH = $(VERILOG_PATH)/rtl
|
||||
BEHAVIOURAL_MODELS = ../../
|
||||
|
||||
# Temporary: Path to management SoC wrapper repository
|
||||
MGMT_WRAPPER_PATH = ~/gits/caravel_pico/verilog/rtl
|
||||
|
||||
FIRMWARE_PATH = ../..
|
||||
GCC_PATH?=/ef/apps/bin
|
||||
GCC_PREFIX?=riscv32-unknown-elf
|
||||
|
|
@ -34,6 +31,14 @@ SIM?=RTL
|
|||
|
||||
PATTERN = perf
|
||||
|
||||
# Path to management SoC wrapper repository
|
||||
MGMT_CORE_PATH ?= ~/gits/caravel_pico
|
||||
ifeq ($(SIM),RTL)
|
||||
MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
|
||||
else
|
||||
MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
|
||||
endif
|
||||
|
||||
all: ${PATTERN:=.vcd}
|
||||
|
||||
hex: ${PATTERN:=.hex}
|
||||
|
|
@ -45,7 +50,7 @@ ifeq ($(SIM),RTL)
|
|||
$< -o $@
|
||||
else
|
||||
iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
|
||||
-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
|
||||
-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
|
||||
$< -o $@
|
||||
endif
|
||||
|
||||
|
|
|
|||
|
|
@ -20,9 +20,6 @@ RTL_PATH = $(VERILOG_PATH)/rtl
|
|||
IP_PATH = ../../../../ip
|
||||
BEHAVIOURAL_MODELS = ../../
|
||||
|
||||
# Temporary: Path to management SoC wrapper repository
|
||||
MGMT_WRAPPER_PATH = ~/gits/caravel_pico/verilog/rtl
|
||||
|
||||
GCC_PATH?=/ef/apps/bin
|
||||
GCC_PREFIX?=riscv32-unknown-elf
|
||||
PDK_PATH?=$(PDK_ROOT)/sky130A
|
||||
|
|
@ -35,14 +32,28 @@ SIM?=RTL
|
|||
|
||||
PATTERN = pll
|
||||
|
||||
# Path to management SoC wrapper repository
|
||||
MGMT_CORE_PATH ?= ~/gits/caravel_pico
|
||||
ifeq ($(SIM),RTL)
|
||||
MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
|
||||
else
|
||||
MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
|
||||
endif
|
||||
|
||||
all: ${PATTERN:=.vcd}
|
||||
|
||||
hex: ${PATTERN:=.hex}
|
||||
|
||||
%.vvp: %_tb.v %.hex
|
||||
ifeq ($(SIM),RTL)
|
||||
iverilog -Ttyp $(SIM_DEFINES) -I $(BEHAVIOURAL_MODELS) \
|
||||
-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
|
||||
$< -o $@
|
||||
else
|
||||
iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
|
||||
-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
|
||||
$< -o $@
|
||||
endif
|
||||
|
||||
%.vcd: %.vvp check-env
|
||||
vvp $<
|
||||
|
|
|
|||
|
|
@ -19,9 +19,6 @@ VERILOG_PATH = ../../../..
|
|||
RTL_PATH = $(VERILOG_PATH)/rtl
|
||||
BEHAVIOURAL_MODELS = ../../
|
||||
|
||||
# Temporary: Path to management SoC wrapper repository
|
||||
MGMT_WRAPPER_PATH = ~/gits/caravel_pico/verilog/rtl
|
||||
|
||||
FIRMWARE_PATH = ../..
|
||||
GCC_PATH?=/ef/apps/bin
|
||||
GCC_PREFIX?=riscv32-unknown-elf
|
||||
|
|
@ -34,6 +31,14 @@ SIM?=RTL
|
|||
|
||||
PATTERN = qspi
|
||||
|
||||
# Path to management SoC wrapper repository
|
||||
MGMT_CORE_PATH ?= ~/gits/caravel_pico
|
||||
ifeq ($(SIM),RTL)
|
||||
MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
|
||||
else
|
||||
MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
|
||||
endif
|
||||
|
||||
all: ${PATTERN:=.vcd}
|
||||
|
||||
hex: ${PATTERN:=.hex}
|
||||
|
|
@ -45,7 +50,7 @@ ifeq ($(SIM),RTL)
|
|||
$< -o $@
|
||||
else
|
||||
iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
|
||||
-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
|
||||
-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
|
||||
$< -o $@
|
||||
endif
|
||||
|
||||
|
|
|
|||
|
|
@ -19,9 +19,6 @@ VERILOG_PATH = ../../../..
|
|||
RTL_PATH = $(VERILOG_PATH)/rtl
|
||||
BEHAVIOURAL_MODELS = ../../
|
||||
|
||||
# Temporary: Path to management SoC wrapper repository
|
||||
MGMT_WRAPPER_PATH = ~/gits/caravel_pico/verilog/rtl
|
||||
|
||||
FIRMWARE_PATH = ../..
|
||||
GCC_PATH?=/ef/apps/bin
|
||||
GCC_PREFIX?=riscv32-unknown-elf
|
||||
|
|
@ -34,6 +31,14 @@ SIM?=RTL
|
|||
|
||||
PATTERN = spi_master
|
||||
|
||||
# Path to management SoC wrapper repository
|
||||
MGMT_CORE_PATH ?= ~/gits/caravel_pico
|
||||
ifeq ($(SIM),RTL)
|
||||
MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
|
||||
else
|
||||
MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
|
||||
endif
|
||||
|
||||
all: ${PATTERN:=.vcd}
|
||||
|
||||
hex: ${PATTERN:=.hex}
|
||||
|
|
@ -45,7 +50,7 @@ ifeq ($(SIM),RTL)
|
|||
$< -o $@
|
||||
else
|
||||
iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
|
||||
-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
|
||||
-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
|
||||
$< -o $@
|
||||
endif
|
||||
|
||||
|
|
|
|||
|
|
@ -19,9 +19,6 @@ VERILOG_PATH = ../../../..
|
|||
RTL_PATH = $(VERILOG_PATH)/rtl
|
||||
BEHAVIOURAL_MODELS = ../../
|
||||
|
||||
# Temporary: Path to management SoC wrapper repository
|
||||
MGMT_WRAPPER_PATH = ~/gits/caravel_pico/verilog/rtl
|
||||
|
||||
FIRMWARE_PATH = ../..
|
||||
GCC_PATH?=/ef/apps/bin
|
||||
GCC_PREFIX?=riscv32-unknown-elf
|
||||
|
|
@ -34,6 +31,14 @@ SIM?=RTL
|
|||
|
||||
PATTERN = sram_exec
|
||||
|
||||
# Path to management SoC wrapper repository
|
||||
MGMT_CORE_PATH ?= ~/gits/caravel_pico
|
||||
ifeq ($(SIM),RTL)
|
||||
MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
|
||||
else
|
||||
MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
|
||||
endif
|
||||
|
||||
all: ${PATTERN:=.vcd}
|
||||
|
||||
hex: ${PATTERN:=.hex}
|
||||
|
|
@ -45,7 +50,7 @@ ifeq ($(SIM),RTL)
|
|||
$< -o $@
|
||||
else
|
||||
iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
|
||||
-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
|
||||
-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
|
||||
$< -o $@
|
||||
endif
|
||||
|
||||
|
|
|
|||
|
|
@ -19,9 +19,6 @@ VERILOG_PATH = ../../../..
|
|||
RTL_PATH = $(VERILOG_PATH)/rtl
|
||||
BEHAVIOURAL_MODELS = ../../
|
||||
|
||||
# Temporary: Path to management SoC wrapper repository
|
||||
MGMT_WRAPPER_PATH = ~/gits/caravel_pico/verilog/rtl
|
||||
|
||||
FIRMWARE_PATH = ../..
|
||||
GCC_PATH?=/ef/apps/bin
|
||||
GCC_PREFIX?=riscv32-unknown-elf
|
||||
|
|
@ -34,6 +31,14 @@ SIM?=RTL
|
|||
|
||||
PATTERN = storage
|
||||
|
||||
# Path to management SoC wrapper repository
|
||||
MGMT_CORE_PATH ?= ~/gits/caravel_pico
|
||||
ifeq ($(SIM),RTL)
|
||||
MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
|
||||
else
|
||||
MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
|
||||
endif
|
||||
|
||||
all: ${PATTERN:=.vcd}
|
||||
|
||||
hex: ${PATTERN:=.hex}
|
||||
|
|
@ -45,7 +50,7 @@ ifeq ($(SIM),RTL)
|
|||
$< -o $@
|
||||
else
|
||||
iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
|
||||
-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
|
||||
-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
|
||||
$< -o $@
|
||||
endif
|
||||
|
||||
|
|
|
|||
|
|
@ -19,9 +19,6 @@ VERILOG_PATH = ../../../..
|
|||
RTL_PATH = $(VERILOG_PATH)/rtl
|
||||
BEHAVIOURAL_MODELS = ../../
|
||||
|
||||
# Temporary: Path to management SoC wrapper repository
|
||||
MGMT_WRAPPER_PATH = ~/gits/caravel_pico/verilog/rtl
|
||||
|
||||
FIRMWARE_PATH = ../..
|
||||
GCC_PATH?=/ef/apps/bin
|
||||
GCC_PREFIX?=riscv32-unknown-elf
|
||||
|
|
@ -34,6 +31,14 @@ SIM?=RTL
|
|||
|
||||
PATTERN = sysctrl
|
||||
|
||||
# Path to management SoC wrapper repository
|
||||
MGMT_CORE_PATH ?= ~/gits/caravel_pico
|
||||
ifeq ($(SIM),RTL)
|
||||
MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
|
||||
else
|
||||
MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
|
||||
endif
|
||||
|
||||
all: ${PATTERN:=.vcd}
|
||||
|
||||
hex: ${PATTERN:=.hex}
|
||||
|
|
@ -45,7 +50,7 @@ ifeq ($(SIM),RTL)
|
|||
$< -o $@
|
||||
else
|
||||
iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
|
||||
-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
|
||||
-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
|
||||
$< -o $@
|
||||
endif
|
||||
|
||||
|
|
|
|||
|
|
@ -19,9 +19,6 @@ VERILOG_PATH = ../../../..
|
|||
RTL_PATH = $(VERILOG_PATH)/rtl
|
||||
BEHAVIOURAL_MODELS = ../../
|
||||
|
||||
# Temporary: Path to management SoC wrapper repository
|
||||
MGMT_WRAPPER_PATH = ~/gits/caravel_pico/verilog/rtl
|
||||
|
||||
FIRMWARE_PATH = ../..
|
||||
GCC_PATH?=/ef/apps/bin
|
||||
GCC_PREFIX?=riscv32-unknown-elf
|
||||
|
|
@ -30,6 +27,14 @@ SIM_DEFINES = -DFUNCTIONAL -DSIM
|
|||
|
||||
SIM?=RTL
|
||||
|
||||
# Path to management SoC wrapper repository
|
||||
MGMT_CORE_PATH ?= ~/gits/caravel_pico
|
||||
ifeq ($(SIM),RTL)
|
||||
MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
|
||||
else
|
||||
MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
|
||||
endif
|
||||
|
||||
.SUFFIXES:
|
||||
|
||||
PATTERN = timer
|
||||
|
|
@ -45,7 +50,7 @@ ifeq ($(SIM),RTL)
|
|||
$< -o $@
|
||||
else
|
||||
iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
|
||||
-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
|
||||
-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
|
||||
$< -o $@
|
||||
endif
|
||||
|
||||
|
|
|
|||
|
|
@ -19,9 +19,6 @@ VERILOG_PATH = ../../../..
|
|||
RTL_PATH = $(VERILOG_PATH)/rtl
|
||||
BEHAVIOURAL_MODELS = ../../
|
||||
|
||||
# Temporary: Path to management SoC wrapper repository
|
||||
MGMT_WRAPPER_PATH = ~/gits/caravel_pico/verilog/rtl
|
||||
|
||||
FIRMWARE_PATH = ../..
|
||||
GCC_PATH?=/ef/apps/bin
|
||||
GCC_PREFIX?=riscv32-unknown-elf
|
||||
|
|
@ -30,6 +27,14 @@ SIM_DEFINES = -DFUNCTIONAL -DSIM
|
|||
|
||||
SIM?=RTL
|
||||
|
||||
# Path to management SoC wrapper repository
|
||||
MGMT_CORE_PATH ?= ~/gits/caravel_pico
|
||||
ifeq ($(SIM),RTL)
|
||||
MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
|
||||
else
|
||||
MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
|
||||
endif
|
||||
|
||||
.SUFFIXES:
|
||||
|
||||
PATTERN = timer2
|
||||
|
|
@ -45,7 +50,7 @@ ifeq ($(SIM),RTL)
|
|||
$< -o $@
|
||||
else
|
||||
iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
|
||||
-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
|
||||
-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
|
||||
$< -o $@
|
||||
endif
|
||||
|
||||
|
|
|
|||
|
|
@ -19,9 +19,6 @@ VERILOG_PATH = ../../../..
|
|||
RTL_PATH = $(VERILOG_PATH)/rtl
|
||||
BEHAVIOURAL_MODELS = ../../
|
||||
|
||||
# Temporary: Path to management SoC wrapper repository
|
||||
MGMT_WRAPPER_PATH = ~/gits/caravel_pico/verilog/rtl
|
||||
|
||||
FIRMWARE_PATH = ../..
|
||||
GCC_PATH?=/ef/apps/bin
|
||||
GCC_PREFIX?=riscv32-unknown-elf
|
||||
|
|
@ -34,6 +31,14 @@ SIM?=RTL
|
|||
|
||||
PATTERN = uart
|
||||
|
||||
# Path to management SoC wrapper repository
|
||||
MGMT_CORE_PATH ?= ~/gits/caravel_pico
|
||||
ifeq ($(SIM),RTL)
|
||||
MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
|
||||
else
|
||||
MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
|
||||
endif
|
||||
|
||||
all: ${PATTERN:=.vcd}
|
||||
|
||||
hex: ${PATTERN:=.hex}
|
||||
|
|
@ -45,7 +50,7 @@ ifeq ($(SIM),RTL)
|
|||
$< -o $@
|
||||
else
|
||||
iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
|
||||
-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
|
||||
-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
|
||||
$< -o $@
|
||||
endif
|
||||
|
||||
|
|
|
|||
|
|
@ -19,9 +19,6 @@ VERILOG_PATH = ../../../..
|
|||
RTL_PATH = $(VERILOG_PATH)/rtl
|
||||
BEHAVIOURAL_MODELS = ../../
|
||||
|
||||
# Temporary: Path to management SoC wrapper repository
|
||||
MGMT_WRAPPER_PATH = ~/gits/caravel_pico/verilog/rtl
|
||||
|
||||
FIRMWARE_PATH = ../..
|
||||
GCC_PATH?=/ef/apps/bin
|
||||
GCC_PREFIX?=riscv32-unknown-elf
|
||||
|
|
@ -34,6 +31,14 @@ SIM?=RTL
|
|||
|
||||
PATTERN = user_pass_thru
|
||||
|
||||
# Path to management SoC wrapper repository
|
||||
MGMT_CORE_PATH ?= ~/gits/caravel_pico
|
||||
ifeq ($(SIM),RTL)
|
||||
MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
|
||||
else
|
||||
MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
|
||||
endif
|
||||
|
||||
all: ${PATTERN:=.vcd}
|
||||
|
||||
hex: ${PATTERN:=.hex}
|
||||
|
|
@ -45,7 +50,7 @@ ifeq ($(SIM),RTL)
|
|||
$< -o $@
|
||||
else
|
||||
iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
|
||||
-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
|
||||
-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
|
||||
$< -o $@
|
||||
endif
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,124 @@
|
|||
// SPDX-FileCopyrightText: 2020 Efabless Corporation
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
// SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
`default_nettype none
|
||||
/*
|
||||
*-------------------------------------------------------------
|
||||
*
|
||||
* user_analog_project_wrapper
|
||||
*
|
||||
* This wrapper enumerates all of the pins available to the
|
||||
* user for the user analog project.
|
||||
*
|
||||
*-------------------------------------------------------------
|
||||
*/
|
||||
|
||||
module user_analog_project_wrapper (
|
||||
`ifdef USE_POWER_PINS
|
||||
inout vdda1, // User area 1 3.3V supply
|
||||
inout vdda2, // User area 2 3.3V supply
|
||||
inout vssa1, // User area 1 analog ground
|
||||
inout vssa2, // User area 2 analog ground
|
||||
inout vccd1, // User area 1 1.8V supply
|
||||
inout vccd2, // User area 2 1.8v supply
|
||||
inout vssd1, // User area 1 digital ground
|
||||
inout vssd2, // User area 2 digital ground
|
||||
`endif
|
||||
|
||||
// Wishbone Slave ports (WB MI A)
|
||||
input wb_clk_i,
|
||||
input wb_rst_i,
|
||||
input wbs_stb_i,
|
||||
input wbs_cyc_i,
|
||||
input wbs_we_i,
|
||||
input [3:0] wbs_sel_i,
|
||||
input [31:0] wbs_dat_i,
|
||||
input [31:0] wbs_adr_i,
|
||||
output wbs_ack_o,
|
||||
output [31:0] wbs_dat_o,
|
||||
|
||||
// Logic Analyzer Signals
|
||||
input [127:0] la_data_in,
|
||||
output [127:0] la_data_out,
|
||||
input [127:0] la_oenb,
|
||||
|
||||
/* GPIOs. There are 27 GPIOs, on either side of the analog.
|
||||
* These have the following mapping to the GPIO padframe pins
|
||||
* and memory-mapped registers, since the numbering remains the
|
||||
* same as caravel but skips over the analog I/O:
|
||||
*
|
||||
* io_in/out/oeb/in_3v3 [26:14] <---> mprj_io[37:25]
|
||||
* io_in/out/oeb/in_3v3 [13:0] <---> mprj_io[13:0]
|
||||
*
|
||||
* When the GPIOs are configured by the Management SoC for
|
||||
* user use, they have three basic bidirectional controls:
|
||||
* in, out, and oeb (output enable, sense inverted). For
|
||||
* analog projects, a 3.3V copy of the signal input is
|
||||
* available. out and oeb must be 1.8V signals.
|
||||
*/
|
||||
|
||||
input [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in,
|
||||
input [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3,
|
||||
output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out,
|
||||
output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb,
|
||||
|
||||
/* Analog (direct connection to GPIO pad---not for high voltage or
|
||||
* high frequency use). The management SoC must turn off both
|
||||
* input and output buffers on these GPIOs to allow analog access.
|
||||
* These signals may drive a voltage up to the value of VDDIO
|
||||
* (3.3V typical, 5.5V maximum).
|
||||
*
|
||||
* Note that analog I/O is not available on the 7 lowest-numbered
|
||||
* GPIO pads, and so the analog_io indexing is offset from the
|
||||
* GPIO indexing by 7, as follows:
|
||||
*
|
||||
* gpio_analog/noesd [17:7] <---> mprj_io[35:25]
|
||||
* gpio_analog/noesd [6:0] <---> mprj_io[13:7]
|
||||
*
|
||||
*/
|
||||
|
||||
inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_analog,
|
||||
inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_noesd,
|
||||
|
||||
/* Analog signals, direct through to pad. These have no ESD at all,
|
||||
* so ESD protection is the responsibility of the designer.
|
||||
*
|
||||
* user_analog[10:0] <---> mprj_io[24:14]
|
||||
*
|
||||
*/
|
||||
inout [`ANALOG_PADS-1:0] io_analog,
|
||||
|
||||
/* Additional power supply ESD clamps, one per analog pad. The
|
||||
* high side should be connected to a 3.3-5.5V power supply.
|
||||
* The low side should be connected to ground.
|
||||
*
|
||||
* clamp_high[2:0] <---> mprj_io[20:18]
|
||||
* clamp_low[2:0] <---> mprj_io[20:18]
|
||||
*
|
||||
*/
|
||||
inout [2:0] io_clamp_high,
|
||||
inout [2:0] io_clamp_low,
|
||||
|
||||
// Independent clock (on independent integer divider)
|
||||
input user_clock2,
|
||||
|
||||
// User maskable interrupt signals
|
||||
output [2:0] user_irq
|
||||
);
|
||||
|
||||
// Dummy assignment so that we can take it through the openlane flow
|
||||
assign io_out = io_in;
|
||||
|
||||
endmodule // user_analog_project_wrapper
|
||||
|
|
@ -0,0 +1,91 @@
|
|||
// SPDX-FileCopyrightText: 2020 Efabless Corporation
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
// SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
`default_nettype none
|
||||
/*
|
||||
*-------------------------------------------------------------
|
||||
*
|
||||
* user_project_wrapper
|
||||
*
|
||||
* This wrapper enumerates all of the pins available to the
|
||||
* user for the user project.
|
||||
*
|
||||
* An example user project is provided in this wrapper. The
|
||||
* example should be removed and replaced with the actual
|
||||
* user project.
|
||||
*
|
||||
*-------------------------------------------------------------
|
||||
*/
|
||||
|
||||
module user_project_wrapper #(
|
||||
parameter BITS = 32
|
||||
)(
|
||||
`ifdef USE_POWER_PINS
|
||||
inout vdda1, // User area 1 3.3V supply
|
||||
inout vdda2, // User area 2 3.3V supply
|
||||
inout vssa1, // User area 1 analog ground
|
||||
inout vssa2, // User area 2 analog ground
|
||||
inout vccd1, // User area 1 1.8V supply
|
||||
inout vccd2, // User area 2 1.8v supply
|
||||
inout vssd1, // User area 1 digital ground
|
||||
inout vssd2, // User area 2 digital ground
|
||||
`endif
|
||||
|
||||
// Wishbone Slave ports (WB MI A)
|
||||
input wb_clk_i,
|
||||
input wb_rst_i,
|
||||
input wbs_stb_i,
|
||||
input wbs_cyc_i,
|
||||
input wbs_we_i,
|
||||
input [3:0] wbs_sel_i,
|
||||
input [31:0] wbs_dat_i,
|
||||
input [31:0] wbs_adr_i,
|
||||
output wbs_ack_o,
|
||||
output [31:0] wbs_dat_o,
|
||||
|
||||
// Logic Analyzer Signals
|
||||
input [127:0] la_data_in,
|
||||
output [127:0] la_data_out,
|
||||
input [127:0] la_oenb,
|
||||
|
||||
// IOs
|
||||
input [`MPRJ_IO_PADS-1:0] io_in,
|
||||
output [`MPRJ_IO_PADS-1:0] io_out,
|
||||
output [`MPRJ_IO_PADS-1:0] io_oeb,
|
||||
|
||||
// Analog (direct connection to GPIO pad---use with caution)
|
||||
// Note that analog I/O is not available on the 7 lowest-numbered
|
||||
// GPIO pads, and so the analog_io indexing is offset from the
|
||||
// GPIO indexing by 7 (also upper 2 GPIOs do not have analog_io).
|
||||
inout [`MPRJ_IO_PADS-10:0] analog_io,
|
||||
|
||||
// Independent clock (on independent integer divider)
|
||||
input user_clock2,
|
||||
|
||||
// User maskable interrupt signals
|
||||
output [2:0] user_irq
|
||||
);
|
||||
|
||||
|
||||
// Dummy assignments so that we can take it through the openlane flow
|
||||
`ifdef SIM
|
||||
// Needed for running GL simulation
|
||||
assign io_out = 0;
|
||||
assign io_oeb = 0;
|
||||
`else
|
||||
assign io_out = io_in;
|
||||
`endif
|
||||
|
||||
endmodule // user_project_wrapper
|
||||
|
|
@ -4041,7 +4041,7 @@ module caravan(vddio, vddio_2, vssio, vssio_2, vdda, vssa, vccd, vssd, vdda1, vd
|
|||
.porb_l(porb_l),
|
||||
.vdd1v8(vccd_core),
|
||||
.vdd3v3(vddio_core),
|
||||
.vss3v3(vssio_core)
|
||||
.vss3v3(vssio_core),
|
||||
.vss1v8(vssd_core)
|
||||
);
|
||||
xres_buf rstb_level (
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -49,18 +49,19 @@
|
|||
// Assume default net type to be wire because GL netlists don't have the wire
|
||||
// definitions
|
||||
`default_nettype wire
|
||||
`include "gl/mgmt_core.v"
|
||||
`include "gl/digital_pll.v"
|
||||
`include "gl/DFFRAM.v"
|
||||
`include "gl/storage.v"
|
||||
`include "gl/caravel_clocking.v"
|
||||
`include "gl/user_id_programming.v"
|
||||
`include "gl/chip_io_alt.v"
|
||||
`include "gl/housekeeping.v"
|
||||
`include "gl/mprj_logic_high.v"
|
||||
`include "gl/mprj2_logic_high.v"
|
||||
`include "gl/mgmt_protect.v"
|
||||
`include "gl/mgmt_protect_hv.v"
|
||||
`include "gl/gpio_control_block.v"
|
||||
`include "gl/gpio_defaults_block.v"
|
||||
`include "gl/gpio_defaults_block_0403.v"
|
||||
`include "gl/gpio_defaults_block_1803.v"
|
||||
`include "gl/gpio_logic_high.v"
|
||||
`include "gl/xres_buf.v"
|
||||
`include "gl/spare_logic_block.v"
|
||||
|
|
|
|||
|
|
@ -47,18 +47,19 @@
|
|||
`endif
|
||||
|
||||
`ifdef GL
|
||||
`include "gl/mgmt_core.v"
|
||||
`include "gl/digital_pll.v"
|
||||
`include "gl/DFFRAM.v"
|
||||
`include "gl/storage.v"
|
||||
`include "gl/caravel_clocking.v"
|
||||
`include "gl/user_id_programming.v"
|
||||
`include "gl/chip_io.v"
|
||||
`include "gl/housekeeping.v"
|
||||
`include "gl/mprj_logic_high.v"
|
||||
`include "gl/mprj2_logic_high.v"
|
||||
`include "gl/mgmt_protect.v"
|
||||
`include "gl/mgmt_protect_hv.v"
|
||||
`include "gl/gpio_control_block.v"
|
||||
`include "gl/gpio_defaults_block.v"
|
||||
`include "gl/gpio_defaults_block_0403.v"
|
||||
`include "gl/gpio_defaults_block_1803.v"
|
||||
`include "gl/gpio_logic_high.v"
|
||||
`include "gl/xres_buf.v"
|
||||
`include "gl/spare_logic_block.v"
|
||||
|
|
|
|||
Loading…
Reference in New Issue