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A handful of changes/corrections: (1) Housekeeping signal "user_clock" 

(input for monitoring) changed from being connected directly to the
user project (where it shouldn't be) to the same signal on the input
side of the management protect block (where it should be).  This is
functionally the same.  Checked for any other signals connected
directly from the user project to any block other than mgmt_protect,
didn't find any (good).  Modified the gate-level netlists and top-level
layouts for caravel and caravan with the corresponding change.  This
was the only change affecting layout.  Also:  Revised the "pll"
testbench.  This is still ongoing work.  Also:  Fixed the way the
pins on I/O pads are declared in chip_io.v, mprj_io.v, and pads.v, so
that it isn't so bizarre.  Most of this change is functionally
agnostic (just a change in the way the ifdefs work), but did fix an
incorrect ifdef that causes the whole user power domain to be broken.
This commit is contained in:
Tim Edwards 2021-12-06 19:38:24 -05:00
parent b6e4d5de4d
commit a9bb8bcd0a
12 changed files with 830 additions and 875 deletions
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612
mag/caravan.mag
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771
mag/caravel.mag
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File diff suppressed because it is too large Load Diff

114
verilog/dv/caravel/mgmt_soc/pll/pll.c
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@ -21,12 +21,9 @@
/*
* PLL Test (self-switching)
* - Enables SPI master
* - Uses SPI master to internally access the housekeeping SPI
* - Switches PLL bypass
* - Changes PLL divider
* - Switches PLL bypass in housekeeping
* - Changes PLL divider in housekeeping
*
* Tesbench mostly copied from sysctrl
*/
void main()
{
@ -54,6 +51,10 @@ void main()
reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
/* Monitor pins must be set to output */
reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
/* Apply configuration */
reg_mprj_xfer = 1;
while (reg_mprj_xfer == 1);
@ -61,60 +62,69 @@ void main()
// Start test
reg_mprj_datal = 0xA0400000;
// Enable SPI master
// SPI master configuration bits:
// bits 7-0: Clock prescaler value (default 2)
// bit 8: MSB/LSB first (0 = MSB first, 1 = LSB first)
// bit 9: CSB sense (0 = inverted, 1 = noninverted)
// bit 10: SCK sense (0 = noninverted, 1 = inverted)
// bit 11: mode (0 = read/write opposite edges, 1 = same edges)
// bit 12: stream (1 = CSB ends transmission)
// bit 13: enable (1 = enabled)
// bit 14: IRQ enable (1 = enabled)
// bit 15: Connect to housekeeping SPI (1 = connected)
/*
*-------------------------------------------------------------
* Register 2610_000c reg_hkspi_pll_ena
* SPI address 0x08 = PLL enables
* bit 0 = PLL enable, bit 1 = DCO enable
*
* Register 2610_0010 reg_hkspi_pll_bypass
* SPI address 0x09 = PLL bypass
* bit 0 = PLL bypass
*
* Register 2610_0020 reg_hkspi_pll_source
* SPI address 0x11 = PLL source
* bits 0-2 = phase 0 divider, bits 3-5 = phase 90 divider
*
* Register 2610_0024 reg_hkspi_pll_divider
* SPI address 0x12 = PLL divider
* bits 0-4 = feedback divider
*
* Register 2620_0004 reg_clk_out_dest
* SPI address 0x1b = Output redirect
* bit 0 = trap to mprj_io[13]
* bit 1 = clk to mprj_io[14]
* bit 2 = clk2 to mprj_io[15]
*-------------------------------------------------------------
*/
reg_spimaster_config = 0xa002; // Enable, prescaler = 2,
// connect to housekeeping SPI
// Apply stream read (0x40 + 0x03) and read back one byte
reg_spimaster_config = 0xb002; // Apply stream mode
reg_spimaster_data = 0x80; // Write 0x80 (write mode)
reg_spimaster_data = 0x08; // Write 0x18 (start address)
reg_spimaster_data = 0x01; // Write 0x01 to PLL enable, no DCO mode
reg_spimaster_config = 0xa102; // Release CSB (ends stream mode)
reg_spimaster_config = 0xb002; // Apply stream mode
reg_spimaster_data = 0x80; // Write 0x80 (write mode)
reg_spimaster_data = 0x11; // Write 0x11 (start address)
reg_spimaster_data = 0x03; // Write 0x03 to PLL output divider
reg_spimaster_config = 0xa102; // Release CSB (ends stream mode)
reg_spimaster_config = 0xb002; // Apply stream mode
reg_spimaster_data = 0x80; // Write 0x80 (write mode)
reg_spimaster_data = 0x09; // Write 0x09 (start address)
reg_spimaster_data = 0x00; // Write 0x00 to clock from PLL (no bypass)
reg_spimaster_config = 0xa102; // Release CSB (ends stream mode)
// Write checkpoint
// Write checkpoint for clock counting (PLL bypassed)
reg_mprj_datal = 0xA0410000;
reg_spimaster_config = 0xb002; // Apply stream mode
reg_spimaster_data = 0x80; // Write 0x80 (write mode)
reg_spimaster_data = 0x12; // Write 0x12 (start address)
reg_spimaster_data = 0x03; // Write 0x03 to feedback divider (was 0x04)
reg_spimaster_config = 0xa102; // Release CSB (ends stream mode)
// Monitor the core clock and user clock on mprj_io[14] and mprj_io[15]
reg_clk_out_dest = 0x6;
// Set PLL enable, no DCO mode
reg_hkspi_pll_ena = 0x1;
// Set PLL output divider to 0x03
reg_hkspi_pll_source = 0x3;
// Write checkpoint for clock counting (PLL bypassed)
reg_mprj_datal = 0xA0420000;
reg_mprj_datal = 0xA0430000;
// Disable PLL bypass
reg_hkspi_pll_bypass = 0x0;
// Write checkpoint for clock counting
reg_mprj_datal = 0xA0440000;
reg_mprj_datal = 0xA0450000;
// Write 0x03 to feedback divider (was 0x04)
reg_hkspi_pll_divider = 0x3;
// Write checkpoint
reg_mprj_datal = 0xA0420000;
reg_mprj_datal = 0xA0460000;
reg_mprj_datal = 0xA0470000;
reg_spimaster_config = 0xb002; // Apply stream mode
reg_spimaster_data = 0x80; // Write 0x80 (write mode)
reg_spimaster_data = 0x11; // Write 0x11 (start address)
reg_spimaster_data = 0x04; // Write 0x04 to PLL output divider
reg_spimaster_config = 0xa102; // Release CSB (ends stream mode)
// Write 0x04 to PLL output divider
reg_hkspi_pll_source = 0x4;
reg_spimaster_config = 0x2102; // Release housekeeping SPI
// Write checkpoint
reg_mprj_datal = 0xA0480000;
reg_mprj_datal = 0xA0490000;
// End test
reg_mprj_datal = 0xA0900000;

57
verilog/dv/caravel/mgmt_soc/pll/pll_tb.v
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@ -37,6 +37,9 @@ module pll_tb;
wire flash_io1;
wire SDO;
integer ccount;
integer ucount;
assign checkbits = mprj_io[31:16];
assign spivalue = mprj_io[15:8];
@ -46,6 +49,16 @@ module pll_tb;
always #10 clock <= (clock === 1'b0);
// User clock monitoring
always @(posedge mprj_io[15]) begin
ucount = ucount + 1;
end
// Core clock monitoring
always @(posedge mprj_io[14]) begin
ccount = ccount + 1;
end
initial begin
clock = 0;
end
@ -66,21 +79,39 @@ module pll_tb;
// Monitor
initial begin
wait(checkbits == 16'hA040);
$display("Monitor: Test PLL (RTL) Started");
$display("Monitor: Test 1 PLL (RTL) Started");
ucount = 0;
ccount = 0;
wait(checkbits == 16'hA041);
// $display(" SPI value = 0x%x (should be 0x04)", spivalue);
// if(spivalue !== 32'h04) begin
// $display("Monitor: Test PLL (RTL) Failed");
// $finish;
// end
$display("Monitor: ucount = %d ccount = %d", ucount, ccount);
wait(checkbits == 16'hA042);
// $display(" SPI value = 0x%x (should be 0x56)", spivalue);
// if(spivalue !== 32'h56) begin
// $display("Monitor: Test PLL (RTL) Failed");
// $finish;
// end
$display("Monitor: Test 2 PLL (RTL) Started");
ucount = 0;
ccount = 0;
wait(checkbits == 16'hA043);
$display("Monitor: ucount = %d ccount = %d", ucount, ccount);
wait(checkbits == 16'hA044);
$display("Monitor: Test 3 PLL (RTL) Started");
ucount = 0;
ccount = 0;
wait(checkbits == 16'hA045);
$display("Monitor: ucount = %d ccount = %d", ucount, ccount);
wait(checkbits == 16'hA046);
$display("Monitor: Test 4 PLL (RTL) Started");
ucount = 0;
ccount = 0;
wait(checkbits == 16'hA047);
$display("Monitor: ucount = %d ccount = %d", ucount, ccount);
wait(checkbits == 16'hA048);
$display("Monitor: Test 5 PLL (RTL) Started");
ucount = 0;
ccount = 0;
wait(checkbits == 16'hA049);
$display("Monitor: ucount = %d ccount = %d", ucount, ccount);
wait(checkbits == 16'hA090);

2
verilog/gl/caravan.v
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@ -3841,7 +3841,7 @@ module caravan(vddio, vddio_2, vssio, vssio_2, vdda, vssa, vccd, vssd, vdda1, vd
.sram_ro_data({ \hkspi_sram_data[31] , \hkspi_sram_data[30] , \hkspi_sram_data[29] , \hkspi_sram_data[28] , \hkspi_sram_data[27] , \hkspi_sram_data[26] , \hkspi_sram_data[25] , \hkspi_sram_data[24] , \hkspi_sram_data[23] , \hkspi_sram_data[22] , \hkspi_sram_data[21] , \hkspi_sram_data[20] , \hkspi_sram_data[19] , \hkspi_sram_data[18] , \hkspi_sram_data[17] , \hkspi_sram_data[16] , \hkspi_sram_data[15] , \hkspi_sram_data[14] , \hkspi_sram_data[13] , \hkspi_sram_data[12] , \hkspi_sram_data[11] , \hkspi_sram_data[10] , \hkspi_sram_data[9] , \hkspi_sram_data[8] , \hkspi_sram_data[7] , \hkspi_sram_data[6] , \hkspi_sram_data[5] , \hkspi_sram_data[4] , \hkspi_sram_data[3] , \hkspi_sram_data[2] , \hkspi_sram_data[1] , \hkspi_sram_data[0] }),
.trap(trap),
.uart_enabled(uart_enabled),
.user_clock(mprj_clock2),
.user_clock(caravel_clk2),
.usr1_vcc_pwrgood(mprj_vcc_pwrgood),
.usr1_vdd_pwrgood(mprj_vdd_pwrgood),
.usr2_vcc_pwrgood(mprj2_vcc_pwrgood),

2
verilog/gl/caravel.v
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@ -4579,7 +4579,7 @@ module caravel(vddio, vddio_2, vssio, vssio_2, vdda, vssa, vccd, vssd, vdda1, vd
.sram_ro_data({ \hkspi_sram_data[31] , \hkspi_sram_data[30] , \hkspi_sram_data[29] , \hkspi_sram_data[28] , \hkspi_sram_data[27] , \hkspi_sram_data[26] , \hkspi_sram_data[25] , \hkspi_sram_data[24] , \hkspi_sram_data[23] , \hkspi_sram_data[22] , \hkspi_sram_data[21] , \hkspi_sram_data[20] , \hkspi_sram_data[19] , \hkspi_sram_data[18] , \hkspi_sram_data[17] , \hkspi_sram_data[16] , \hkspi_sram_data[15] , \hkspi_sram_data[14] , \hkspi_sram_data[13] , \hkspi_sram_data[12] , \hkspi_sram_data[11] , \hkspi_sram_data[10] , \hkspi_sram_data[9] , \hkspi_sram_data[8] , \hkspi_sram_data[7] , \hkspi_sram_data[6] , \hkspi_sram_data[5] , \hkspi_sram_data[4] , \hkspi_sram_data[3] , \hkspi_sram_data[2] , \hkspi_sram_data[1] , \hkspi_sram_data[0] }),
.trap(trap),
.uart_enabled(uart_enabled),
.user_clock(mprj_clock2),
.user_clock(caravel_clk2),
.usr1_vcc_pwrgood(mprj_vcc_pwrgood),
.usr1_vdd_pwrgood(mprj_vdd_pwrgood),
.usr2_vcc_pwrgood(mprj2_vcc_pwrgood),

2
verilog/rtl/caravan.v
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@ -767,7 +767,7 @@ module caravan (
.trap(trap),
.user_clock(mprj_clock2),
.user_clock(caravel_clk2),
.mask_rev_in(mask_rev),

2
verilog/rtl/caravel.v
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@ -712,7 +712,7 @@ module caravel (
.trap(trap),
.user_clock(mprj_clock2),
.user_clock(caravel_clk2),
.mask_rev_in(mask_rev),

4
verilog/rtl/caravel_netlists.v
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@ -48,6 +48,8 @@
`ifdef GL
`include "gl/digital_pll.v"
`include "gl/digital_pll_controller.v"
`include "gl/ring_osc2x13.v"
`include "gl/caravel_clocking.v"
`include "gl/user_id_programming.v"
`include "gl/chip_io.v"
@ -67,6 +69,8 @@
`include "gl/caravel.v"
`else
`include "digital_pll.v"
`include "digital_pll_controller.v"
`include "ring_osc2x13.v"
`include "caravel_clocking.v"
`include "user_id_programming.v"
`include "clock_div.v"

121
verilog/rtl/chip_io.v
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@ -126,74 +126,58 @@ module chip_io(
sky130_ef_io__vddio_hvc_clamped_pad \mgmt_vddio_hvclamp_pad[0] (
`MGMT_ABUTMENT_PINS
`ifdef TOP_ROUTING
.VDDIO(vddio)
`else
,.VDDIO_PAD(vddio_pad)
`ifndef TOP_ROUTING
.VDDIO_PAD(vddio_pad)
`endif
);
// lies in user area 2
sky130_ef_io__vddio_hvc_clamped_pad \mgmt_vddio_hvclamp_pad[1] (
`USER2_ABUTMENT_PINS
`ifdef TOP_ROUTING
.VDDIO(vddio)
`else
,.VDDIO_PAD(vddio_pad2)
`ifndef TOP_ROUTING
.VDDIO_PAD(vddio_pad2)
`endif
);
sky130_ef_io__vdda_hvc_clamped_pad mgmt_vdda_hvclamp_pad (
`MGMT_ABUTMENT_PINS
`ifdef TOP_ROUTING
.VDDA(vdda)
`else
,.VDDA_PAD(vdda_pad)
`ifndef TOP_ROUTING
.VDDA_PAD(vdda_pad)
`endif
);
sky130_ef_io__vccd_lvc_clamped_pad mgmt_vccd_lvclamp_pad (
`MGMT_ABUTMENT_PINS
`ifdef TOP_ROUTING
.VCCD(vccd)
`else
,.VCCD_PAD(vccd_pad)
`ifndef TOP_ROUTING
.VCCD_PAD(vccd_pad)
`endif
);
sky130_ef_io__vssio_hvc_clamped_pad \mgmt_vssio_hvclamp_pad[0] (
`MGMT_ABUTMENT_PINS
`ifdef TOP_ROUTING
.VSSIO(vssio)
`else
,.VSSIO_PAD(vssio_pad)
`ifndef TOP_ROUTING
.VSSIO_PAD(vssio_pad)
`endif
);
sky130_ef_io__vssio_hvc_clamped_pad \mgmt_vssio_hvclamp_pad[1] (
`USER2_ABUTMENT_PINS
`ifdef TOP_ROUTING
.VSSIO(vssio)
`else
,.VSSIO_PAD(vssio_pad2)
`ifndef TOP_ROUTING
.VSSIO_PAD(vssio_pad2)
`endif
);
sky130_ef_io__vssa_hvc_clamped_pad mgmt_vssa_hvclamp_pad (
`MGMT_ABUTMENT_PINS
`ifdef TOP_ROUTING
.VSSA(vssa)
`else
,.VSSA_PAD(vssa_pad)
`ifndef TOP_ROUTING
.VSSA_PAD(vssa_pad)
`endif
);
sky130_ef_io__vssd_lvc_clamped_pad mgmt_vssd_lvclamp_pad (
`MGMT_ABUTMENT_PINS
`ifdef TOP_ROUTING
.VSSD(vssd)
`else
,.VSSD_PAD(vssd_pad)
`ifndef TOP_ROUTING
.VSSD_PAD(vssd_pad)
`endif
);
@ -202,58 +186,48 @@ module chip_io(
sky130_ef_io__vdda_hvc_clamped_pad \user1_vdda_hvclamp_pad[0] (
`USER1_ABUTMENT_PINS
`ifdef TOP_ROUTING
.VDDA(vdda1)
`else
,.VDDA_PAD(vdda1_pad)
`ifndef TOP_ROUTING
.VDDA_PAD(vdda1_pad)
`endif
);
sky130_ef_io__vdda_hvc_clamped_pad \user1_vdda_hvclamp_pad[1] (
`USER1_ABUTMENT_PINS
`ifdef TOP_ROUTING
.VDDA(vdda1)
`else
,.VDDA_PAD(vdda1_pad2)
`ifndef TOP_ROUTING
.VDDA_PAD(vdda1_pad2)
`endif
);
sky130_ef_io__vccd_lvc_clamped3_pad user1_vccd_lvclamp_pad (
`USER1_ABUTMENT_PINS
`ifdef TOP_ROUTING
.VCCD1(vccd1),
.VSSD1(vssd1)
`else
,.VCCD_PAD(vccd1_pad)
.VSSD1(vssd1),
`ifndef TOP_ROUTING
.VCCD_PAD(vccd1_pad)
`endif
);
sky130_ef_io__vssa_hvc_clamped_pad \user1_vssa_hvclamp_pad[0] (
`USER1_ABUTMENT_PINS
`ifdef TOP_ROUTING
.VSSA(vssa1)
`else
,.VSSA_PAD(vssa1_pad)
`ifndef TOP_ROUTING
.VSSA_PAD(vssa1_pad)
`endif
);
sky130_ef_io__vssa_hvc_clamped_pad \user1_vssa_hvclamp_pad[1] (
`USER1_ABUTMENT_PINS
`ifdef TOP_ROUTING
.VSSA(vssa1)
`else
,.VSSA_PAD(vssa1_pad2)
`ifndef TOP_ROUTING
.VSSA_PAD(vssa1_pad2)
`endif
);
sky130_ef_io__vssd_lvc_clamped3_pad user1_vssd_lvclamp_pad (
`USER1_ABUTMENT_PINS
`ifdef TOP_ROUTING
.VCCD1(vccd1),
.VSSD1(vssd1)
`else
,.VSSD_PAD(vssd1_pad)
.VSSD1(vssd1),
`ifndef TOP_ROUTING
.VSSD_PAD(vssd1_pad)
`endif
);
@ -262,39 +236,33 @@ module chip_io(
sky130_ef_io__vdda_hvc_clamped_pad user2_vdda_hvclamp_pad (
`USER2_ABUTMENT_PINS
`ifdef TOP_ROUTING
.VDDA(vdda2)
`else
,.VDDA_PAD(vdda2_pad)
`ifndef TOP_ROUTING
.VDDA_PAD(vdda2_pad)
`endif
);
sky130_ef_io__vccd_lvc_clamped3_pad user2_vccd_lvclamp_pad (
`USER2_ABUTMENT_PINS
`ifdef TOP_ROUTING
.VCCD1(vccd2),
.VSSD1(vssd2)
`else
,.VCCD_PAD(vccd2_pad)
.VSSD1(vssd2),
`ifndef TOP_ROUTING
.VCCD_PAD(vccd2_pad)
`endif
);
sky130_ef_io__vssa_hvc_clamped_pad user2_vssa_hvclamp_pad (
`USER2_ABUTMENT_PINS
`ifdef TOP_ROUTING
.VSSA(vssa2)
`else
,.VSSA_PAD(vssa2_pad)
`ifndef TOP_ROUTING
.VSSA_PAD(vssa2_pad)
`endif
);
sky130_ef_io__vssd_lvc_clamped3_pad user2_vssd_lvclamp_pad (
`USER2_ABUTMENT_PINS
`ifdef TOP_ROUTING
.VCCD1(vccd2),
.VSSD1(vssd2)
`else
,.VSSD_PAD(vssd2_pad)
.VSSD1(vssd2),
`ifndef TOP_ROUTING
.VSSD_PAD(vssd2_pad)
`endif
);
@ -328,7 +296,7 @@ module chip_io(
sky130_fd_io__top_xres4v2 resetb_pad (
`MGMT_ABUTMENT_PINS
`ifndef TOP_ROUTING
,.PAD(resetb),
.PAD(resetb),
`endif
.TIE_WEAK_HI_H(xresloop), // Loop-back connection to pad through pad_a_esd_h
.TIE_HI_ESD(),
@ -361,10 +329,7 @@ module chip_io(
.VDDA(vdda),
.VCCD(vccd),
.VCCHIB(vccd)
`else
.VCCHIB()
`endif
);
sky130_ef_io__corner_pad user1_corner (
`ifndef TOP_ROUTING
@ -380,8 +345,6 @@ module chip_io(
.VDDA(vdda1),
.VCCD(vccd),
.VCCHIB(vccd)
`else
.VCCHIB()
`endif
);
sky130_ef_io__corner_pad user2_corner (
@ -398,8 +361,6 @@ module chip_io(
.VDDA(vdda2),
.VCCD(vccd),
.VCCHIB(vccd)
`else
.VCCHIB()
`endif
);

4
verilog/rtl/mprj_io.v
View File

@ -71,7 +71,7 @@ module mprj_io #(
sky130_ef_io__gpiov2_pad_wrapped area1_io_pad [AREA1PADS - 1:0] (
`USER1_ABUTMENT_PINS
`ifndef TOP_ROUTING
,.PAD(io[AREA1PADS - 1:0]),
.PAD(io[AREA1PADS - 1:0]),
`endif
.OUT(io_out[AREA1PADS - 1:0]),
.OE_N(oeb[AREA1PADS - 1:0]),
@ -102,7 +102,7 @@ module mprj_io #(
sky130_ef_io__gpiov2_pad_wrapped area2_io_pad [TOTAL_PADS - AREA1PADS - 1:0] (
`USER2_ABUTMENT_PINS
`ifndef TOP_ROUTING
,.PAD(io[TOTAL_PADS - 1:AREA1PADS]),
.PAD(io[TOTAL_PADS - 1:AREA1PADS]),
`endif
.OUT(io_out[TOTAL_PADS - 1:AREA1PADS]),
.OE_N(oeb[TOTAL_PADS - 1:AREA1PADS]),

14
verilog/rtl/pads.v
View File

@ -27,7 +27,7 @@
.VCCD(vccd),\
.VSSIO(vssio),\
.VSSD(vssd),\
.VSSIO_Q(vssio_q)
.VSSIO_Q(vssio_q),
`define USER2_ABUTMENT_PINS \
.AMUXBUS_A(analog_a),\
@ -41,7 +41,7 @@
.VCCD(vccd),\
.VSSIO(vssio),\
.VSSD(vssd),\
.VSSIO_Q(vssio_q)
.VSSIO_Q(vssio_q),
`define MGMT_ABUTMENT_PINS \
.AMUXBUS_A(analog_a),\
@ -55,7 +55,7 @@
.VCCD(vccd),\
.VSSIO(vssio),\
.VSSD(vssd),\
.VSSIO_Q(vssio_q)
.VSSIO_Q(vssio_q),
`else
`define USER1_ABUTMENT_PINS
`define USER2_ABUTMENT_PINS
@ -78,7 +78,7 @@
sky130_ef_io__gpiov2_pad_wrapped X``_pad ( \
`MGMT_ABUTMENT_PINS \
`ifndef TOP_ROUTING \
,.PAD(X), \
.PAD(X), \
`endif \
.OUT(vssd), \
.OE_N(vccd), \
@ -110,7 +110,7 @@
sky130_ef_io__gpiov2_pad_wrapped X``_pad ( \
`MGMT_ABUTMENT_PINS \
`ifndef TOP_ROUTING \
,.PAD(X), \
.PAD(X), \
`endif \
.OUT(Y), \
.OE_N(OUT_EN_N), \
@ -142,7 +142,7 @@
sky130_ef_io__gpiov2_pad_wrapped X``_pad ( \
`MGMT_ABUTMENT_PINS \
`ifndef TOP_ROUTING \
,.PAD(X), \
.PAD(X), \
`endif \
.OUT(Y), \
.OE_N(OUT_EN_N), \
@ -174,7 +174,7 @@
sky130_ef_io__gpiov2_pad_wrapped X``_pad ( \
`MGMT_ABUTMENT_PINS \
`ifndef TOP_ROUTING \
,.PAD(X), \
.PAD(X), \
`endif \
.OUT(Y_OUT), \
.OE_N(OUT_EN_N), \