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caravel
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This (late and invasive) change modifies the housekeeping block to 

add a separate signal for the houskeeping wb_cyc_i wishbone signal,
instead of combining it with the user project's wb_cyc_i.  This
change makes it compatible with the LiteX implementation of the
wishbone bus.
This commit is contained in:
Tim Edwards 2021-11-29 14:23:30 -05:00
parent d033d2e62d
commit 4dac106297
2 changed files with 5 additions and 2 deletions
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4
verilog/rtl/caravel.v
View File

@ -332,6 +332,7 @@ module caravel (
wire [31:0] hk_dat_i;
wire hk_ack_i;
wire hk_stb_o;
wire hk_cyc_o;
// Exported Wishbone Bus (user area facing)
wire mprj_cyc_o_user;
@ -411,6 +412,7 @@ module caravel (
.mprj_dat_i(mprj_dat_i_core),
.hk_stb_o(hk_stb_o),
.hk_cyc_o(hk_cyc_o),
.hk_dat_i(hk_dat_i),
.hk_ack_i(hk_ack_i),
@ -656,7 +658,7 @@ module caravel (
.wb_dat_i(mprj_dat_o_core),
.wb_sel_i(mprj_sel_o_core),
.wb_we_i(mprj_we_o_core),
.wb_cyc_i(mprj_cyc_o_core),
.wb_cyc_i(hk_cyc_o),
.wb_stb_i(hk_stb_o),
.wb_ack_o(hk_ack_i),
.wb_dat_o(hk_dat_i),

3
verilog/rtl/housekeeping.v
View File

@ -651,7 +651,8 @@ module housekeeping #(
case (wbbd_state)
`WBBD_IDLE: begin
wbbd_busy <= 1'b0;
if (wb_cyc_i && (sys_select | gpio_select | spi_select)) begin
if ((sys_select | gpio_select | spi_select) &&
wb_cyc_i && wb_stb_i) begin
wb_ack_o <= 1'b0;
wbbd_state <= `WBBD_SETUP0;
end