Commit Graph

237 Commits

Author SHA1 Message Date
Marwan Abbas cb051054af
Merge pull request #254 from mo-hosni/hk_without_lables
housekeeping without labels
2022-10-16 13:38:02 +02:00
mo-hosni 3f0bddbcc6 update openlane views 2022-10-16 03:45:30 -07:00
mo-hosni 22dde425ac add mgmt_protect views and openlane files 2022-10-16 03:14:55 -07:00
kareem 507446e719 Merge branch 'caravel_redesign' into fix_top_buffers_again 2022-10-16 02:01:52 -07:00
Tim Edwards a77a45babe Adjustments to the top level buffering cells to do various things
like avoid obstructions in the padframe and power routing, add
decap, and separate coupling wires to reduce capacitance.
2022-10-15 17:35:17 -04:00
kareem 5d5d019ea1 Revert "add buff_flash_clkrst"
This reverts commit 2675487322.
2022-10-15 08:47:02 -07:00
Tim Edwards 3db846b119 Fixes issues with the GPIO signal buffering by applying a bounding
box to the layout, so that LEF and DEF positions are correct.
2022-10-15 10:31:35 -04:00
mo-hosni 2675487322 add buff_flash_clkrst 2022-10-15 06:38:42 -07:00
kareem 3e3bd111c1 ~ correct paths refereces in mag and maglef files from openlane 2022-10-15 04:06:07 -07:00
Marwan Abbas 316f2dbb58
Merge pull request #238 from mo-hosni/update_mgmt_protect
Update mgmt protect
2022-10-15 11:27:59 +02:00
mo-hosni 3361c8787d Add mgmt_protect views and openlane files 2022-10-15 01:46:22 -07:00
passant5 8c0e4f7403
Merge branch 'caravel_redesign' into add_top_level_buffers 2022-10-15 00:28:14 +02:00
Tim Edwards 1f5a158077 Essentially the same commit as the last one, but setting the metal
3 horizontal bus width to 0.5um, as requested, rather than 0.6um.
2022-10-14 16:36:42 -04:00
Tim Edwards 276580feb4 Updated the metal 3 horizontal power stripes on the mgmt_protect_hv
layout to make them 0.6um (up from 0.3um wide).
2022-10-14 16:28:07 -04:00
Tim Edwards 92e2f5e8a4 Added layout views (.mag, GDS, DEF, and LEF) for the caravan
variant of the top level GPIO signal buffering (module
gpio_signal_buffering_alt).
2022-10-14 16:06:11 -04:00
Tim Edwards aff5817f30 Rewrote the layout for mgmt_protect_hv after correcting the pins,
which had not been correctly annotated for ports and so were
marked only as plain labels, causing issues when using the cell
as a macro inside mgmt_protect.
2022-10-14 15:11:52 -04:00
mo-hosni 0e01725608 add housekeeping views 2022-10-14 09:26:34 -07:00
kareem aadfb57609 reharden: caravel_clocking
~ align pdn with top level
~ move spefs and sdfs output corners to signoff/*/openlane-signoff
2022-10-14 05:24:49 -07:00
Tim Edwards 46d44793e2 Added layout for the gpio_signal_buffering module, including GDS,
LEF, DEF, and magic views.
2022-10-13 21:59:10 -04:00
kareem 6452f14de0 reimplement caravel with latest blocks updates and a buffer macro 2022-10-13 13:34:47 -07:00
Marwan Abbas f7299933ee
Merge pull request #217 from mo-hosni/buff_flash_clkrst
Buff flash clkrst
2022-10-13 20:53:18 +02:00
Marwan Abbas 14856fea6d
Merge pull request #216 from mo-hosni/housekeeping_final_views
Housekeeping final views
2022-10-13 20:47:09 +02:00
Marwan Abbas e72f819020
Merge pull request #210 from mo-hosni/final_views
mgmt_protect final views
2022-10-13 20:33:57 +02:00
Marwan Abbas 08ac55bed8
Merge pull request #214 from efabless/caravel_clocking-buffering
Caravel clocking reharden
2022-10-13 20:13:45 +02:00
kareem c922241c3f reharden: caravel_clocking
+ add custom interactive script to insert a buffer on user_clk output
and have a large buffer on core_clk
~ change pdn config to match top level
~ change sdc
~ change openlane configuration
2022-10-13 10:54:04 -07:00
mo-hosni 889aa7e308 add buff_flash_clkrst 2022-10-13 10:35:51 -07:00
mo-hosni 0389423ea6 add housekeeping 2022-10-13 10:15:05 -07:00
mo-hosni 1aaebf5cbb add mgmt_protect 2022-10-13 10:11:45 -07:00
kareem 59743f4832 change buf16 to clkbuf16 and reimplement 2022-10-13 06:54:55 -07:00
kareem 0eed96f33f reharden: digital_pll
~ reimplement digital_pll using updated RTL
~ changes in config to generate same PDN
~ change deprecated variables
2022-10-13 06:21:08 -07:00
kareem 9ccb0ff2ed reharden!: caravel
~ reimplement based on updated views of the macros
~ change interactive script to call label_macro_pins
~ extract all spef and sdf corners using timing-scripts repo

!important same work arounds as before
2022-10-12 04:45:08 -07:00
Mohamed Shalan 98951388d0
Merge pull request #179 from efabless/chip_io_fix_ports
Fixes the .mag, LEF, DEF, and GDS views of chip_io and chip_io_alt
2022-10-12 11:37:24 +02:00
mo-hosni 76f8d37496 Rehardened housekeeping to fix Antenna violations. 2022-10-11 16:41:50 -07:00
Tim Edwards 0fd05dde39 This commit creates a LEF abstract view of the top level, which
establishes all the pin names, positions, classes, and uses.  Adds
a script which uses the LEF abstract view to annotate the top level
layouts for caravel and caravan with the chip pins (not yet run---
waiting for a valid top level layout after top-level routing).
Also:  Updated the copyright block to increase the chip version
number and update the date.
2022-10-11 16:19:06 -04:00
Tim Edwards a2feddf714 Corrected the layout views of chip_io and chip_io_alt, which were
missing some of the labels for the power supplies (they were
accidentally erased during layout re-work).
2022-10-11 11:39:03 -04:00
marwaneltoukhy fe96857e5e added gpio_defaults_block_0801.mag 2022-10-11 07:48:14 -07:00
Mohamed Hosni ee17bcf177
Merge branch 'efabless:caravel_redesign' into caravel_redesign 2022-10-11 01:47:06 -07:00
mo-hosni df05079b6f update houskeepong powere netlst and fixed some antenna violations 2022-10-11 01:46:23 -07:00
Mohamed Shalan 344f806980
Merge pull request #166 from efabless/gpio_control_block-sparecell
gpio_control_block sparecell
2022-10-11 10:39:50 +02:00
kareem f4218ddde9 reharden!: gpio_control_block
- reimplement using a sparecell
- reimplement using newest open_pdks

!important using openlane pre odb with some local patches which
most if not all are merged in the current head of openlane however
still takes effort to update the interactive script to be latest
openlane compatible

!important override abstract lef generated by openlane. openlane
 generates lef and mag that contain def BLOCKAGE layers that cause
congestions during top level routing
2022-10-10 05:42:29 -07:00
Mohamed Hosni 40098f693e
Merge branch 'efabless:caravel_redesign' into caravel_redesign 2022-10-10 05:08:33 -07:00
kareem 285ef6b642 reharden!: caravel
~ update the following views:
def
mag
verilog
spef(all corners)
+ add the ability to override the interactive script filename
+ add the ability to run openlane regression using regression.config
file
~ change GRT ADJUSTMENT values
~ change pointers to some files for workarounds

!important the interactive script still needs updates
!important this was done using old openlane v0.22 and its matching
pdk
!important known workarounds:
- a custom techlef is used where large metal spacing rules are the
only ones present to avoid violations by the router
- some odd behaviour happening when a macro has a lef view
with a non zero origin. so the power routing cell is (temporarily)
modified to have a zero origin and its placement has been shifted
which doesn't match the power routing mag.
- the old openlane doesn't generate multi spef corners. they
are generated using timing-scripts repo
2022-10-10 04:51:05 -07:00
Mohamed Hosni fa441babea
Merge branch 'efabless:caravel_redesign' into caravel_redesign 2022-10-10 01:24:24 -07:00
mo-hosni 7a7690ba10 Update housekeeping 2022-10-10 01:21:51 -07:00
mo-hosni 7e5891dd9f Update mgmt_protect 2022-10-10 01:19:40 -07:00
Tim Edwards 2459b3583e Updated all views of chip_io and chip_io_alt based on the abstract
view of constant_block which was recently merged into the repository.
The constant_block instance positions and connections were modified
slightly to avoid routing over obstruction areas.
2022-10-09 14:20:43 -04:00
Mohamed Shalan 7538c8c776
Merge pull request #161 from efabless/chip_io_rework 2022-10-09 16:31:28 +02:00
Tim Edwards bd4f053ec1 Updated I/O layouts with constant_block instances from M. Hosni's
fork of caravel (layout .mag file not copied into this commit).
The layouts of both chip_io and chip_io_alt are believed to be
complete, but need verification (with LVS).
2022-10-08 16:48:59 -04:00
mo-hosni dde6e034e0 added constant_block view 2022-10-08 12:05:53 -07:00
Tim Edwards fd29bb3442 Generated new chip_io_alt layout to match the chip_io changes in
the previous commit.  Fixed a few minor errors in the chip_io
layout.  Waiting on layout of constant_block to finish.
2022-10-08 14:05:46 -04:00
Tim Edwards d1a3922dbb Initial commit for rework of chip_io and chip_io_alt layouts;
includes RTL change inside the padframe definition to remove one
previously unnoticed hard-wired connection between VDDIO and a
3.3V domain digital input pin.
2022-10-08 12:05:10 -04:00
mo-hosni d6ca7f9091 rehardened housekeeping after rtl update, and fixed all hold and transition violations. 2022-10-07 16:59:01 -07:00
Mohamed Hosni 5c38e38767
Merge branch 'efabless:caravel_redesign' into caravel_redesign 2022-10-07 16:52:16 -07:00
kareem 6d1d618974 reharden!: gpio_control_block
- rtl updated
~ add one column to the right to pass placement congestion
~ density adjusted (probably has no effect)
+ manually add isosubstrate layer in mag and gds from older iterations

!important still need to run dynamic simulations
!important depends on some updates to openlane
!important need to be able to recreate using newer openlane versions
2022-10-07 05:02:14 -07:00
mo-hosni 9c850bf94b rehardened housekeeping 2022-10-05 12:35:03 -07:00
mo-hosni fcc009e65a rehardeneded mgmt_protect 2022-10-05 12:26:24 -07:00
R. Timothy Edwards 69240123c0
Merge branch 'caravel_redesign' into make_CSB_a_pullup 2022-10-05 10:18:35 -04:00
kareem aaa3b863e5 reharden!: gpio_control_clock
- add met5 obs to avoid drc with the top level pdn

!important: still need to use the latest openlane to replicate
2022-10-05 07:03:11 -07:00
Tim Edwards 7276623d3c Corrected the pull-up definition and revised the CSB definition to
match the corrected defintions (namely, pull-up is configuration
0x0801, and pull-down is configuration 0x0c01).
2022-10-05 10:02:24 -04:00
Mohamed Shalan 599ee23610
Merge pull request #137 from efabless/fix_caravan_gpio_default
Changed gpio_defaults_block_14 to gpio_defaults_block_25
2022-10-04 19:03:46 +02:00
R. Timothy Edwards cda2c87ae8
Merge branch 'caravel_redesign' into make_CSB_a_pullup 2022-10-03 17:39:24 -04:00
Tim Edwards dd6088e013 Corrected the instance name of the topmost GPIO defaults block on
the left hand side of caravan from gpio_defaults_block_14 to
gpio_defaults_block_25.  Otherwise, the script that generates the
custom user configuration won't be able to change the defaults
for GPIO 25.
2022-09-28 15:36:24 -04:00
Tim Edwards aba145e0e2 Made modifications in support of changing the hard-coded default
configuration of GPIO 3 (CSB) from a standard input to a weak
pull-up input.
2022-09-27 20:58:57 -04:00
kareem 85f7f86c4e reharden!: gpio_control_block
- high level changes:
* add larger buffers on output ports
* add buffers on input ports
* adjust sdc file increasing output load and setting a high transition

- detailed changes:
* add interactive script for openlane where the order of events is a bit shuffled
	- to add obstruction before pdn
	- to manually insert buffers on some ports
	- to manually remove buffers inserted by synthesis on for example serial_clock_out
* change openlane config adding extra row and columns to increase the space and fit the
added buffers
* change config to enable buffering
* increase density for better placement?
* change the cell exclude list. some excluded cells didn't make sense
* ef decap cells break dynamic sims?
* add custom pdn script for to duplicate the old pdn

- misc changes:
* fix openlane makefile to properly detect interactive script

!important still need to run dynamic simulations
!important depends on some updates to openlane
2022-09-27 07:09:26 -07:00
kareem c1e0d5ba06 openlane!: reharden gpio_control_block
update gpio_control_block config for new openlane versions:
- disable `SYNTH_BUFFERING` and `SYNTH_SIZING` to limit the design size
and fit the floorplan
- change `SYNTH_STRATEGY` to `AREA 0` to minimize design cells
- disable `PL_RESIZER_TIMING_OPTIMIZATIONS` and
enable `GLB_RESIZER_TIMING_OPTIMIZATIONS`
- remove `FP_IO_*` and replace them with `FP_DEF_TEMPLATE` for io placement
- set `DECAP_CELL` to not use ef decaps.. i think that was for simulations?
- enable some turned off `QUIT_*` variables
- replace deprecated variables such as `GLB_RT_*`
- customize `pdn.tcl` to force pdn straps to follow the old pattern
- replace `$script_dir` with `$::env(DESIGN_DIR)`

!IMPORTANT - still need to run dynamic simulations
2022-09-14 11:06:23 -07:00
Tim Edwards 1b4637dbb7 Merge branch 'main' into fix_serial_loader_data_timing
Merging latest changes from main branch into this fix.
2022-09-02 10:02:36 -04:00
sto6 9949306c42
issue-105: caravel & caravan.mag: relabel top-level v*_core power nets (label PLUS underlying met5); (#110)
tweak blackbox lvs scripts for very fast extract; update spi/lvs/*.spice.
The .spice (once propagated to caravel-lite AND caravel-lite embed in mpw_precheck docker)
will pass the consistency check.

Co-authored-by: Risto Bell <rb@efabless.com>
2022-08-26 23:03:00 -07:00
kareem ac1928a45b harden: gpio_control_block with updated rtl
TODO: run full verification
2022-08-15 02:29:01 -07:00
R. Timothy Edwards d882f42803
Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. (#90)
* Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds.
This commit does the following:
(1) Corrects the xschem simple_por schematic to separate the 1.8V and 3.3V grounds.
(2) Corrects the xschem simple_por symbol to separate the 1.8V and 3.3V grounds.
(3) Corrects the xschem testbench to connect to both grounds of simple_por.
(4) Corrects the simple_por layout to remove the 1.8V logic from the
    3.3V ground and connect it instead to the 1.8V ground.
(5) Extends the top-level power routing of caravel and caravan to
    make a better connection to the simple_por 1.8V ground.
(6) Adds an LVS script to properly check the simple_por layout against the
    xschem-generated schematic netlist.

NOTE: None of these modifications change the function of any circuit.  The
1.8V and 3.3V ground nets are only logically separated in the netlists but
share the substrate.  This fix cleanly defines the 1.8V and 3.3V grounds
within the simple_por, where they were previously mingled.  It also ensures
that the full LVS for caravel and caravan can now include the simple_por at
the transistor level and still pass.

* Updated the GDS of simple_por (previously did not remove GDS_FILE
from the .mag file and so it just overwrote the original GDS file
with itself).

* Corrected a route to simple_por in the top level of both caravel
and caravan that was shorting to the extra metals put on top of
the substrate contact across the top (bottom, in the top level)
of the simple_por layout.
2022-05-08 22:51:29 -07:00
Marwan Abbas 6cfedf89a2
fixed caravel netlist to use the 1803 defaults block (#94)
Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-05-03 10:36:11 -07:00
R. Timothy Edwards b2089fe9eb
Corrected the gpio_control_block so that the user_gpio_out signal (#89)
does not pass through an inverter, so that the input can remain
unconnected.  Rewired the existing implementation to use an
alternative gate that has an inverting input so that the
user_gpio_out signal can be left undriven when the GPIOs are in
the management enable state.  This is a simple logic refactoring
and does not change the logic function.  The manual rewiring has
been confirmed by LVS, but at least one GL simulation should be
run to confirm that the logic function remains the same as before.
2022-04-25 11:27:41 -07:00
R. Timothy Edwards ad8d168555
Corrects four signal routes which were missing from the caravan top level (#88)
* Corrects four signals which were missing from the caravan top level
(management output and output enable to GPIO 0 and 1---these errors
would have prevented the houskeeping SPI from working on caravel).
Corrected RTL verilog (source of the error), GL verilog, and layout.

* Apply automatic changes to Manifest and README.rst

Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
2022-04-25 08:50:55 -07:00
Mitch Bailey 21d44910b4
Fix verilog gpio_defaults_block replacement for gpio 0-4 (#87)
* Create lvs-cvc.rst

* user_project_analog_wrapper -> user_analog_project_wrapper

* Added table

* Update lvs-cvc.rst

* Create lvs_cvc_mpw4.rst

Initial steps for LVS and CVC-RV for MPW-4 slot-002

* Update lvs_cvc_mpw4.rst

diode and short errors

* daily progress

`simple_por` changes to `caravel.v`

* Update lvs_cvc_mpw4.rst

* Changed int (truncate) to round to correct gpio_default error.

* Replace gpio_defaults_block for gpio 0-4 correctly.
Remove old versions of gpio_defaults_block 0403 and 1803.

* Removed local CVC-RV docs not ready for commit.
2022-04-23 17:57:34 -07:00
R. Timothy Edwards 2741111106
Quick fix to a layout route for DRC (#84)
* Quick fix to a route that was hand-corrected from an Openlane
short but which is just shy of the minimum width for metal4.

* Apply automatic changes to Manifest and README.rst

Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
2022-04-22 15:10:31 -07:00
R. Timothy Edwards 99518acd15
Numerous bug fixes, ending in clean full LVS for both caravel and caravan. (#76)
* (1) Modified the .magicrc file to set a default for PDK if not set in the
environment.  (2) Fixed the user ID programming layout to not leave holes
behind when the script moves the vias around (similar to the handling of
the GPIO defaults block).  (3) Added substrate isolation to gpio_control_block
and fixed the path references to the standard cells.  (4) Fixed the four
missing routes on the Caravan top level.  (5) Reinstated the large rendered
labels for the pads on both caravel and caravan.  (6) Corrected the top
level gate-level netlist for caravan to add the missing pins to the
management core wrapper.  (7) Did the same for the caravan top level RTL.
(8) Created scripts to run full LVS including extracting the management
core wrapper and reading all gate-level verilog submodules.  (9) Moved all
of the LVS scripts to the scripts directory.

* Apply automatic changes to Manifest and README.rst

* Made the changes from pull request #73 as they did not get merged
successfully, and if merged now they will generate conflicts with
this pull request in scripts/set_user_id.py.  So it's easier to
just manually add them to this pull request.

* Apply automatic changes to Manifest and README.rst

Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
2022-04-19 19:05:27 -07:00
Kareem Farid 9ddb806293
gpio_control_block constrains fix (#69)
Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 11:50:54 -07:00
R. Timothy Edwards 71600440bc
Caravan top lvs (#67)
* - update caravan configuration
* change correct gpio_default blocks instance names
* implement powerrouting work around
* place spare logic blocks
* keep the history of runs and sym link last/final one

* - update caravan mag, def and gl views
- add fake power routing cell in the rtl as a placeholder for openlane
  to prevent routing on that cell
- fix some syntax errors in chip_io_alt
- match simple_por lef pins with mag by regenerating it

* Apply automatic changes to Manifest and README.rst

* add caravan power routing lef

* - update mag and def view of caravan
- add_macro_placement for fake cell

* Added back the power routing to Caravan, fixed DRC errors, ran LVS,
corrected placement of isolated substrate regions, and replaced the
signal routing for the analog lines.  Be aware that merging with
main may cause issues with the mgmt_protect.mag file and its
subcells mprj2_logic_high.mag and mprj_logic_high.mag.  It may be
worth cherry-picking the files to merge and exclude those layouts.

Co-authored-by: kareem <kareem.farid@efabless.com>
Co-authored-by: kareefardi <kareefardi@users.noreply.github.com>
Co-authored-by: Jeff DiCorpo <42048757+jeffdi@users.noreply.github.com>
2022-04-14 15:05:16 -07:00
Tim Edwards c52cd9b1e5 Added other blocks that were modified to put in the isolated
substrate regions, although this does not completely resolve
the substrate-related LVS error.
2022-04-09 14:29:19 -04:00
Tim Edwards 680353f7a7 This corrects a shorted net in the caravel top level layout.
Still evaluating why the layout does not pass LVS like it did
previously, although all current LVS errors appear to be related
to magic's extraction of the isolated substrates, and do not
imply functional issues.  Also, LVS has only been done on the
top level.
2022-04-09 14:23:19 -04:00
Kareem Farid c84e1393e7
updates to top level caravel (#59)
* REVERT ME: temporarily match simple_por pin in verilog with lef

* - update configs
- add patch file for power routing def

* - update the following caravel toplevel views
    - gl
    - mag
    - def
- add caravel power routing def

* Apply automatic changes to Manifest and README.rst

* update gl mag and def for caravel

* Revert "REVERT ME: temporarily match simple_por pin in verilog with lef"

This reverts commit b70c27c69f.

* update caravel gds

* Apply automatic changes to Manifest and README.rst

* Added text and logo cells back into the caravel top level.  Put an
isolated ground marker layer on the xres_buf layout.  Corrected
the power supply pin names on the gate level verilog netlist of
simple_por in caravel.v.  Updated the copyright block text.
Corrected DRC errors in the top level routing.

Co-authored-by: Tim Edwards <tim@opencircuitdesign.com>
2022-04-08 09:31:33 -07:00
Kareem Farid dcebeed7e7
Mgmt protect update (#58)
* - add openlane patch file to for input buffering workaround
- update configuration of mgmt protect

* mgmt_protect updated

* mgmt_protect updated

* remove some via3 to fix power shorts

Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-08 09:29:49 -07:00
Kareem Farid e3b9a99154
- update gpio_control_block config (#57)
- update gpio_control_block views
- gitignore gds/*gds
2022-04-08 09:27:51 -07:00
Marwan Abbas e9f023f9fa
Introduction of PDK variable (#39)
* added PDK_VARIENT variable

* changed variable name to PDK

* resolve issue

Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-08 09:05:58 -07:00
Jeff DiCorpo 5d8b579b6c
Merge pull request #49 from efabless/fix_user_id_prog
This commit fixes the issue with the user ID programming block not
2022-03-22 09:36:06 -07:00
Tim Edwards 53abff5bbf This commit fixes the issue with the user ID programming block not
getting changed by "make ship" because the build is done in a place
where the path pointer to the user_id_programming GDS still points
back to the original caravel repository, not the user project
repository.  The user_id_programming GDS was removed (no longer used),
the user_id_programming.mag file was modified to remove the path
pointer to the GDS, and the set_user_id.py script was modified to
make changes directly to the user_id_programming.mag file instead of
the GDS.  An additional method was added to the set_user_id.py script
to modify the gate-level verilog/gl/user_id_programming.v to make
the user ID correct for gate-level testbench simulations.
2022-03-22 10:25:25 -04:00
D. Mitch Bailey 35781987e1 Correct gpio_defaults_block_34 instance name in caravel.mag 2022-03-14 15:04:14 -07:00
Tim Edwards 1b3fe4379c Corrected the placement of the isosub layer in the layouts so that
it is exactly overlapping;  this resolves issues with LVS.  Also:
Corrected the references to the OpenLane/ path in the .mag files
by changing them to the canonical $PDKPATH reference.
2021-12-24 22:22:23 -05:00
manarabdelaty e408d08f93 [DATA] Update gpio_control_block 2021-12-24 22:53:42 +02:00
manarabdelaty 06f05bd296 [DATA] Update mgmt_protect block (lvs clean mag/gds) 2021-12-24 22:19:00 +02:00
manarabdelaty 0225f6b69c [DATA] Update mgmt_core mag/gds to add isosubstrate on the mgmt_protect_hv 2021-12-24 21:51:25 +02:00
manarabdelaty 981043cb7b [DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells 2021-12-24 21:06:58 +02:00
Tim Edwards 5f563c3f4f Corrected a statement in the LVS scripts in the mag/ directory that
is Makefile syntax, not bash syntax, and will cause the script to
produce an incorrect LVS result without generating a syntax error.
2021-12-17 22:27:32 -05:00
Tim Edwards b9fdac94ff Corrected a typo in the run_chip_io_alt_lvs.sh script. 2021-12-08 10:06:50 -05:00
Tim Edwards 75f4e49a99 Removed two floating metal2 rectangles from chip_io_alt. 2021-12-08 10:00:57 -05:00
Tim Edwards 8cac89ec74 Changed the user project wrapper and user analog project wrapper
to be abstract views, and modified the LVS scripts accordingly
(they no longer need a special version of the netgen setup
script).  LVS was verified on both caravel and caravan using this
setup.
2021-12-07 22:21:49 -05:00
Tim Edwards 489bddcf98 Two more changes: (1) Correction to chip_io_alt.v RTL verilog to
match what was done earlier on chip_io.v, and (2) Corrected a
set of four labels in chip_io_alt.mag which had been rotated,
causing an error in LVS.
2021-12-07 17:16:44 -05:00
Tim Edwards 624317bc3f Corrected the missing port designation on porb_h in chip_io.mag
and chip_io_alt.mag.
2021-12-07 12:38:18 -05:00
Tim Edwards 79828c00b3 Revised the LVS run scripts to use $PDK_ROOT instead of a hard-
coded path.
2021-12-07 10:32:22 -05:00
Tim Edwards c3fc004072 Corrected an error in verilog/gl/chip_io_alt.v, which was missing
connections to the core side VCCD1 and VSSD1 on the clamped3 pads.
Also added scripts for running LVS on chip_io to the mag/ directory,
and revised the scripts so that they will only re-run extraction if
there is no netlist file in the mag/ directory.
2021-12-07 10:06:35 -05:00
manarabdelaty bd88221d17 [DATA] Update caravel_clocking 2021-12-07 13:36:56 +02:00