mirror of https://github.com/efabless/caravel.git
Initial commit for rework of chip_io and chip_io_alt layouts;
includes RTL change inside the padframe definition to remove one previously unnoticed hard-wired connection between VDDIO and a 3.3V domain digital input pin.
This commit is contained in:
Tim Edwards
parent
7b271a7808
commit
d1a3922dbb
13952
mag/chip_io.mag
13952
mag/chip_io.mag
File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,76 @@
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magic
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tech sky130A
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magscale 1 2
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timestamp 1665238917
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<< checkpaint >>
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rect 675407 99896 675887 115709
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<< metal1 >>
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rect 675682 113371 675734 115709
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rect 675586 112665 675638 112671
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rect 675586 112487 675638 112493
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rect 675490 109630 675542 109636
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rect 675490 109452 675542 109458
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rect 675492 101631 675540 109452
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rect 675588 108347 675636 112487
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rect 675586 108341 675638 108347
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rect 675586 108163 675638 108169
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rect 675490 101625 675542 101631
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rect 675490 101567 675542 101573
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rect 675492 100265 675540 101567
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rect 675588 100462 675636 108163
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rect 675586 100456 675638 100462
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rect 675586 100278 675638 100284
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rect 675588 100265 675636 100278
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rect 675682 99896 675734 113199
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<< via1 >>
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rect 675682 113199 675734 113371
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rect 675586 112493 675638 112665
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rect 675490 109458 675542 109630
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rect 675586 108169 675638 108341
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rect 675490 101573 675542 101625
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rect 675586 100284 675638 100456
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<< metal2 >>
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rect 675676 113311 675682 113371
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rect 675407 113255 675682 113311
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rect 675676 113199 675682 113255
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rect 675734 113311 675740 113371
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rect 675734 113255 675887 113311
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rect 675734 113199 675740 113255
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rect 675407 112665 675887 112667
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rect 675407 112611 675586 112665
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rect 675580 112493 675586 112611
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rect 675638 112611 675887 112665
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rect 675638 112493 675644 112611
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rect 675407 109630 675887 109631
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rect 675407 109575 675490 109630
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rect 675484 109458 675490 109575
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rect 675542 109575 675887 109630
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rect 675542 109458 675548 109575
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rect 675407 108341 675887 108343
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rect 675407 108287 675586 108341
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rect 675580 108169 675586 108287
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rect 675638 108287 675887 108341
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rect 675638 108169 675644 108287
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rect 675407 101625 675887 101627
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rect 675407 101573 675490 101625
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rect 675542 101573 675887 101625
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rect 675407 101571 675887 101573
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rect 675580 100339 675586 100456
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rect 675407 100284 675586 100339
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rect 675638 100339 675644 100456
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rect 675638 100284 675887 100339
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rect 675407 100283 675887 100284
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<< labels >>
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rlabel metal2 s 675407 113255 675887 113311 8 mprj_pads.area1_io_pad\[0\]/ENABLE_VDDA_H
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port 14 nsew signal input
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rlabel metal2 s 675407 100283 675887 100339 8 mprj_pads.area1_io_pad\[0\]/TIE_LO_ESD
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port 18 nsew signal output
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rlabel metal2 s 675407 108287 675887 108343 8 mprj_pads.area1_io_pad\[0\]/ENABLE_INP_H
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port 15 nsew signal input
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rlabel metal2 s 675407 112611 675887 112667 8 mprj_pads.area1_io_pad\[0\]/ENABLE_VSWITCH_H
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port 25 nsew signal input
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rlabel metal2 s 675407 101571 675887 101627 8 mprj_pads.area1_io_pad\[0\]/TIE_HI_ESD
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port 17 nsew signal output
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rlabel metal2 s 675407 109575 675887 109631 8 mprj_pads.area1_io_pad\[0\]/HLD_H_N
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port 9 nsew signal input
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<< end >>
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@ -104,14 +104,13 @@ module chip_io(
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inout [`MPRJ_IO_PADS-10:0] mprj_analog_io
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);
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// To be considered: Master hold signal on all user pads (?)
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// For now, set holdh_n to 1 (NOTE: This is in the 3.3V domain)
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// To be considered: Master hold signal on all user pads (?)
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// For now, set holdh_n to 1 internally (NOTE: This is in the
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// VDDIO 3.3V domain)
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// and setting enh to porb_h.
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wire [`MPRJ_IO_PADS-1:0] mprj_io_hldh_n;
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wire [`MPRJ_IO_PADS-1:0] mprj_io_enh;
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assign mprj_io_hldh_n = {`MPRJ_IO_PADS{vddio}};
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assign mprj_io_enh = {`MPRJ_IO_PADS{porb_h}};
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wire analog_a, analog_b;
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@ -395,7 +394,6 @@ module chip_io(
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.io(mprj_io),
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.io_out(mprj_io_out),
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.oeb(mprj_io_oeb),
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.hldh_n(mprj_io_hldh_n),
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.enh(mprj_io_enh),
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.inp_dis(mprj_io_inp_dis),
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.ib_mode_sel(mprj_io_ib_mode_sel),
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@ -140,13 +140,12 @@ module chip_io_alt #(
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wire analog_a, analog_b;
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wire vddio_q, vssio_q;
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// To be considered: Master hold signal on all user pads (?)
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// For now, set holdh_n to 1 (NOTE: This is in the 3.3V domain)
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// and setting enh to porb_h.
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wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_hldh_n;
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// To be considered: Master hold signal on all user pads (?)
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// For now, set holdh_n to 1 internally (NOTE: This is in the
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// VDDIO 3.3V domain) and setting enh to porb_h.
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wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_enh;
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assign mprj_io_hldh_n = {`MPRJ_IO_PADS{vddio}};
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assign mprj_io_enh = {`MPRJ_IO_PADS{porb_h}};
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// Instantiate power and ground pads for management domain
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@ -469,7 +468,6 @@ module chip_io_alt #(
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mprj_io[`MPRJ_IO_PADS_1-ANALOG_PADS_1-1:0]}),
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.io_out(mprj_io_out),
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.oeb(mprj_io_oeb),
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.hldh_n(mprj_io_hldh_n),
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.enh(mprj_io_enh),
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.inp_dis(mprj_io_inp_dis),
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.ib_mode_sel(mprj_io_ib_mode_sel),
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@ -48,7 +48,6 @@ module mprj_io #(
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inout [TOTAL_PADS-1:0] io,
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input [TOTAL_PADS-1:0] io_out,
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input [TOTAL_PADS-1:0] oeb,
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input [TOTAL_PADS-1:0] hldh_n,
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input [TOTAL_PADS-1:0] enh,
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input [TOTAL_PADS-1:0] inp_dis,
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input [TOTAL_PADS-1:0] ib_mode_sel,
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@ -65,7 +64,8 @@ module mprj_io #(
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inout [TOTAL_PADS-10:0] analog_noesd_io
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);
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wire [TOTAL_PADS-1:0] loop1_io;
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wire [TOTAL_PADS-1:0] loop0_io; // Internal loopback to 3.3V domain ground
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wire [TOTAL_PADS-1:0] loop1_io; // Internal loopback to 3.3V domain power
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wire [6:0] no_connect_1a, no_connect_1b;
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wire [1:0] no_connect_2a, no_connect_2b;
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@ -76,11 +76,11 @@ module mprj_io #(
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`endif
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.OUT(io_out[AREA1PADS - 1:0]),
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.OE_N(oeb[AREA1PADS - 1:0]),
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.HLD_H_N(hldh_n[AREA1PADS - 1:0]),
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.HLD_H_N(loop1_iop[AREA1PADS - 1:0]),
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.ENABLE_H(enh[AREA1PADS - 1:0]),
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.ENABLE_INP_H(loop1_io[AREA1PADS - 1:0]),
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.ENABLE_INP_H(loop0_io[AREA1PADS - 1:0]),
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.ENABLE_VDDA_H(porb_h),
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.ENABLE_VSWITCH_H(loop1_io[AREA1PADS - 1:0]),
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.ENABLE_VSWITCH_H(loop0_io[AREA1PADS - 1:0]),
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.ENABLE_VDDIO(vccd_conb[AREA1PADS - 1:0]),
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.INP_DIS(inp_dis[AREA1PADS - 1:0]),
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.IB_MODE_SEL(ib_mode_sel[AREA1PADS - 1:0]),
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@ -96,8 +96,8 @@ module mprj_io #(
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.PAD_A_ESD_1_H(),
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.IN(io_in[AREA1PADS - 1:0]),
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.IN_H(io_in_3v3[AREA1PADS - 1:0]),
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.TIE_HI_ESD(),
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.TIE_LO_ESD(loop1_io[AREA1PADS - 1:0])
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.TIE_HI_ESD(loop1_io[AREA1PADS - 1:0]),
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.TIE_LO_ESD(loop0_io[AREA1PADS - 1:0])
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);
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sky130_ef_io__gpiov2_pad_wrapped area2_io_pad [TOTAL_PADS - AREA1PADS - 1:0] (
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@ -107,11 +107,11 @@ module mprj_io #(
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`endif
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.OUT(io_out[TOTAL_PADS - 1:AREA1PADS]),
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.OE_N(oeb[TOTAL_PADS - 1:AREA1PADS]),
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.HLD_H_N(hldh_n[TOTAL_PADS - 1:AREA1PADS]),
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.HLD_H_N(loop1_io[TOTAL_PADS - 1:AREA1PADS]),
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.ENABLE_H(enh[TOTAL_PADS - 1:AREA1PADS]),
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.ENABLE_INP_H(loop1_io[TOTAL_PADS - 1:AREA1PADS]),
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.ENABLE_INP_H(loop0_io[TOTAL_PADS - 1:AREA1PADS]),
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.ENABLE_VDDA_H(porb_h),
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.ENABLE_VSWITCH_H(loop1_io[TOTAL_PADS - 1:AREA1PADS]),
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.ENABLE_VSWITCH_H(loop0_io[TOTAL_PADS - 1:AREA1PADS]),
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.ENABLE_VDDIO(vccd_conb[TOTAL_PADS - 1:AREA1PADS]),
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.INP_DIS(inp_dis[TOTAL_PADS - 1:AREA1PADS]),
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.IB_MODE_SEL(ib_mode_sel[TOTAL_PADS - 1:AREA1PADS]),
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@ -127,8 +127,8 @@ module mprj_io #(
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.PAD_A_ESD_1_H(),
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.IN(io_in[TOTAL_PADS - 1:AREA1PADS]),
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.IN_H(io_in_3v3[TOTAL_PADS - 1:AREA1PADS]),
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.TIE_HI_ESD(),
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.TIE_LO_ESD(loop1_io[TOTAL_PADS - 1:AREA1PADS])
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.TIE_HI_ESD(loop1_io[TOTAL_PADS - 1:AREA1PADS]),
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.TIE_LO_ESD(loop0_io[TOTAL_PADS - 1:AREA1PADS])
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);
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endmodule
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