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Fix verilog gpio_defaults_block replacement for gpio 0-4 (#87) 

* Create lvs-cvc.rst

* user_project_analog_wrapper -> user_analog_project_wrapper

* Added table

* Update lvs-cvc.rst

* Create lvs_cvc_mpw4.rst

Initial steps for LVS and CVC-RV for MPW-4 slot-002

* Update lvs_cvc_mpw4.rst

diode and short errors

* daily progress

`simple_por` changes to `caravel.v`

* Update lvs_cvc_mpw4.rst

* Changed int (truncate) to round to correct gpio_default error.

* Replace gpio_defaults_block for gpio 0-4 correctly.
Remove old versions of gpio_defaults_block 0403 and 1803.

* Removed local CVC-RV docs not ready for commit.
This commit is contained in:
Mitch Bailey 2022-04-24 09:57:34 +09:00 committed by GitHub
parent 2741111106
commit 21d44910b4
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GPG Key ID: 4AEE18F83AFDEB23
3 changed files with 16 additions and 3027 deletions
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1512
mag/gpio_defaults_block_0403.mag
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1510
mag/gpio_defaults_block_1803.mag
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21
scripts/gen_gpio_defaults.py
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@ -362,7 +362,8 @@ if __name__ == '__main__':
# Do the same to the top gate-level verilog
instrex = re.compile('[ \t]*(gpio_defaults_block_?[0-9]*)[ \t]+gpio_defaults_block_([0-9]+)')
inst1rex = re.compile('[ \t]*(gpio_defaults_block_?[0-9]*)[ \t]+.?gpio_defaults_block_([0-9]+).([0-9]+)')
inst2rex = re.compile('[ \t]*(gpio_defaults_block_?[0-9]*)[ \t]+gpio_defaults_block_([0-9]+)')
if testmode:
print('Test only: Caravel top gate-level verilog:')
@ -370,10 +371,15 @@ if __name__ == '__main__':
vlines = ifile.read().splitlines()
outlines = []
for vline in vlines:
imatch = instrex.match(vline)
imatch = inst1rex.match(vline)
if imatch:
gpioidx = int(imatch.group(2)) + int(imatch.group(3))
else:
imatch = inst2rex.match(vline)
if imatch:
gpioidx = int(imatch.group(2))
if imatch:
gpioname = imatch.group(1)
gpioidx = int(imatch.group(2))
cellname = cellsused[gpioidx]
if cellname:
outlines.append(re.sub(gpioname, cellname, vline, 1))
@ -434,10 +440,15 @@ if __name__ == '__main__':
vlines = ifile.read().splitlines()
outlines = []
for vline in vlines:
imatch = instrex.match(vline)
imatch = inst1rex.match(vline)
if imatch:
gpioidx = int(imatch.group(2)) + int(imatch.group(3))
else:
imatch = inst2rex.match(vline)
if imatch:
gpioidx = int(imatch.group(2))
if imatch:
gpioname = imatch.group(1)
gpioidx = int(imatch.group(2))
cellname = cellsused[gpioidx]
if cellname:
outlines.append(re.sub(gpioname, cellname, vline, 1))