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Final1.1

v0.1-alpha

v0.2-alpha

v0.3-alpha

v1.1.0

v1.1.525

v1.1.541

v1.2.0

Mono Color

• 079e6f2fca [core] add new syntax to support from_pin and to_pin for internal driver in clock network tangxifan 2024-07-10 14:28:28 -0700
• 215de8eb93 [core] code format tangxifan 2024-07-10 14:17:22 -0700
• f5ba43e392 [core] fixed a bug where rst internal net is used to wire global ports of fpga fabric in verilog testbench tangxifan 2024-07-10 14:16:24 -0700
• 977283dd34 [core] typo tangxifan 2024-07-10 14:12:49 -0700
• af996e563e [test] add a new test to validate reset generated by internal driver through programmable clock network tangxifan 2024-07-10 14:11:06 -0700
• 213914e4ac [core] code format tangxifan 2024-07-10 12:23:57 -0700
• 48e159dd8d [core] fixed a bug where internal clock will be wired to fpga input pins in verilog testbenches tangxifan 2024-07-10 12:23:15 -0700
• c6dd33a965 [core] fixed a bug when annotating global nets on OPIN tangxifan 2024-07-10 11:59:25 -0700
• b6ff69faac [test] reworking the testcase to validate clock network with internal drivers tangxifan 2024-07-10 11:36:22 -0700
• dbe8e63f53 [test] remove unused files tangxifan 2024-07-10 10:15:47 -0700
• 77304164f4 [test] rework pin loc for k4_frac_N4_tileable_fracff_40nm to save route W tangxifan 2024-07-10 10:13:41 -0700
• 191a3d1c5e [test] update W tangxifan 2024-07-10 10:01:31 -0700
• 81fe722d98 [test] adjust W tangxifan 2024-07-09 23:49:01 -0700
• 66a77c8658
  Bump yosys from `dac5bd1` to `b08688f` dependabot[bot] 2024-07-10 06:25:00 +0000
• 96bdcc8b35 [core] code format tangxifan 2024-07-09 22:54:55 -0700
• 63f2a07c86 [test] typo tangxifan 2024-07-09 22:54:33 -0700
• 27e29f949c [core] fixed a bug where the pin idx of global net on rr graph is not well annotated tangxifan 2024-07-09 22:53:12 -0700
• a16b3df063 [test] update arch to allow clock access on CLB inputs tangxifan 2024-07-09 20:59:44 -0700
• 0f78803759 [core] fixed a bug on connecting clk/rst pins from programmable network any CLB inputs tangxifan 2024-07-09 20:47:15 -0700
• 43dbeafd44 [test] typo tangxifan 2024-07-09 20:27:28 -0700
• 9ce4b57363 [test] typo tangxifan 2024-07-09 20:25:39 -0700
• e5d146a67a [test] add new tests to validate rst on lut and clk on lut features tangxifan 2024-07-09 20:24:23 -0700
• 89e6a0483f [test] add a new benchmark to validate rst and clk on LUTs tangxifan 2024-07-09 18:45:33 -0700
• 38bb5aa906 [test] add a new benchmark to validate clock on LUT tangxifan 2024-07-09 18:42:39 -0700
• a155ea4b41
  Merge pull request #1743 from lnis-uofu/dependabot/submodules/yosys-dac5bd1 tangxifan 2024-07-09 16:15:21 -0700
• e3caff56ee
  Merge pull request #1745 from lnis-uofu/patch_update tangxifan 2024-07-09 16:14:57 -0700
• f0e168c2b3 Updated Patch Count github-actions[bot] 2024-07-09 21:54:39 +0000
• a2afdae0cc
  Merge pull request #1741 from lnis-uofu/xt_clkntwk2 tangxifan 2024-07-09 14:54:16 -0700
• f42884304a [doc] update clock network details tangxifan 2024-07-09 11:40:41 -0700
• 5efc9d0e00 [test] update golden outputs tangxifan 2024-07-08 23:24:16 -0700
• ce759d0780
  Bump vtr-verilog-to-routing from `6a4f0ca` to `ddc3ac4` dependabot[bot] 2024-07-09 06:08:29 +0000
• 092b8b038f [core] remove verbose out tangxifan 2024-07-08 22:23:37 -0700
• 04504e4d5d [core] code format tangxifan 2024-07-08 22:22:59 -0700
• 1cdb1c5995 [core] fixed a bug on calculating subtile pins tangxifan 2024-07-08 22:22:08 -0700
• 5cb104a5f6 [test] fixed a bug tangxifan 2024-07-08 22:04:40 -0700
• bf484dbc70 [doc] add perimeter cb examples on prog clk network tangxifan 2024-07-08 21:25:12 -0700
• 229adebe07 [doc] new option to write_fabric_verilog tangxifan 2024-07-08 21:06:12 -0700
• 41839bfd7a [test] typo tangxifan 2024-07-08 20:21:40 -0700
• 8a5c33b1d6 [doc] new option for perimeter cb tangxifan 2024-07-08 19:01:16 -0700
• 03c1c6f917 [test] code format tangxifan 2024-07-08 18:35:23 -0700
• c7d6c3ab61 [arch] now all the outputs of I/O can only on 1 side tangxifan 2024-07-08 18:34:13 -0700
• ad053cddca [test] code format tangxifan 2024-07-08 18:02:30 -0700
• fe06c2f2b1 [core] code format tangxifan 2024-07-08 16:18:58 -0700
• db459b0e87 [core] add verbose outputs tangxifan 2024-07-08 16:18:32 -0700
• e8f9deeeaf [core] fixed a critical bug on computing pin index for subtile in clock taps tangxifan 2024-07-08 16:12:20 -0700
• 6dde383a7f [core] debugging tangxifan 2024-07-08 16:00:18 -0700
• c30eafac9f [test] fixed a bug on clk ntwk arch where some io clocks are not tapped tangxifan 2024-07-08 15:26:16 -0700
• 8bca3d79be [core] fixed a bug where tap points of clock network cannot reach perimeter cb tangxifan 2024-07-08 15:17:24 -0700
• b50acacfba [test] fixed some bug in pin loc; Outputs are not recommend on the fringe I/O tiles tangxifan 2024-07-08 15:09:31 -0700
• 549dc6e7e6 [lib] update vtr tangxifan 2024-07-08 13:39:55 -0700
• ab454be831 [lib] update vtr tangxifan 2024-07-08 13:32:54 -0700
• 7bd60f5f7d [core] support perimeter cb when identify pins of I/Os tiles tangxifan 2024-07-08 12:39:54 -0700
• 6492d43a01 [test] add a new test to validate perimeter cb using global tile clock tangxifan 2024-07-08 11:29:20 -0700
• 48ae3691c4 [test] typo tangxifan 2024-07-08 10:57:54 -0700
• 5c9c4d93c5 [core] typo tangxifan 2024-07-08 10:46:47 -0700
• cdd477ad80 [core] remove restrictions on cb clock nodes tangxifan 2024-07-08 10:14:39 -0700
• 8449da0143 [core] typo tangxifan 2024-07-07 23:36:13 -0700
• 7d9fcc1a7b
  Bump yosys from `a739e21` to `dac5bd1` dependabot[bot] 2024-07-08 06:12:43 +0000
• 200ab2c424
  Bump vtr-verilog-to-routing from `6a4f0ca` to `d2be1c8` dependabot[bot] 2024-07-08 06:12:40 +0000
• ff56139a53 [test] debugging tangxifan 2024-07-07 23:07:51 -0700
• b0851a6299 [test] debugging tangxifan 2024-07-07 23:05:37 -0700
• 686cd761b7 [test] debugging tangxifan 2024-07-07 22:48:21 -0700
• 57a378ae59 [test] typo tangxifan 2024-07-07 22:35:14 -0700
• f784e58383 [test] typo tangxifan 2024-07-07 22:33:45 -0700
• 1a5e2392fc [test] add a new testcase to validate clock network when perimeter cb is on tangxifan 2024-07-07 22:32:13 -0700
• db12532eb8 [test] typo tangxifan 2024-07-07 21:41:39 -0700
• 7996de3fe6 [core] now support perimeter cb in programmable clock network arch tangxifan 2024-07-07 14:57:05 -0700
• 4da5150a26 [doc] update for bottom-left tile organization tangxifan 2024-07-07 14:20:26 -0700
• 439de61fd0 [test] fixed a bug on ecb support tangxifan 2024-07-07 14:00:11 -0700
• 91f8bb5841 [doc] update figures for ecb tangxifan 2024-07-07 13:40:01 -0700
• 201b2555e5 [test] code format tangxifan 2024-07-06 12:15:08 -0700
• 703cbddc9e [core] code format tangxifan 2024-07-06 12:14:57 -0700
• 43ca3ec747 [test] make arch pin loc for spread for perimeter cb validation tangxifan 2024-07-06 12:11:31 -0700
• 6024e35f89 [core] fixed a bug tangxifan 2024-07-05 18:50:14 -0700
• 1f7fbfef64 [core] fixed a bug on inter-tile connections in top module tangxifan 2024-07-05 18:19:22 -0700
• e95b264965 [core] debugging tangxifan 2024-07-05 18:08:48 -0700
• a46820b7c1 [core] add a new test for bottom-left tile grouping tangxifan 2024-07-05 18:00:37 -0700
• cca9fb4756 [core] fixed a bug on bottom left tile organization tangxifan 2024-07-05 17:55:19 -0700
• 46d916f0a0 [core] fixed the bugs in fabric tile build-up tangxifan 2024-07-05 16:59:08 -0700
• 5e89b950ed [lib] update vtr tangxifan 2024-07-05 13:41:38 -0700
• a41f437109 [core] now netlist look ok tangxifan 2024-07-05 12:36:47 -0700
• 283aa3a1c9 [core] debug tangxifan 2024-07-05 12:21:17 -0700
• f2506598a9 [lib] update vtr tangxifan 2024-07-05 12:20:49 -0700
• 36c0cfe645 [lib] update vtr tangxifan 2024-07-05 12:14:14 -0700
• 46e3b4b071 [core] debug tangxifan 2024-07-05 11:50:41 -0700
• e5d75cc51e [lib] update vtr tangxifan 2024-07-05 11:47:04 -0700
• fdbc427f70 [core] debug tangxifan 2024-07-05 11:17:05 -0700
• f6adca1545 [core] fixed a bug tangxifan 2024-07-05 11:02:01 -0700
• ba1482f533 [lib] update vtr tangxifan 2024-07-05 11:01:31 -0700
• b6e89b8943 [lib] update vtr tangxifan 2024-07-05 10:52:35 -0700
• 1dc602a849 [core] syntax tangxifan 2024-07-05 10:38:26 -0700
• 266c2686d4 [core] adapt new gsb coordinate system tangxifan 2024-07-05 10:32:33 -0700
• 47ba57a27c [lib] update vtr tangxifan 2024-07-05 10:16:50 -0700
• e34a808528
  Bump vtr-verilog-to-routing from `6a4f0ca` to `589b6bc` dependabot[bot] 2024-07-05 06:25:56 +0000
• fe73e03c69 [test] changing arch tangxifan 2024-07-04 21:31:43 -0700
• 4064c29d49 [test] updating arch for perimeter cb tangxifan 2024-07-04 21:23:15 -0700
• 5865aebf93 [test] add new arch tangxifan 2024-07-04 21:12:26 -0700
• 1f8c2436ef [core] now constant_undriven_inputs are force to enable when perimeter_cb is selected tangxifan 2024-07-04 20:46:38 -0700
• 72ee39f178 [core] add new command line option 'constant_undriven_inputs' tangxifan 2024-07-04 20:39:02 -0700
• 4e21bbb3f1 [core] now support constant undriven local wires in verilog writer tangxifan 2024-07-04 20:32:56 -0700