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[test] typo

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tangxifan 2024-07-08 10:57:54 -07:00
parent 5c9c4d93c5
commit 48ae3691c4
1 changed files with 1 additions and 1 deletions
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openfpga_flow/openfpga_arch/k4_N4_40nm_ClkNtwk_registerable_io_cc_openfpga.xml
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@ -173,7 +173,7 @@
<segment name="L4" circuit_model_name="chan_segment"/>
</routing_segment>
<tile_annotations>
<global_port name="clk" is_clock="true" default_val="0" clk_tree_name="clk_tree_2lvl">
<global_port name="clk" is_clock="true" default_val="0" clock_arch_tree_name="clk_tree_2lvl">
<tile name="clb" port="clk" x="-1" y="-1"/>
<tile name="io_top" port="clk" x="-1" y="-1"/>
<tile name="io_right" port="clk" x="-1" y="-1"/>