[test] typo
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@ -27,7 +27,7 @@ openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml
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openfpga_verilog_testbench_options=--explicit_port_mapping
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[ARCHITECTURES]
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arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_ecb_tileable_TileOrgzBr_40nm.xml
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arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_ecb_tileable_TileOrgzBl_40nm.xml
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[BENCHMARKS]
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bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
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@ -1 +1 @@
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<tiles style="top_left"/>
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<tiles style="bottom_left"/>
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