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Merge pull request #1741 from lnis-uofu/xt_clkntwk2 

Support Connection Blocks on Perimeter Tiles
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tangxifan 2024-07-09 14:54:16 -07:00 committed by GitHub
parent 27d23399b5 f42884304a
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155 changed files with 17189 additions and 15451 deletions
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17
docs/source/manual/arch_lang/addon_vpr_syntax.rst
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@ -88,6 +88,23 @@ Layout
.. warning:: Do NOT enable ``shrink_boundary`` if you are not using the tileable routing resource graph generator!
.. option:: perimeter_cb="<bool>"
Allow connection blocks to appear around the perimeter programmable block (mainly I/Os). This is designed to enhance routability of I/Os on perimeter. Also strongly recommended when programmable clock network is required to touch clock pins on I/Os. As illustrated in :numref:`fig_perimeter_cb`, routing tracks can access three sides of each I/O when perimeter connection blocks are created.
By default, it is ``false``.
.. warning:: When enabled, please only place outputs at one side of I/Os. For example, outputs of an I/O on the top side can only occur on the bottom side of the I/O tile. Otherwise, routability loss may be expected, leading to some pins cannot be reachable. Enable the ``opin2all_sides`` to recover routability loss.
.. _fig_perimeter_cb:
.. figure:: ./figures/perimeter_cb.png
:width: 100%
:alt: Impact of perimeter_cb
Impact on routing architecture when perimeter connection blocks are : (a) disabled; (b) enabled.
.. warning:: Do NOT enable ``perimeter_cb`` if you are not using the tileable routing resource graph generator!
.. option:: opin2all_sides="<bool>"
Allow each output pin of a programmable block to drive the routing tracks on all the sides of its adjacent switch block (see an illustrative example in :numref:`fig_opin2all_sides`). This can improve the routability of an FPGA fabric with an increase in the sizes of routing multiplexers in each switch block.

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19
docs/source/manual/file_formats/clock_network.rst
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@ -14,6 +14,8 @@ Using the clock network description language, users can define multiple clock ne
- A number of switch points which interconnects clock spines using programmable routing switches. See details in :ref:`file_formats_clock_network_switch_point`.
- A number of tap points which connect the clock spines to programmable blocks, e.g., CLBs. See details in :ref:`file_formats_clock_network_tap_point`.
The entry point of a clock tree must be at a valid connection block.
.. note:: Please note that the levels of a clock network will be automatically inferred from the clock spines and switch points. Clock network will be **only** built based on the width and the number of levels, as well as the tap points.
.. note:: The switch points and clock spines will be used to route a clock network. The switch points will not impact the physical clock network but only impact the configuration of the programmable routing switches in the physical clock network.
@ -45,6 +47,17 @@ Using the clock network description language, users can define multiple clock ne
An example of programmable clock network considering a 2x2 FPGA fabric
Note that when the ``perimeter_cb`` is enabled for routing architecture (See details in :ref:`addon_vpr_syntax`), clock entry point can be indeed at the fringe of FPGA fabrics. See example in :numref:`prog_clock_network_example_2x2_perimeter_cb`.
.. _fig_prog_clock_network_example_2x2_perimeter_cb:
.. figure:: figures/prog_clk_network_example_2x2_perimeter_cb.png
:width: 100%
:alt: An example of programmable clock network considering a 2x2 FPGA fabric with perimeter cb
An example of programmable clock network considering a 2x2 FPGA fabric with perimeter cb
General Settings
^^^^^^^^^^^^^^^^
@ -134,6 +147,8 @@ Clock Spine Settings
The following syntax are applicable to the XML definition tagged by ``spine``.
Note that a number of clock spines can be defined under the node ``clock_network``.
.. note:: Use coordinates of connection blocks to define the starting and ending points of clock spines.
.. option:: name="<string>"
The unique name of the clock spine. It will be used to build switch points between other clock spines.
@ -172,6 +187,8 @@ Switch Point Settings
The following syntax are applicable to the XML definition tagged by ``switch_point``.
Note that a number of switch points can be defined under each clock spine ``spine``.
.. note:: Use the coordinate of switch block to define switching points!
.. option:: tap="<string>"
Define which clock spine will be tapped from the current clock spine.
@ -292,6 +309,8 @@ For example,
where all the clock spines of the clock network ``clk_tree_0`` tap the clock pins ``clk`` of tile ``clb`` in a VPR architecture description file:
.. note:: Use the name of ``subtile`` in the ``to_pin`` when there are a number of subtiles in your tile!
.. code-block:: xml
<tile name="clb">

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13
docs/source/manual/file_formats/tile_config_file.rst
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@ -24,7 +24,7 @@ Detailed syntax are presented as follows.
Specify the style of tile organization. Can be [``top_left`` | ``top_right`` | ``bottom_left`` | ``bottom_right`` | ``custom``]
.. warning:: Currently, only ``top_left`` is supported!
.. warning:: Currently, only ``top_left`` and ``bottom_left`` are supported!
The ``top_left`` is a shortcut to define the organization for all the tiles. :numref:`fig_tile_style_top_left` shows an example of tiles in the top-left sytle, where the programmable block locates in the top-left corner of all the tiles, surrounded by two connection blocks and one switch blocks.
@ -37,3 +37,14 @@ Detailed syntax are presented as follows.
An example of top-left style of a tile in FPGA fabric
The ``bottom_left`` is a shortcut to define the organization for all the tiles. :numref:`fig_tile_style_bottom_left` shows an example of tiles in the bottom-left sytle, where the programmable block locates in the bottom-left corner of all the tiles, surrounded by two connection blocks and one switch blocks.
.. _fig_tile_style_bottom_left:
.. figure:: ./figures/tile_style_bottom_left.png
:width: 100%
:alt: An example of bottom-left style of tile
An example of bottom-left style of a tile in FPGA fabric

8
docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst
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@ -14,6 +14,14 @@ write_fabric_verilog
Specify the output directory for the Verilog netlists. For example, ``--file /temp/fabric_netlist/``
.. option:: --constant_undriven_inputs
.. note:: This option is automatically enabled when the option ``perimeter_cb`` of tileable routing resource graph is enabled (see details in :ref`addon_vpr_syntax`).
.. note:: Enable this option may shadow issues in your FPGA architecture, which causes them difficult to be found in design verification.
Use constant gnd for undriven wires in Verilog netlists. Recommand to enable when there are boundary routing tracks in FPGA fabric.
.. option:: --default_net_type <string>
Specify the default net type for the Verilog netlists. Currently, supported types are ``none`` and ``wire``. Default value: ``none``.

35
openfpga/src/annotation/annotate_rr_graph.cpp
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@ -98,7 +98,7 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx,
const vtr::Point<size_t>& gsb_range,
const size_t& layer,
const vtr::Point<size_t>& gsb_coord,
const bool& include_clock) {
const bool& perimeter_cb, const bool& include_clock) {
/* Create an object to return */
RRGSB rr_gsb;
@ -126,7 +126,6 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx,
switch (side) {
case TOP: /* TOP = 0 */
/* For the border, we should take special care */
if (gsb_coord.y() == gsb_range.y()) {
rr_gsb.clear_one_side(side_manager.get_side());
break;
@ -157,7 +156,6 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx,
break;
case RIGHT: /* RIGHT = 1 */
/* For the border, we should take special care */
if (gsb_coord.x() == gsb_range.x()) {
rr_gsb.clear_one_side(side_manager.get_side());
break;
@ -189,8 +187,7 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx,
gsb_coord.x() + 1, gsb_coord.y(), OPIN, opin_grid_side[1]);
break;
case BOTTOM: /* BOTTOM = 2*/
/* For the border, we should take special care */
if (gsb_coord.y() == 0) {
if (!perimeter_cb && gsb_coord.y() == 0) {
rr_gsb.clear_one_side(side_manager.get_side());
break;
}
@ -220,8 +217,7 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx,
gsb_coord.y(), OPIN, opin_grid_side[1]);
break;
case LEFT: /* LEFT = 3 */
/* For the border, we should take special care */
if (gsb_coord.x() == 0) {
if (!perimeter_cb && gsb_coord.x() == 0) {
rr_gsb.clear_one_side(side_manager.get_side());
break;
}
@ -333,11 +329,11 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx,
case RIGHT: /* RIGHT = 1 */
/* For the bording, we should take special care */
/* Check if TOP side chan width is 0 or not */
chan_side = TOP;
chan_side = BOTTOM;
/* Build the connection block: ipin and ipin_grid_side */
/* LEFT side INPUT Pins of Grid[x+1][y+1] */
/* LEFT side INPUT Pins of Grid[x+1][y] */
ix = rr_gsb.get_sb_x() + 1;
iy = rr_gsb.get_sb_y() + 1;
iy = rr_gsb.get_sb_y();
ipin_rr_node_grid_side = LEFT;
break;
case BOTTOM: /* BOTTOM = 2*/
@ -353,11 +349,11 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx,
case LEFT: /* LEFT = 3 */
/* For the bording, we should take special care */
/* Check if left side chan width is 0 or not */
chan_side = TOP;
chan_side = BOTTOM;
/* Build the connection block: ipin and ipin_grid_side */
/* RIGHT side INPUT Pins of Grid[x][y+1] */
/* RIGHT side INPUT Pins of Grid[x][y] */
ix = rr_gsb.get_sb_x();
iy = rr_gsb.get_sb_y() + 1;
iy = rr_gsb.get_sb_y();
ipin_rr_node_grid_side = RIGHT;
break;
default:
@ -420,6 +416,9 @@ void annotate_device_rr_gsb(const DeviceContext& vpr_device_ctx,
*/
vtr::Point<size_t> gsb_range(vpr_device_ctx.grid.width() - 1,
vpr_device_ctx.grid.height() - 1);
if (vpr_device_ctx.arch->perimeter_cb) {
gsb_range.set(vpr_device_ctx.grid.width(), vpr_device_ctx.grid.height());
}
device_rr_gsb.reserve(gsb_range);
VTR_LOGV(verbose_output, "Start annotation GSB up to [%lu][%lu]\n",
@ -434,11 +433,11 @@ void annotate_device_rr_gsb(const DeviceContext& vpr_device_ctx,
* the GSBs at the borderside correctly sort drive_rr_nodes should be
* called if required by users
*/
const RRGSB& rr_gsb =
build_rr_gsb(vpr_device_ctx,
vtr::Point<size_t>(vpr_device_ctx.grid.width() - 2,
vpr_device_ctx.grid.height() - 2),
layer, vtr::Point<size_t>(ix, iy), include_clock);
vtr::Point<size_t> sub_gsb_range(vpr_device_ctx.grid.width() - 1,
vpr_device_ctx.grid.height() - 1);
const RRGSB& rr_gsb = build_rr_gsb(
vpr_device_ctx, sub_gsb_range, layer, vtr::Point<size_t>(ix, iy),
vpr_device_ctx.arch->perimeter_cb, include_clock);
/* Add to device_rr_gsb */
vtr::Point<size_t> gsb_coordinate = rr_gsb.get_sb_coordinate();
device_rr_gsb.add_rr_gsb(gsb_coordinate, rr_gsb);

143
openfpga/src/annotation/append_clock_rr_graph.cpp
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@ -45,17 +45,25 @@ static size_t estimate_clock_rr_graph_num_chan_nodes(
*******************************************************************/
static size_t estimate_clock_rr_graph_num_nodes(const DeviceGrid& grids,
const size_t& layer,
const bool& perimeter_cb,
const bool& through_channel,
const ClockNetwork& clk_ntwk) {
size_t num_nodes = 0;
vtr::Rect<size_t> chanx_bb(1, 0, grids.width() - 1, grids.height() - 1);
if (perimeter_cb) {
chanx_bb.set_xmin(0);
chanx_bb.set_xmax(grids.width());
chanx_bb.set_ymin(0);
chanx_bb.set_ymax(grids.height());
}
/* Check the number of CHANX nodes required */
for (size_t iy = 0; iy < grids.height() - 1; ++iy) {
for (size_t ix = 1; ix < grids.width() - 1; ++ix) {
for (size_t iy = chanx_bb.ymin(); iy < chanx_bb.ymax(); ++iy) {
for (size_t ix = chanx_bb.xmin(); ix < chanx_bb.xmax(); ++ix) {
vtr::Point<size_t> chanx_coord(ix, iy);
/* Bypass if the routing channel does not exist when through channels are
* not allowed */
if ((false == through_channel) &&
(false == is_chanx_exist(grids, layer, chanx_coord))) {
(false == is_chanx_exist(grids, layer, chanx_coord, perimeter_cb))) {
continue;
}
/* Estimate the routing tracks required by clock routing only */
@ -63,13 +71,21 @@ static size_t estimate_clock_rr_graph_num_nodes(const DeviceGrid& grids,
}
}
for (size_t ix = 0; ix < grids.width() - 1; ++ix) {
for (size_t iy = 1; iy < grids.height() - 1; ++iy) {
vtr::Rect<size_t> chany_bb(0, 1, grids.width() - 1, grids.height() - 1);
if (perimeter_cb) {
chany_bb.set_xmin(0);
chany_bb.set_xmax(grids.width());
chany_bb.set_ymin(0);
chany_bb.set_ymax(grids.height());
}
for (size_t ix = chany_bb.xmin(); ix < chany_bb.xmax(); ++ix) {
for (size_t iy = chany_bb.ymin(); iy < chany_bb.ymax(); ++iy) {
vtr::Point<size_t> chany_coord(ix, iy);
/* Bypass if the routing channel does not exist when through channel are
* not allowed */
if ((false == through_channel) &&
(false == is_chany_exist(grids, layer, chany_coord))) {
(false == is_chany_exist(grids, layer, chany_coord, perimeter_cb))) {
continue;
}
/* Estimate the routing tracks required by clock routing only */
@ -151,56 +167,59 @@ static void add_rr_graph_block_clock_nodes(
static void add_rr_graph_clock_nodes(
RRGraphBuilder& rr_graph_builder, RRClockSpatialLookup& clk_rr_lookup,
const RRGraphView& rr_graph_view, const DeviceGrid& grids,
const size_t& layer, const bool& through_channel,
const size_t& layer, const bool& perimeter_cb, const bool& through_channel,
const ClockNetwork& clk_ntwk, const bool& verbose) {
/* Pre-allocate memory: Must do otherwise data will be messed up! */
clk_rr_lookup.reserve_nodes(grids.width(), grids.height(),
clk_ntwk.num_trees(), clk_ntwk.max_tree_depth(),
clk_ntwk.max_tree_width());
vtr::Rect<size_t> chanx_bb(1, 0, grids.width() - 1, grids.height() - 1);
if (perimeter_cb) {
chanx_bb.set_xmin(0);
chanx_bb.set_xmax(grids.width());
chanx_bb.set_ymin(0);
chanx_bb.set_ymax(grids.height());
}
/* Add X-direction clock nodes */
for (size_t iy = 0; iy < grids.height() - 1; ++iy) {
for (size_t ix = 1; ix < grids.width() - 1; ++ix) {
for (size_t iy = chanx_bb.ymin(); iy < chanx_bb.ymax(); ++iy) {
for (size_t ix = chanx_bb.xmin(); ix < chanx_bb.xmax(); ++ix) {
vtr::Point<size_t> chanx_coord(ix, iy);
/* Bypass if the routing channel does not exist when through channels are
* not allowed */
if ((false == through_channel) &&
(false == is_chanx_exist(grids, layer, chanx_coord))) {
(false == is_chanx_exist(grids, layer, chanx_coord, perimeter_cb))) {
continue;
}
add_rr_graph_block_clock_nodes(
rr_graph_builder, clk_rr_lookup, rr_graph_view, clk_ntwk, layer,
chanx_coord, CHANX, CHANX_COST_INDEX_START, verbose);
VTR_ASSERT(rr_graph_view.valid_node(
clk_rr_lookup.find_node(1, 0, ClockTreeId(0), ClockLevelId(0),
ClockTreePinId(0), Direction::INC)));
}
}
VTR_ASSERT(rr_graph_view.valid_node(clk_rr_lookup.find_node(
1, 0, ClockTreeId(0), ClockLevelId(0), ClockTreePinId(0), Direction::INC)));
/* Add Y-direction clock nodes */
for (size_t ix = 0; ix < grids.width() - 1; ++ix) {
for (size_t iy = 1; iy < grids.height() - 1; ++iy) {
vtr::Rect<size_t> chany_bb(0, 1, grids.width() - 1, grids.height() - 1);
if (perimeter_cb) {
chany_bb.set_xmin(0);
chany_bb.set_xmax(grids.width());
chany_bb.set_ymin(0);
chany_bb.set_ymax(grids.height());
}
for (size_t ix = chany_bb.xmin(); ix < chany_bb.xmax(); ++ix) {
for (size_t iy = chany_bb.ymin(); iy < chany_bb.ymax(); ++iy) {
vtr::Point<size_t> chany_coord(ix, iy);
/* Bypass if the routing channel does not exist when through channel are
* not allowed */
if ((false == through_channel) &&
(false == is_chany_exist(grids, layer, chany_coord))) {
(false == is_chany_exist(grids, layer, chany_coord, perimeter_cb))) {
continue;
}
add_rr_graph_block_clock_nodes(
rr_graph_builder, clk_rr_lookup, rr_graph_view, clk_ntwk, layer,
chany_coord, CHANY,
CHANX_COST_INDEX_START + rr_graph_view.num_rr_segments(), verbose);
VTR_ASSERT(rr_graph_view.valid_node(
clk_rr_lookup.find_node(1, 0, ClockTreeId(0), ClockLevelId(0),
ClockTreePinId(0), Direction::INC)));
}
}
VTR_ASSERT(rr_graph_view.valid_node(clk_rr_lookup.find_node(
1, 0, ClockTreeId(0), ClockLevelId(0), ClockTreePinId(0), Direction::INC)));
}
/********************************************************************
@ -396,19 +415,23 @@ static void try_find_and_add_clock_track2ipin_node(
const RRGraphView& rr_graph_view, const size_t& layer,
const vtr::Point<size_t>& grid_coord, const e_side& pin_side,
const ClockNetwork& clk_ntwk, const ClockTreeId& clk_tree,
const ClockTreePinId& clk_pin) {
const ClockTreePinId& clk_pin, const bool& verbose) {
t_physical_tile_type_ptr grid_type = grids.get_physical_type(
t_physical_tile_loc(grid_coord.x(), grid_coord.y(), layer));
for (std::string tap_pin_name :
clk_ntwk.tree_flatten_tap_to_ports(clk_tree, clk_pin, grid_coord)) {
VTR_LOGV(verbose, "Checking tap pin name: %s\n", tap_pin_name.c_str());
/* tap pin name could be 'io[5:5].a2f[0]' */
int grid_pin_idx = find_physical_tile_pin_index(grid_type, tap_pin_name);
if (grid_pin_idx == grid_type->num_pins) {
continue;
}
VTR_LOGV(verbose, "Found a valid pin (index=%d) in physical tile\n",
grid_pin_idx);
RRNodeId des_node = rr_graph_view.node_lookup().find_node(
layer, grid_coord.x(), grid_coord.y(), IPIN, grid_pin_idx, pin_side);
if (rr_graph_view.valid_node(des_node)) {
VTR_LOGV(verbose, "Found a valid pin in rr graph\n");
des_nodes.push_back(des_node);
}
}
@ -444,34 +467,35 @@ static std::vector<RRNodeId> find_clock_track2ipin_node(
const DeviceGrid& grids, const RRGraphView& rr_graph_view,
const t_rr_type& chan_type, const size_t& layer,
const vtr::Point<size_t>& chan_coord, const ClockNetwork& clk_ntwk,
const ClockTreeId& clk_tree, const ClockTreePinId& clk_pin) {
const ClockTreeId& clk_tree, const ClockTreePinId& clk_pin,
const bool& verbose) {
std::vector<RRNodeId> des_nodes;
if (chan_type == CHANX) {
/* Get the clock IPINs at the BOTTOM side of adjacent grids [x][y+1] */
vtr::Point<size_t> bot_grid_coord(chan_coord.x(), chan_coord.y() + 1);
try_find_and_add_clock_track2ipin_node(des_nodes, grids, rr_graph_view,
layer, bot_grid_coord, BOTTOM,
clk_ntwk, clk_tree, clk_pin);
try_find_and_add_clock_track2ipin_node(
des_nodes, grids, rr_graph_view, layer, bot_grid_coord, BOTTOM, clk_ntwk,
clk_tree, clk_pin, verbose);
/* Get the clock IPINs at the TOP side of adjacent grids [x][y] */
vtr::Point<size_t> top_grid_coord(chan_coord.x(), chan_coord.y());
try_find_and_add_clock_track2ipin_node(des_nodes, grids, rr_graph_view,
layer, top_grid_coord, TOP, clk_ntwk,
clk_tree, clk_pin);
clk_tree, clk_pin, verbose);
} else {
VTR_ASSERT(chan_type == CHANY);
/* Get the clock IPINs at the LEFT side of adjacent grids [x][y+1] */
vtr::Point<size_t> left_grid_coord(chan_coord.x() + 1, chan_coord.y());
try_find_and_add_clock_track2ipin_node(des_nodes, grids, rr_graph_view,
layer, left_grid_coord, LEFT,
clk_ntwk, clk_tree, clk_pin);
try_find_and_add_clock_track2ipin_node(
des_nodes, grids, rr_graph_view, layer, left_grid_coord, LEFT, clk_ntwk,
clk_tree, clk_pin, verbose);
/* Get the clock IPINs at the RIGHT side of adjacent grids [x][y] */
vtr::Point<size_t> right_grid_coord(chan_coord.x(), chan_coord.y());
try_find_and_add_clock_track2ipin_node(des_nodes, grids, rr_graph_view,
layer, right_grid_coord, RIGHT,
clk_ntwk, clk_tree, clk_pin);
try_find_and_add_clock_track2ipin_node(
des_nodes, grids, rr_graph_view, layer, right_grid_coord, RIGHT, clk_ntwk,
clk_tree, clk_pin, verbose);
}
return des_nodes;
@ -538,7 +562,7 @@ static void add_rr_graph_block_clock_edges(
size_t curr_edge_count = edge_count;
for (RRNodeId des_node : find_clock_track2ipin_node(
grids, rr_graph_view, chan_type, layer, chan_coord, clk_ntwk,
itree, ClockTreePinId(ipin))) {
itree, ClockTreePinId(ipin), verbose)) {
/* Create edges */
VTR_ASSERT(rr_graph_view.valid_node(des_node));
rr_graph_builder.create_edge(
@ -729,16 +753,24 @@ static int add_rr_graph_opin2clk_edges(
static void add_rr_graph_clock_edges(
RRGraphBuilder& rr_graph_builder, size_t& num_edges_to_create,
const RRClockSpatialLookup& clk_rr_lookup, const RRGraphView& rr_graph_view,
const DeviceGrid& grids, const size_t& layer, const bool& through_channel,
const ClockNetwork& clk_ntwk, const bool& verbose) {
const DeviceGrid& grids, const size_t& layer, const bool& perimeter_cb,
const bool& through_channel, const ClockNetwork& clk_ntwk,
const bool& verbose) {
vtr::Rect<size_t> chanx_bb(1, 0, grids.width() - 1, grids.height() - 1);
if (perimeter_cb) {
chanx_bb.set_xmin(0);
chanx_bb.set_xmax(grids.width());
chanx_bb.set_ymin(0);
chanx_bb.set_ymax(grids.height());
}
/* Add edges which is driven by X-direction clock routing tracks */
for (size_t iy = 0; iy < grids.height() - 1; ++iy) {
for (size_t ix = 1; ix < grids.width() - 1; ++ix) {
for (size_t iy = chanx_bb.ymin(); iy < chanx_bb.ymax(); ++iy) {
for (size_t ix = chanx_bb.xmin(); ix < chanx_bb.xmax(); ++ix) {
vtr::Point<size_t> chanx_coord(ix, iy);
/* Bypass if the routing channel does not exist when through channels are
* not allowed */
if ((false == through_channel) &&
(false == is_chanx_exist(grids, layer, chanx_coord))) {
(false == is_chanx_exist(grids, layer, chanx_coord, perimeter_cb))) {
continue;
}
add_rr_graph_block_clock_edges(rr_graph_builder, num_edges_to_create,
@ -748,13 +780,20 @@ static void add_rr_graph_clock_edges(
}
/* Add edges which is driven by Y-direction clock routing tracks */
for (size_t ix = 0; ix < grids.width() - 1; ++ix) {
for (size_t iy = 1; iy < grids.height() - 1; ++iy) {
vtr::Rect<size_t> chany_bb(0, 1, grids.width() - 1, grids.height() - 1);
if (perimeter_cb) {
chany_bb.set_xmin(0);
chany_bb.set_xmax(grids.width());
chany_bb.set_ymin(0);
chany_bb.set_ymax(grids.height());
}
for (size_t ix = chany_bb.xmin(); ix < chany_bb.xmax(); ++ix) {
for (size_t iy = chany_bb.ymin(); iy < chany_bb.ymax(); ++iy) {
vtr::Point<size_t> chany_coord(ix, iy);
/* Bypass if the routing channel does not exist when through channel are
* not allowed */
if ((false == through_channel) &&
(false == is_chany_exist(grids, layer, chany_coord))) {
(false == is_chany_exist(grids, layer, chany_coord, perimeter_cb))) {
continue;
}
add_rr_graph_block_clock_edges(rr_graph_builder, num_edges_to_create,
@ -793,7 +832,8 @@ int append_clock_rr_graph(DeviceContext& vpr_device_ctx,
/* Estimate the number of nodes and pre-allocate */
size_t orig_num_nodes = vpr_device_ctx.rr_graph.num_nodes();
size_t num_clock_nodes = estimate_clock_rr_graph_num_nodes(
vpr_device_ctx.grid, 0, vpr_device_ctx.arch->through_channel, clk_ntwk);
vpr_device_ctx.grid, 0, vpr_device_ctx.arch->perimeter_cb,
vpr_device_ctx.arch->through_channel, clk_ntwk);
vpr_device_ctx.rr_graph_builder.unlock_storage();
vpr_device_ctx.rr_graph_builder.reserve_nodes(num_clock_nodes +
orig_num_nodes);
@ -803,10 +843,10 @@ int append_clock_rr_graph(DeviceContext& vpr_device_ctx,
num_clock_nodes, (float)(num_clock_nodes / orig_num_nodes));
/* Add clock nodes */
add_rr_graph_clock_nodes(vpr_device_ctx.rr_graph_builder, clk_rr_lookup,
vpr_device_ctx.rr_graph, vpr_device_ctx.grid, 0,
vpr_device_ctx.arch->through_channel, clk_ntwk,
verbose);
add_rr_graph_clock_nodes(
vpr_device_ctx.rr_graph_builder, clk_rr_lookup, vpr_device_ctx.rr_graph,
vpr_device_ctx.grid, 0, vpr_device_ctx.arch->perimeter_cb,
vpr_device_ctx.arch->through_channel, clk_ntwk, verbose);
VTR_LOGV(verbose,
"Added %lu clock nodes to routing "
"resource graph.\n",
@ -820,7 +860,8 @@ int append_clock_rr_graph(DeviceContext& vpr_device_ctx,
vpr_device_ctx.rr_graph_builder, num_clock_edges,
static_cast<const RRClockSpatialLookup&>(clk_rr_lookup),
vpr_device_ctx.rr_graph, vpr_device_ctx.grid, 0,
vpr_device_ctx.arch->through_channel, clk_ntwk, verbose);
vpr_device_ctx.arch->perimeter_cb, vpr_device_ctx.arch->through_channel,
clk_ntwk, verbose);
VTR_LOGV(verbose,
"Added %lu clock edges to routing "
"resource graph.\n",

4
openfpga/src/annotation/route_clock_rr_graph.cpp
View File

@ -186,8 +186,6 @@ static int route_spine_taps(
const std::map<ClockTreePinId, ClusterNetId>& tree2clk_pin_map,
const ClockNetwork& clk_ntwk, const ClockTreeId& clk_tree,
const ClockSpineId& ispine, const ClockTreePinId& ipin, const bool& verbose) {
std::vector<vtr::Point<int>> spine_coords =
clk_ntwk.spine_coordinates(ispine);
size_t spine_tap_cnt = 0;
/* Route the spine-to-IPIN connections (only for the last level) */
if (clk_ntwk.is_last_level(ispine)) {
@ -195,6 +193,8 @@ static int route_spine_taps(
"Routing clock taps of spine '%s' for pin '%d' of tree '%s'...\n",
clk_ntwk.spine_name(ispine).c_str(), size_t(ipin),
clk_ntwk.tree_name(clk_tree).c_str());
std::vector<vtr::Point<int>> spine_coords =
clk_ntwk.spine_coordinates(ispine);
/* Connect to any fan-out node which is IPIN */
for (size_t icoord = 0; icoord < spine_coords.size(); ++icoord) {
vtr::Point<int> src_coord = spine_coords[icoord];

4
openfpga/src/base/openfpga_pb_pin_fixup.cpp
View File

@ -59,8 +59,8 @@ static void update_cluster_pin_with_post_routing_results(
VTR_ASSERT(class_inf.type == RECEIVER);
rr_node_type = IPIN;
}
std::vector<e_side> pin_sides =
find_physical_tile_pin_side(physical_tile, physical_pin, border_side);
std::vector<e_side> pin_sides = find_physical_tile_pin_side(
physical_tile, physical_pin, border_side, device_ctx.arch->perimeter_cb);
/* As some grid has height/width offset, we may not have the pin on any side
*/
if (0 == pin_sides.size()) {

6
openfpga/src/base/openfpga_verilog_command_template.h
View File

@ -30,6 +30,12 @@ ShellCommandId add_write_fabric_verilog_command_template(
shell_cmd.set_option_short_name(output_opt, "f");
shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING);
/* Add an option '--constant_undriven_inputs' */
shell_cmd.add_option(
"constant_undriven_inputs", false,
"Use constant gnd for undriven wires in Verilog netlists. Recommand to "
"enable when there are boundary routing tracks in FPGA fabric");
/* Add an option '--explicit_port_mapping' */
shell_cmd.add_option("explicit_port_mapping", false,
"Use explicit port mapping in Verilog netlists");

13
openfpga/src/base/openfpga_verilog_template.h
View File

@ -28,6 +28,8 @@ int write_fabric_verilog_template(T& openfpga_ctx, const Command& cmd,
CommandOptionId opt_output_dir = cmd.option("file");
CommandOptionId opt_explicit_port_mapping =
cmd.option("explicit_port_mapping");
CommandOptionId opt_constant_undriven_inputs =
cmd.option("constant_undriven_inputs");
CommandOptionId opt_include_timing = cmd.option("include_timing");
CommandOptionId opt_print_user_defined_template =
cmd.option("print_user_defined_template");
@ -56,6 +58,17 @@ int write_fabric_verilog_template(T& openfpga_ctx, const Command& cmd,
}
options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose));
options.set_compress_routing(openfpga_ctx.flow_manager().compress_routing());
/* For perimeter cb, enable the constant undriven inputs, unless it is off by
* user */
if (g_vpr_ctx.device().arch->perimeter_cb) {
options.set_constant_undriven_inputs(true);
VTR_LOG(
"Automatically enable the constant_undriven_input option as perimeter "
"connection blocks are seen in FPGA fabric\n");
} else {
options.set_constant_undriven_inputs(
cmd_context.option_enable(cmd, opt_constant_undriven_inputs));
}
return fpga_fabric_verilog(
openfpga_ctx.mutable_module_graph(),

6
openfpga/src/fabric/build_device_module.cpp
View File

@ -128,7 +128,8 @@ int build_device_module_graph(
openfpga_ctx.device_rr_gsb(), vpr_device_ctx.rr_graph,
openfpga_ctx.arch().tile_annotations, openfpga_ctx.arch().circuit_lib,
sram_model, openfpga_ctx.arch().config_protocol.type(),
name_module_using_index, frame_view, verbose);
name_module_using_index, vpr_device_ctx.arch->perimeter_cb, frame_view,
verbose);
}
/* Build FPGA fabric top-level module */
@ -141,7 +142,8 @@ int build_device_module_graph(
openfpga_ctx.arch().arch_direct, openfpga_ctx.arch().config_protocol,
sram_model, fabric_tile, name_module_using_index, frame_view,
compress_routing, duplicate_grid_pin, fabric_key,
generate_random_fabric_key, group_config_block, verbose);
generate_random_fabric_key, group_config_block,
vpr_device_ctx.arch->perimeter_cb, verbose);
if (CMD_EXEC_FATAL_ERROR == status) {
return status;

300
openfpga/src/fabric/build_fabric_tile.cpp
View File

@ -22,10 +22,175 @@
namespace openfpga {
/********************************************************************
* Build tiles by following the top-level style.
* With a given coordinate of a grid, find an existing fabric tile
* or create a new fabric tile
* - A grid may never exist in any fabric tile (no coordinate matches)
* Create a new one
* - A grid already in another fabric tile (occur in heterogeneous blocks)
* Find the existing one
*******************************************************************/
static int find_or_create_one_fabric_tile_from_grid(
FabricTile& fabric_tile, FabricTileId& curr_tile_id, const DeviceGrid& grids,
const t_physical_tile_loc& tile_loc, const bool& verbose) {
t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(tile_loc);
vtr::Point<size_t> curr_tile_coord(tile_loc.x, tile_loc.y);
vtr::Point<size_t> curr_gsb_coord(tile_loc.x, tile_loc.y);
bool skip_add_pb = false;
/* For EMPTY grid, routing blocks may still be required if there is a gsb
*/
if (true == is_empty_type(phy_tile_type)) {
return CMD_EXEC_SUCCESS;
} else if ((0 < grids.get_width_offset(tile_loc)) ||
(0 < grids.get_height_offset(tile_loc))) {
/* Skip width, height > 1 tiles (mostly heterogeneous blocks) */
/* Find the root of this grid, the instance id should be valid.
* We just copy it here
*/
vtr::Point<size_t> root_tile_coord(
curr_tile_coord.x() - grids.get_width_offset(tile_loc),
curr_tile_coord.y() - grids.get_height_offset(tile_loc));
skip_add_pb = true;
VTR_LOGV(verbose,
"Tile[%lu][%lu] contains a heterogeneous block which is "
"rooted from tile[%lu][%lu]\n",
curr_tile_coord.x(), curr_tile_coord.y(), root_tile_coord.x(),
root_tile_coord.y());
curr_tile_id = fabric_tile.find_tile(root_tile_coord);
/* Update the coordinates of the pb in tiles */
size_t root_pb_idx_in_curr_tile =
fabric_tile.find_pb_index_in_tile(curr_tile_id, root_tile_coord);
int status_code = fabric_tile.set_pb_max_coordinate(
curr_tile_id, root_pb_idx_in_curr_tile, curr_tile_coord);
if (status_code != CMD_EXEC_SUCCESS) {
return CMD_EXEC_FATAL_ERROR;
}
} else {
/* Need to create a new tile here */
VTR_LOGV(verbose, "Create a regular tile[%lu][%lu]\n", curr_tile_coord.x(),
curr_tile_coord.y());
curr_tile_id = fabric_tile.create_tile(curr_tile_coord);
}
/* Ensure that we have a valid id */
if (!fabric_tile.valid_tile_id(curr_tile_id)) {
VTR_LOG_ERROR("Failed to get a valid id for tile[%lu][%lu]!\n",
curr_tile_coord.x(), curr_tile_coord.y());
return CMD_EXEC_FATAL_ERROR;
}
/* Add components: pb, cbx, cby, and sb if exists */
if (!skip_add_pb) {
fabric_tile.add_pb_coordinate(curr_tile_id, curr_tile_coord,
curr_gsb_coord);
}
return CMD_EXEC_SUCCESS;
}
/********************************************************************
* Build tiles by following the bottom style.
* - The programmble block, e.g., clb, is placed on the bottom-left corner
* - The connection blocks and switch block are placed on the top and bottom
*sides
* This is exactly how GSB is organized. Just need to transfer data from one GSB
* The gsb coordinate is the same as the grid coordinate when the
* bottom-left style is considered
*
* ------------------------------
* +----------+ +----------+ ^
* | CBx | | SB | |
* | [x][y] | | [x][y] | GSB[x][y]
* +----------+ +----------+ |
* +----------+ +----------+ |
* | Grid | | CBy | |
* | [x][y] | | [x][y] | |
* +----------+ +----------+ v
* ------------------------------
*
*******************************************************************/
static int build_fabric_tile_style_bottom_left(FabricTile& fabric_tile,
const DeviceGrid& grids,
const size_t& layer,
const RRGraphView& rr_graph,
const DeviceRRGSB& device_rr_gsb,
const bool& verbose) {
int status_code = CMD_EXEC_SUCCESS;
/* Walk through all the device rr_gsb and create tile one by one */
for (size_t ix = 0; ix < grids.width(); ++ix) {
for (size_t iy = 0; iy < grids.height(); ++iy) {
t_physical_tile_loc tile_loc(ix, iy, layer);
FabricTileId curr_tile_id = FabricTileId::INVALID();
status_code = find_or_create_one_fabric_tile_from_grid(
fabric_tile, curr_tile_id, grids, tile_loc, verbose);
if (status_code != CMD_EXEC_SUCCESS) {
return CMD_EXEC_FATAL_ERROR;
}
/* If no tile is created for the pb, check if routing exists */
vtr::Point<size_t> curr_tile_coord(tile_loc.x, tile_loc.y);
vtr::Point<size_t> curr_gsb_coord(ix, iy);
if (!fabric_tile.valid_tile_id(curr_tile_id)) {
if (!device_rr_gsb.is_gsb_exist(rr_graph, curr_gsb_coord)) {
VTR_LOGV(verbose, "Skip tile[%lu][%lu] as it is empty\n",
curr_tile_coord.x(), curr_tile_coord.y());
continue;
}
/* Need to create a new tile here */
VTR_LOGV(verbose,
"Create tile[%lu][%lu] which only has routing but not a "
"programmable block\n",
curr_tile_coord.x(), curr_tile_coord.y());
curr_tile_id = fabric_tile.create_tile(curr_tile_coord);
}
if (fabric_tile.valid_tile_id(curr_tile_id) &&
!device_rr_gsb.is_gsb_exist(rr_graph, curr_gsb_coord)) {
VTR_LOGV(
verbose,
"Skip to add routing to tile[%lu][%lu] as it is not required\n",
curr_tile_coord.x(), curr_tile_coord.y());
continue;
}
const RRGSB& curr_rr_gsb = device_rr_gsb.get_gsb(curr_gsb_coord);
for (t_rr_type cb_type : {CHANX, CHANY}) {
if (curr_rr_gsb.is_cb_exist(cb_type)) {
fabric_tile.add_cb_coordinate(curr_tile_id, cb_type,
curr_rr_gsb.get_sb_coordinate());
VTR_LOGV(
verbose, "Added %s connection block [%lu][%lu] to tile[%lu][%lu]\n",
cb_type == CHANX ? "x-" : "y-", curr_rr_gsb.get_cb_x(cb_type),
curr_rr_gsb.get_cb_y(cb_type), ix, iy);
}
}
if (curr_rr_gsb.is_sb_exist(rr_graph)) {
fabric_tile.add_sb_coordinate(curr_tile_id,
curr_rr_gsb.get_sb_coordinate());
VTR_LOGV(verbose, "Added switch block [%lu][%lu] to tile[%lu][%lu]\n",
curr_rr_gsb.get_sb_x(), curr_rr_gsb.get_sb_y(), ix, iy);
}
}
}
return status_code;
}
/********************************************************************
* Build tiles by following the top-left style.
* - The programmble block, e.g., clb, is placed on the top-left corner
* - The connection blocks and switch block are placed on the right and bottom
*sides
* Tile[x][y]
* ------------------------------
* +----------+ +----------+ ^
* | Grid | | CBy | GSB[x][y]
* | [x][y] | | [x][y] | |
* +----------+ +----------+ v
* ------------------------------
* +----------+ +----------+ ^
* | CBx | | SB | |
* | [x][y-1] | | [x][y-1] | GSB[x][y-1]
* +----------+ +----------+ |
* ------------------------------
*******************************************************************/
static int build_fabric_tile_style_top_left(FabricTile& fabric_tile,
const DeviceGrid& grids,
@ -39,17 +204,34 @@ static int build_fabric_tile_style_top_left(FabricTile& fabric_tile,
for (size_t ix = 0; ix < grids.width(); ++ix) {
for (size_t iy = 0; iy < grids.height(); ++iy) {
t_physical_tile_loc tile_loc(ix, iy, layer);
t_physical_tile_type_ptr phy_tile_type =
grids.get_physical_type(tile_loc);
bool skip_add_pb = false;
vtr::Point<size_t> curr_tile_coord(ix, iy);
vtr::Point<size_t> curr_gsb_coord(ix, iy - 1);
FabricTileId curr_tile_id = FabricTileId::INVALID();
/* For EMPTY grid, routing blocks may still be required if there is a gsb
*/
if (true == is_empty_type(phy_tile_type)) {
skip_add_pb = true;
if (!device_rr_gsb.is_gsb_exist(rr_graph, curr_gsb_coord)) {
status_code = find_or_create_one_fabric_tile_from_grid(
fabric_tile, curr_tile_id, grids, tile_loc, verbose);
if (status_code != CMD_EXEC_SUCCESS) {
return CMD_EXEC_FATAL_ERROR;
}
/* If no valid tile is created/found by the pb, check if there is any
* routing inside */
vtr::Point<size_t> curr_tile_coord(tile_loc.x, tile_loc.y);
vtr::Point<size_t> curr_gsb_coord(ix, iy);
vtr::Point<size_t> neighbor_gsb_coord(ix, iy - 1);
if (!fabric_tile.valid_tile_id(curr_tile_id)) {
bool routing_exist = false;
if (device_rr_gsb.is_gsb_exist(rr_graph, curr_gsb_coord)) {
const RRGSB& routing_rr_gsb = device_rr_gsb.get_gsb(curr_gsb_coord);
if (routing_rr_gsb.is_cb_exist(CHANY)) {
routing_exist = true;
}
}
if (device_rr_gsb.is_gsb_exist(rr_graph, neighbor_gsb_coord)) {
const RRGSB& routing_rr_gsb =
device_rr_gsb.get_gsb(neighbor_gsb_coord);
if (routing_rr_gsb.is_cb_exist(CHANX) ||
routing_rr_gsb.is_sb_exist(rr_graph)) {
routing_exist = true;
}
}
if (!routing_exist) {
VTR_LOGV(verbose, "Skip tile[%lu][%lu] as it is empty\n",
curr_tile_coord.x(), curr_tile_coord.y());
continue;
@ -60,74 +242,38 @@ static int build_fabric_tile_style_top_left(FabricTile& fabric_tile,
"programmable block\n",
curr_tile_coord.x(), curr_tile_coord.y());
curr_tile_id = fabric_tile.create_tile(curr_tile_coord);
} else if ((0 < grids.get_width_offset(tile_loc)) ||
(0 < grids.get_height_offset(tile_loc))) {
/* Skip width, height > 1 tiles (mostly heterogeneous blocks) */
/* Find the root of this grid, the instance id should be valid.
* We just copy it here
*/
vtr::Point<size_t> root_tile_coord(
ix - grids.get_width_offset(tile_loc),
iy - grids.get_height_offset(tile_loc));
skip_add_pb = true;
VTR_LOGV(verbose,
"Tile[%lu][%lu] contains a heterogeneous block which is "
"rooted from tile[%lu][%lu]\n",
curr_tile_coord.x(), curr_tile_coord.y(), root_tile_coord.x(),
root_tile_coord.y());
curr_tile_id = fabric_tile.find_tile(root_tile_coord);
/* Update the coordinates of the pb in tiles */
size_t root_pb_idx_in_curr_tile =
fabric_tile.find_pb_index_in_tile(curr_tile_id, root_tile_coord);
status_code = fabric_tile.set_pb_max_coordinate(
curr_tile_id, root_pb_idx_in_curr_tile, vtr::Point<size_t>(ix, iy));
if (status_code != CMD_EXEC_SUCCESS) {
return CMD_EXEC_FATAL_ERROR;
}
} else {
/* Need to create a new tile here */
VTR_LOGV(verbose, "Create a regular tile[%lu][%lu]\n",
curr_tile_coord.x(), curr_tile_coord.y());
curr_tile_id = fabric_tile.create_tile(curr_tile_coord);
}
/* Ensure that we have a valid id */
if (!fabric_tile.valid_tile_id(curr_tile_id)) {
VTR_LOG_ERROR("Failed to get a valid id for tile[%lu][%lu]!\n", ix, iy);
return CMD_EXEC_FATAL_ERROR;
}
/* Add components: pb, cbx, cby, and sb if exists */
if (!skip_add_pb) {
fabric_tile.add_pb_coordinate(curr_tile_id, curr_tile_coord,
curr_gsb_coord);
}
/* The gsb coordinate is different than the grid coordinate when the
* top-left style is considered
*
* +----------+ +----------+
* | Grid | | CBx |
* | [x][y] | | [x][y] |
* +----------+ +----------+
* +----------+ +----------+
* | CBy | | SB |
* | [x][y-1] | | [x][y-1] |
* +----------+ +----------+
*
*/
if (!device_rr_gsb.is_gsb_exist(rr_graph, curr_gsb_coord)) {
continue;
}
const RRGSB& curr_rr_gsb = device_rr_gsb.get_gsb(curr_gsb_coord);
for (t_rr_type cb_type : {CHANX, CHANY}) {
if (curr_rr_gsb.is_cb_exist(cb_type)) {
fabric_tile.add_cb_coordinate(curr_tile_id, cb_type,
/* For the cby in the same gsb */
if (device_rr_gsb.is_gsb_exist(rr_graph, curr_gsb_coord)) {
const RRGSB& curr_rr_gsb = device_rr_gsb.get_gsb(curr_gsb_coord);
if (curr_rr_gsb.is_cb_exist(CHANY)) {
fabric_tile.add_cb_coordinate(curr_tile_id, CHANY,
curr_rr_gsb.get_sb_coordinate());
VTR_LOGV(
verbose, "Added y- connection block [%lu][%lu] to tile[%lu][%lu]\n",
curr_rr_gsb.get_cb_x(CHANY), curr_rr_gsb.get_cb_y(CHANY), ix, iy);
}
}
if (curr_rr_gsb.is_sb_exist(rr_graph)) {
fabric_tile.add_sb_coordinate(curr_tile_id,
curr_rr_gsb.get_sb_coordinate());
/* For the cbx and sb in the neighbour gsb */
if (device_rr_gsb.is_gsb_exist(rr_graph, neighbor_gsb_coord)) {
const RRGSB& neighbor_rr_gsb =
device_rr_gsb.get_gsb(neighbor_gsb_coord);
if (neighbor_rr_gsb.is_cb_exist(CHANX)) {
fabric_tile.add_cb_coordinate(curr_tile_id, CHANX,
neighbor_rr_gsb.get_sb_coordinate());
VTR_LOGV(verbose,
"Added x- connection block [%lu][%lu] to tile[%lu][%lu]\n",
neighbor_rr_gsb.get_cb_x(CHANX),
neighbor_rr_gsb.get_cb_y(CHANX), ix, iy);
}
if (neighbor_rr_gsb.is_sb_exist(rr_graph)) {
fabric_tile.add_sb_coordinate(curr_tile_id,
neighbor_rr_gsb.get_sb_coordinate());
VTR_LOGV(verbose, "Added switch block [%lu][%lu] to tile[%lu][%lu]\n",
neighbor_rr_gsb.get_sb_x(), neighbor_rr_gsb.get_sb_y(), ix,
iy);
}
}
}
}
@ -152,6 +298,10 @@ int build_fabric_tile(FabricTile& fabric_tile, const TileConfig& tile_config,
if (tile_config.style() == TileConfig::e_style::TOP_LEFT) {
status_code = build_fabric_tile_style_top_left(
fabric_tile, grids, 0, rr_graph, device_rr_gsb, verbose);
} else if (tile_config.style() == TileConfig::e_style::BOTTOM_LEFT) {
status_code = build_fabric_tile_style_bottom_left(
fabric_tile, grids, 0, rr_graph, device_rr_gsb, verbose);
} else {
/* Error out for styles that are not supported yet! */
VTR_LOG_ERROR("Tile style '%s' is not supported yet!\n",

23
openfpga/src/fabric/build_grid_module_duplicated_pins.cpp
View File

@ -55,7 +55,8 @@ void add_grid_module_duplicated_pb_type_ports(
ModuleManager& module_manager, const ModuleId& grid_module,
const VprDeviceAnnotation& vpr_device_annotation,
t_physical_tile_type_ptr grid_type_descriptor,
const TileAnnotation& tile_annotation, const e_side& border_side) {
const TileAnnotation& tile_annotation, const e_side& border_side,
const bool& perimeter_cb) {
/* Ensure that we have a valid grid_type_descriptor */
VTR_ASSERT(false == is_empty_type(grid_type_descriptor));
@ -65,8 +66,8 @@ void add_grid_module_duplicated_pb_type_ports(
* Otherwise, we will iterate all the 4 sides
*/
if (true == is_io_type(grid_type_descriptor)) {
grid_pin_sides =
find_grid_module_pin_sides(grid_type_descriptor, border_side);
grid_pin_sides = find_grid_module_pin_sides(grid_type_descriptor,
border_side, perimeter_cb);
} else {
grid_pin_sides = {TOP, RIGHT, BOTTOM, LEFT};
}
@ -172,7 +173,8 @@ static void add_grid_module_net_connect_duplicated_pb_graph_pin(
const size_t& child_inst_subtile_index,
const VprDeviceAnnotation& vpr_device_annotation,
t_physical_tile_type_ptr grid_type_descriptor, t_pb_graph_pin* pb_graph_pin,
const e_side& border_side, const e_pin2pin_interc_type& pin2pin_interc_type) {
const e_side& border_side, const bool& perimeter_cb,
const e_pin2pin_interc_type& pin2pin_interc_type) {
/* Make sure this is ONLY applied to output pins */
VTR_ASSERT(OUTPUT2OUTPUT_INTERC == pin2pin_interc_type);
@ -182,8 +184,8 @@ static void add_grid_module_net_connect_duplicated_pb_graph_pin(
* Otherwise, we will iterate all the 4 sides
*/
if (true == is_io_type(grid_type_descriptor)) {
grid_pin_sides =
find_grid_module_pin_sides(grid_type_descriptor, border_side);
grid_pin_sides = find_grid_module_pin_sides(grid_type_descriptor,
border_side, perimeter_cb);
} else {
grid_pin_sides = {TOP, RIGHT, BOTTOM, LEFT};
}
@ -316,7 +318,8 @@ void add_grid_module_nets_connect_duplicated_pb_type_ports(
const ModuleId& child_module, const size_t& child_instance,
const t_sub_tile& sub_tile, const VprDeviceAnnotation& vpr_device_annotation,
t_physical_tile_type_ptr grid_type_descriptor,
const TileAnnotation& tile_annotation, const e_side& border_side) {
const TileAnnotation& tile_annotation, const e_side& border_side,
const bool& perimeter_cb) {
/* Ensure that we have a valid grid_type_descriptor */
VTR_ASSERT(false == is_empty_type(grid_type_descriptor));
@ -334,7 +337,7 @@ void add_grid_module_nets_connect_duplicated_pb_type_ports(
module_manager, grid_module, child_module, child_instance,
child_inst_subtile_index, vpr_device_annotation, grid_type_descriptor,
tile_annotation, &(top_pb_graph_node->input_pins[iport][ipin]),
border_side, INPUT2INPUT_INTERC);
border_side, perimeter_cb, INPUT2INPUT_INTERC);
}
}
@ -345,7 +348,7 @@ void add_grid_module_nets_connect_duplicated_pb_type_ports(
module_manager, grid_module, child_module, child_instance,
child_inst_subtile_index, vpr_device_annotation, grid_type_descriptor,
&(top_pb_graph_node->output_pins[iport][ipin]), border_side,
OUTPUT2OUTPUT_INTERC);
perimeter_cb, OUTPUT2OUTPUT_INTERC);
}
}
@ -356,7 +359,7 @@ void add_grid_module_nets_connect_duplicated_pb_type_ports(
module_manager, grid_module, child_module, child_instance,
child_inst_subtile_index, vpr_device_annotation, grid_type_descriptor,
tile_annotation, &(top_pb_graph_node->clock_pins[iport][ipin]),
border_side, INPUT2INPUT_INTERC);
border_side, perimeter_cb, INPUT2INPUT_INTERC);
}
}
}

6
openfpga/src/fabric/build_grid_module_duplicated_pins.h
View File

@ -21,14 +21,16 @@ void add_grid_module_duplicated_pb_type_ports(
ModuleManager& module_manager, const ModuleId& grid_module,
const VprDeviceAnnotation& vpr_device_annotation,
t_physical_tile_type_ptr grid_type_descriptor,
const TileAnnotation& tile_annotation, const e_side& border_side);
const TileAnnotation& tile_annotation, const e_side& border_side,
const bool& perimeter_cb);
void add_grid_module_nets_connect_duplicated_pb_type_ports(
ModuleManager& module_manager, const ModuleId& grid_module,
const ModuleId& child_module, const size_t& child_instance,
const t_sub_tile& sub_tile, const VprDeviceAnnotation& vpr_device_annotation,
t_physical_tile_type_ptr grid_type_descriptor,
const TileAnnotation& tile_annotation, const e_side& border_side);
const TileAnnotation& tile_annotation, const e_side& border_side,
const bool& perimeter_cb);
} /* end namespace openfpga */

24
openfpga/src/fabric/build_grid_module_utils.cpp
View File

@ -24,7 +24,8 @@ namespace openfpga {
* 5. I/O grids in the center part of FPGA can have ports on any side
*******************************************************************/
std::vector<e_side> find_grid_module_pin_sides(
t_physical_tile_type_ptr grid_type_descriptor, const e_side& border_side) {
t_physical_tile_type_ptr grid_type_descriptor, const e_side& border_side,
const bool& perimeter_cb) {
/* We must have an regular (non-I/O) type here */
VTR_ASSERT(true == is_io_type(grid_type_descriptor));
SideManager side_manager(border_side);
@ -33,7 +34,19 @@ std::vector<e_side> find_grid_module_pin_sides(
return {TOP, RIGHT, BOTTOM, LEFT};
}
return std::vector<e_side>(1, side_manager.get_opposite());
if (!perimeter_cb) {
return std::vector<e_side>(1, side_manager.get_opposite());
}
/* For cbs on perimeter, exclude the border side. All the other 3 sides are ok
*/
std::vector<e_side> pin_sides;
pin_sides.reserve(3);
for (e_side pin_side : {TOP, RIGHT, BOTTOM, LEFT}) {
if (pin_side != border_side) {
pin_sides.push_back(pin_side);
}
}
return pin_sides;
}
/********************************************************************
@ -47,15 +60,16 @@ void add_grid_module_net_connect_pb_graph_pin(
const VprDeviceAnnotation& vpr_device_annotation,
t_physical_tile_type_ptr grid_type_descriptor,
const TileAnnotation& tile_annotation, t_pb_graph_pin* pb_graph_pin,
const e_side& border_side, const e_pin2pin_interc_type& pin2pin_interc_type) {
const e_side& border_side, const bool& perimeter_cb,
const e_pin2pin_interc_type& pin2pin_interc_type) {
/* Find the pin side for I/O grids*/
std::vector<e_side> grid_pin_sides;
/* For I/O grids, we care only one side
* Otherwise, we will iterate all the 4 sides
*/
if (true == is_io_type(grid_type_descriptor)) {
grid_pin_sides =
find_grid_module_pin_sides(grid_type_descriptor, border_side);
grid_pin_sides = find_grid_module_pin_sides(grid_type_descriptor,
border_side, perimeter_cb);
} else {
grid_pin_sides = {TOP, RIGHT, BOTTOM, LEFT};
}

5
openfpga/src/fabric/build_grid_module_utils.h
View File

@ -19,7 +19,8 @@
namespace openfpga {
std::vector<e_side> find_grid_module_pin_sides(
t_physical_tile_type_ptr grid_type_descriptor, const e_side& border_side);
t_physical_tile_type_ptr grid_type_descriptor, const e_side& border_side,
const bool& perimeter_cb);
void add_grid_module_net_connect_pb_graph_pin(
ModuleManager& module_manager, const ModuleId& grid_module,
@ -28,7 +29,7 @@ void add_grid_module_net_connect_pb_graph_pin(
const VprDeviceAnnotation& vpr_device_annotation,
t_physical_tile_type_ptr grid_type_descriptor,
const TileAnnotation& tile_annotation, t_pb_graph_pin* pb_graph_pin,
const e_side& border_side,
const e_side& border_side, const bool& perimeter_cb,
const enum e_pin2pin_interc_type& pin2pin_interc_type);
} /* end namespace openfpga */

32
openfpga/src/fabric/build_grid_modules.cpp
View File

@ -42,7 +42,8 @@ static void add_grid_module_pb_type_ports(
ModuleManager& module_manager, const ModuleId& grid_module,
const VprDeviceAnnotation& vpr_device_annotation,
t_physical_tile_type_ptr grid_type_descriptor,
const TileAnnotation& tile_annotation, const e_side& border_side) {
const TileAnnotation& tile_annotation, const e_side& border_side,
const bool& perimeter_cb) {
/* Ensure that we have a valid grid_type_descriptor */
VTR_ASSERT(nullptr != grid_type_descriptor);
@ -52,8 +53,8 @@ static void add_grid_module_pb_type_ports(
* Otherwise, we will iterate all the 4 sides
*/
if (true == is_io_type(grid_type_descriptor)) {
grid_pin_sides =
find_grid_module_pin_sides(grid_type_descriptor, border_side);
grid_pin_sides = find_grid_module_pin_sides(grid_type_descriptor,
border_side, perimeter_cb);
} else {
grid_pin_sides = {TOP, RIGHT, BOTTOM, LEFT};
}
@ -125,7 +126,8 @@ static void add_grid_module_nets_connect_pb_type_ports(
const ModuleId& child_module, const size_t& child_instance,
const t_sub_tile& sub_tile, const VprDeviceAnnotation& vpr_device_annotation,
t_physical_tile_type_ptr grid_type_descriptor,
const TileAnnotation& tile_annotation, const e_side& border_side) {
const TileAnnotation& tile_annotation, const e_side& border_side,
const bool& perimeter_cb) {
/* Ensure that we have a valid grid_type_descriptor */
VTR_ASSERT(nullptr != grid_type_descriptor);
@ -144,7 +146,7 @@ static void add_grid_module_nets_connect_pb_type_ports(
module_manager, grid_module, child_module, child_instance,
child_inst_subtile_index, vpr_device_annotation, grid_type_descriptor,
tile_annotation, &(top_pb_graph_node->input_pins[iport][ipin]),
border_side, INPUT2INPUT_INTERC);
border_side, perimeter_cb, INPUT2INPUT_INTERC);
}
}
@ -155,7 +157,7 @@ static void add_grid_module_nets_connect_pb_type_ports(
module_manager, grid_module, child_module, child_instance,
child_inst_subtile_index, vpr_device_annotation, grid_type_descriptor,
tile_annotation, &(top_pb_graph_node->output_pins[iport][ipin]),
border_side, OUTPUT2OUTPUT_INTERC);
border_side, perimeter_cb, OUTPUT2OUTPUT_INTERC);
}
}
@ -166,7 +168,7 @@ static void add_grid_module_nets_connect_pb_type_ports(
module_manager, grid_module, child_module, child_instance,
child_inst_subtile_index, vpr_device_annotation, grid_type_descriptor,
tile_annotation, &(top_pb_graph_node->clock_pins[iport][ipin]),
border_side, INPUT2INPUT_INTERC);
border_side, perimeter_cb, INPUT2INPUT_INTERC);
}
}
}
@ -1168,7 +1170,7 @@ static int build_physical_tile_module(
const TileAnnotation& tile_annotation, const e_side& border_side,
const QLMemoryBankConfigSetting* ql_memory_bank_config_setting,
const bool& duplicate_grid_pin, const bool& group_config_block,
const bool& verbose) {
const bool& perimeter_cb, const bool& verbose) {
int status = CMD_EXEC_SUCCESS;
/* Create a Module for the top-level physical block, and add to module manager
*/
@ -1247,7 +1249,7 @@ static int build_physical_tile_module(
/* Default way to add these ports by following the definition in pb_types */
add_grid_module_pb_type_ports(module_manager, grid_module,
vpr_device_annotation, phy_block_type,
tile_annotation, border_side);
tile_annotation, border_side, perimeter_cb);
/* Add module nets to connect the pb_type ports to sub modules */
for (const t_sub_tile& sub_tile : phy_block_type->sub_tiles) {
VTR_ASSERT(sub_tile.equivalent_sites.size() == 1);
@ -1264,7 +1266,8 @@ static int build_physical_tile_module(
module_manager.child_module_instances(grid_module, pb_module)) {
add_grid_module_nets_connect_pb_type_ports(
module_manager, grid_module, pb_module, child_instance, sub_tile,
vpr_device_annotation, phy_block_type, tile_annotation, border_side);
vpr_device_annotation, phy_block_type, tile_annotation, border_side,
perimeter_cb);
}
}
} else {
@ -1272,7 +1275,7 @@ static int build_physical_tile_module(
/* Add these ports with duplication */
add_grid_module_duplicated_pb_type_ports(
module_manager, grid_module, vpr_device_annotation, phy_block_type,
tile_annotation, border_side);
tile_annotation, border_side, perimeter_cb);
/* Add module nets to connect the duplicated pb_type ports to sub modules */
for (const t_sub_tile& sub_tile : phy_block_type->sub_tiles) {
@ -1290,7 +1293,8 @@ static int build_physical_tile_module(
module_manager.child_module_instances(grid_module, pb_module)) {
add_grid_module_nets_connect_duplicated_pb_type_ports(
module_manager, grid_module, pb_module, child_instance, sub_tile,
vpr_device_annotation, phy_block_type, tile_annotation, border_side);
vpr_device_annotation, phy_block_type, tile_annotation, border_side,
perimeter_cb);
}
}
}
@ -1436,7 +1440,7 @@ int build_grid_modules(
module_manager, decoder_lib, device_annotation, circuit_lib,
sram_orgz_type, sram_model, &physical_tile, tile_annotation,
io_type_side, ql_memory_bank_config_setting, duplicate_grid_pin,
group_config_block, verbose);
group_config_block, device_ctx.arch->perimeter_cb, verbose);
if (status != CMD_EXEC_SUCCESS) {
return CMD_EXEC_FATAL_ERROR;
}
@ -1447,7 +1451,7 @@ int build_grid_modules(
module_manager, decoder_lib, device_annotation, circuit_lib,
sram_orgz_type, sram_model, &physical_tile, tile_annotation, NUM_SIDES,
ql_memory_bank_config_setting, duplicate_grid_pin, group_config_block,
verbose);
device_ctx.arch->perimeter_cb, verbose);
if (status != CMD_EXEC_SUCCESS) {
return CMD_EXEC_FATAL_ERROR;
}

43
openfpga/src/fabric/build_tile_modules.cpp
View File

@ -732,13 +732,13 @@ static int build_tile_module_port_and_nets_between_sb_and_cb(
* is_cb_exist() FOr RIGHT and BOTTOM side, find the adjacent RRGSB and then
* use is_cb_exist()
*/
if (TOP == side_manager.get_side() || LEFT == side_manager.get_side()) {
if (BOTTOM == side_manager.get_side() || LEFT == side_manager.get_side()) {
if (false == rr_gsb.is_cb_exist(cb_type)) {
continue;
}
}
if (RIGHT == side_manager.get_side() || BOTTOM == side_manager.get_side()) {
if (RIGHT == side_manager.get_side() || TOP == side_manager.get_side()) {
const RRGSB& adjacent_gsb =
device_rr_gsb.get_gsb(module_gsb_cb_coordinate);
if (false == adjacent_gsb.is_cb_exist(cb_type)) {
@ -1175,7 +1175,7 @@ static int build_tile_port_and_nets_from_pb(
const TileAnnotation& tile_annotation, const vtr::Point<size_t>& pb_coord,
const std::vector<size_t>& pb_instances, const FabricTile& fabric_tile,
const FabricTileId& curr_fabric_tile_id, const size_t& ipb,
const bool& frame_view, const bool& verbose) {
const bool& perimeter_cb, const bool& frame_view, const bool& verbose) {
size_t pb_instance = pb_instances[ipb];
t_physical_tile_type_ptr phy_tile = grids.get_physical_type(
t_physical_tile_loc(pb_coord.x(), pb_coord.y(), layer));
@ -1201,7 +1201,8 @@ static int build_tile_port_and_nets_from_pb(
* Otherwise, we will iterate all the 4 sides
*/
if (true == is_io_type(phy_tile)) {
grid_pin_sides = find_grid_module_pin_sides(phy_tile, grid_side);
grid_pin_sides =
find_grid_module_pin_sides(phy_tile, grid_side, perimeter_cb);
} else {
grid_pin_sides = {TOP, RIGHT, BOTTOM, LEFT};
}
@ -1378,7 +1379,7 @@ static int build_tile_module_ports_and_nets(
const FabricTileId& fabric_tile_id, const std::vector<size_t>& pb_instances,
const std::map<t_rr_type, std::vector<size_t>>& cb_instances,
const std::vector<size_t>& sb_instances, const bool& name_module_using_index,
const bool& frame_view, const bool& verbose) {
const bool& perimeter_cb, const bool& frame_view, const bool& verbose) {
int status_code = CMD_EXEC_SUCCESS;
/* Get the submodule of Switch blocks one by one, build connections between sb
@ -1441,7 +1442,7 @@ static int build_tile_module_ports_and_nets(
status_code = build_tile_port_and_nets_from_pb(
module_manager, tile_module, grids, layer, vpr_device_annotation,
rr_graph_view, tile_annotation, pb_coord, pb_instances, fabric_tile,
fabric_tile_id, ipb, frame_view, verbose);
fabric_tile_id, ipb, perimeter_cb, frame_view, verbose);
if (status_code != CMD_EXEC_SUCCESS) {
return CMD_EXEC_FATAL_ERROR;
}
@ -1487,8 +1488,8 @@ static int build_tile_module(
const TileAnnotation& tile_annotation, const CircuitLibrary& circuit_lib,
const CircuitModelId& sram_model,
const e_config_protocol_type& sram_orgz_type,
const bool& name_module_using_index, const bool& frame_view,
const bool& verbose) {
const bool& name_module_using_index, const bool& perimeter_cb,
const bool& frame_view, const bool& verbose) {
int status_code = CMD_EXEC_SUCCESS;
/* Create the module */
@ -1635,7 +1636,7 @@ static int build_tile_module(
module_manager, tile_module, grids, layer, vpr_device_annotation,
device_rr_gsb, rr_graph_view, tile_annotation, fabric_tile, fabric_tile_id,
pb_instances, cb_instances, sb_instances, name_module_using_index,
frame_view, verbose);
perimeter_cb, frame_view, verbose);
/* Add global ports to the pb_module:
* This is a much easier job after adding sub modules (instances),
@ -1698,18 +1699,16 @@ static int build_tile_module(
/********************************************************************
* Build all the tile modules
*******************************************************************/
int build_tile_modules(ModuleManager& module_manager,
DecoderLibrary& decoder_lib,
const FabricTile& fabric_tile, const DeviceGrid& grids,
const VprDeviceAnnotation& vpr_device_annotation,
const DeviceRRGSB& device_rr_gsb,
const RRGraphView& rr_graph_view,
const TileAnnotation& tile_annotation,
const CircuitLibrary& circuit_lib,
const CircuitModelId& sram_model,
const e_config_protocol_type& sram_orgz_type,
const bool& name_module_using_index,
const bool& frame_view, const bool& verbose) {
int build_tile_modules(
ModuleManager& module_manager, DecoderLibrary& decoder_lib,
const FabricTile& fabric_tile, const DeviceGrid& grids,
const VprDeviceAnnotation& vpr_device_annotation,
const DeviceRRGSB& device_rr_gsb, const RRGraphView& rr_graph_view,
const TileAnnotation& tile_annotation, const CircuitLibrary& circuit_lib,
const CircuitModelId& sram_model,
const e_config_protocol_type& sram_orgz_type,
const bool& name_module_using_index, const bool& perimeter_cb,
const bool& frame_view, const bool& verbose) {
vtr::ScopedStartFinishTimer timer("Build tile modules for the FPGA fabric");
int status_code = CMD_EXEC_SUCCESS;
@ -1722,7 +1721,7 @@ int build_tile_modules(ModuleManager& module_manager,
module_manager, decoder_lib, fabric_tile, fabric_tile_id, grids, layer,
vpr_device_annotation, device_rr_gsb, rr_graph_view, tile_annotation,
circuit_lib, sram_model, sram_orgz_type, name_module_using_index,
frame_view, verbose);
perimeter_cb, frame_view, verbose);
if (status_code != CMD_EXEC_SUCCESS) {
return CMD_EXEC_FATAL_ERROR;
}

22
openfpga/src/fabric/build_tile_modules.h
View File

@ -25,18 +25,16 @@
/* begin namespace openfpga */
namespace openfpga {
int build_tile_modules(ModuleManager& module_manager,
DecoderLibrary& decoder_lib,
const FabricTile& fabric_tile, const DeviceGrid& grids,
const VprDeviceAnnotation& vpr_device_annotation,
const DeviceRRGSB& device_rr_gsb,
const RRGraphView& rr_graph_view,
const TileAnnotation& tile_annotation,
const CircuitLibrary& circuit_lib,
const CircuitModelId& sram_model,
const e_config_protocol_type& sram_orgz_type,
const bool& name_module_using_index,
const bool& frame_view, const bool& verbose);
int build_tile_modules(
ModuleManager& module_manager, DecoderLibrary& decoder_lib,
const FabricTile& fabric_tile, const DeviceGrid& grids,
const VprDeviceAnnotation& vpr_device_annotation,
const DeviceRRGSB& device_rr_gsb, const RRGraphView& rr_graph_view,
const TileAnnotation& tile_annotation, const CircuitLibrary& circuit_lib,
const CircuitModelId& sram_model,
const e_config_protocol_type& sram_orgz_type,
const bool& name_module_using_index, const bool& perimeter_cb,
const bool& frame_view, const bool& verbose);
} /* end namespace openfpga */

7
openfpga/src/fabric/build_top_module.cpp
View File

@ -58,7 +58,8 @@ int build_top_module(
const bool& name_module_using_index, const bool& frame_view,
const bool& compact_routing_hierarchy, const bool& duplicate_grid_pin,
const FabricKey& fabric_key, const bool& generate_random_fabric_key,
const bool& group_config_block, const bool& verbose) {
const bool& group_config_block, const bool& perimeter_cb,
const bool& verbose) {
vtr::ScopedStartFinishTimer timer("Build FPGA fabric module");
int status = CMD_EXEC_SUCCESS;
@ -79,7 +80,7 @@ int build_top_module(
rr_clock_lookup, vpr_device_annotation, grids, layer, tile_annotation,
rr_graph, device_rr_gsb, tile_direct, arch_direct, config_protocol,
sram_model, frame_view, compact_routing_hierarchy, duplicate_grid_pin,
fabric_key, group_config_block);
fabric_key, group_config_block, perimeter_cb, verbose);
} else {
/* Build the tile instances under the top module */
status = build_top_module_tile_child_instances(
@ -87,7 +88,7 @@ int build_top_module(
rr_clock_lookup, vpr_device_annotation, grids, layer, tile_annotation,
rr_graph, device_rr_gsb, tile_direct, arch_direct, fabric_tile,
config_protocol, sram_model, fabric_key, group_config_block,
name_module_using_index, frame_view, verbose);
name_module_using_index, perimeter_cb, frame_view, verbose);
}
if (status != CMD_EXEC_SUCCESS) {

3
openfpga/src/fabric/build_top_module.h
View File

@ -45,7 +45,8 @@ int build_top_module(
const bool& name_module_using_index, const bool& frame_view,
const bool& compact_routing_hierarchy, const bool& duplicate_grid_pin,
const FabricKey& fabric_key, const bool& generate_random_fabric_key,
const bool& group_config_block, const bool& verbose);
const bool& group_config_block, const bool& perimeter_cb,
const bool& verbose);
} /* end namespace openfpga */

24
openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp
View File

@ -244,7 +244,7 @@ static vtr::Matrix<size_t> add_top_module_switch_block_instances(
static vtr::Matrix<size_t> add_top_module_connection_block_instances(
ModuleManager& module_manager, const ModuleId& top_module,
const DeviceRRGSB& device_rr_gsb, const t_rr_type& cb_type,
const bool& compact_routing_hierarchy) {
const bool& compact_routing_hierarchy, const bool& verbose) {
vtr::ScopedStartFinishTimer timer(
"Add connection block instances to top module");
@ -261,9 +261,15 @@ static vtr::Matrix<size_t> add_top_module_connection_block_instances(
* We will skip those modules
*/
const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy);
VTR_LOGV(verbose, "Try to add %s connnection block at (%lu, %lu)\n",
cb_type == CHANX ? "X-" : "Y-", ix, iy);
vtr::Point<size_t> cb_coordinate(rr_gsb.get_cb_x(cb_type),
rr_gsb.get_cb_y(cb_type));
if (false == rr_gsb.is_cb_exist(cb_type)) {
VTR_LOGV(
verbose,
"Skip %s connnection block at (%lu, %lu) as it does not exist\n",
cb_type == CHANX ? "X-" : "Y-", cb_coordinate.x(), cb_coordinate.y());
continue;
}
/* If we use compact routing hierarchy, we should instanciate the unique
@ -295,6 +301,9 @@ static vtr::Matrix<size_t> add_top_module_connection_block_instances(
top_module, cb_module,
cb_instance_ids[rr_gsb.get_cb_x(cb_type)][rr_gsb.get_cb_y(cb_type)],
cb_instance_name);
VTR_LOGV(verbose, "Added %s connnection block '%s' (module '%s')\n",
cb_type == CHANX ? "X-" : "Y-", cb_instance_name.c_str(),
cb_module_name.c_str());
}
}
@ -445,7 +454,8 @@ int build_top_module_fine_grained_child_instances(
const ConfigProtocol& config_protocol, const CircuitModelId& sram_model,
const bool& frame_view, const bool& compact_routing_hierarchy,
const bool& duplicate_grid_pin, const FabricKey& fabric_key,
const bool& group_config_block) {
const bool& group_config_block, const bool& perimeter_cb,
const bool& verbose) {
int status = CMD_EXEC_SUCCESS;
std::map<t_rr_type, vtr::Matrix<size_t>> cb_instance_ids;
@ -459,11 +469,11 @@ int build_top_module_fine_grained_child_instances(
compact_routing_hierarchy);
/* Add all the CBX and CBYs across the fabric */
cb_instance_ids[CHANX] = add_top_module_connection_block_instances(
module_manager, top_module, device_rr_gsb, CHANX,
compact_routing_hierarchy);
module_manager, top_module, device_rr_gsb, CHANX, compact_routing_hierarchy,
verbose);
cb_instance_ids[CHANY] = add_top_module_connection_block_instances(
module_manager, top_module, device_rr_gsb, CHANY,
compact_routing_hierarchy);
module_manager, top_module, device_rr_gsb, CHANY, compact_routing_hierarchy,
verbose);
/* Update I/O children list */
add_top_module_io_children(module_manager, top_module, grids, layer,
@ -492,7 +502,7 @@ int build_top_module_fine_grained_child_instances(
status = add_top_module_global_ports_from_grid_modules(
module_manager, top_module, tile_annotation, vpr_device_annotation, grids,
layer, rr_graph, device_rr_gsb, cb_instance_ids, grid_instance_ids,
clk_ntwk, rr_clock_lookup);
clk_ntwk, rr_clock_lookup, perimeter_cb);
if (CMD_EXEC_FATAL_ERROR == status) {
return status;
}

3
openfpga/src/fabric/build_top_module_child_fine_grained_instance.h
View File

@ -44,7 +44,8 @@ int build_top_module_fine_grained_child_instances(
const ConfigProtocol& config_protocol, const CircuitModelId& sram_model,
const bool& frame_view, const bool& compact_routing_hierarchy,
const bool& duplicate_grid_pin, const FabricKey& fabric_key,
const bool& group_config_block);
const bool& group_config_block, const bool& perimeter_cb,
const bool& verbose);
} /* end namespace openfpga */

25
openfpga/src/fabric/build_top_module_child_tile_instance.cpp
View File

@ -802,13 +802,13 @@ static int build_top_module_tile_nets_between_sb_and_cb(
* is_cb_exist() FOr RIGHT and BOTTOM side, find the adjacent RRGSB and then
* use is_cb_exist()
*/
if (TOP == side_manager.get_side() || LEFT == side_manager.get_side()) {
if (BOTTOM == side_manager.get_side() || LEFT == side_manager.get_side()) {
if (false == rr_gsb.is_cb_exist(cb_type)) {
continue;
}
}
if (RIGHT == side_manager.get_side() || BOTTOM == side_manager.get_side()) {
if (RIGHT == side_manager.get_side() || TOP == side_manager.get_side()) {
const RRGSB& adjacent_gsb =
device_rr_gsb.get_gsb(module_gsb_cb_coordinate);
if (false == adjacent_gsb.is_cb_exist(cb_type)) {
@ -1295,7 +1295,7 @@ static int build_top_module_global_net_for_given_tile_module(
const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids,
const size_t& layer, const vtr::Point<size_t>& grid_coordinate,
const e_side& border_side, const vtr::Matrix<size_t>& tile_instance_ids,
const FabricTile& fabric_tile) {
const FabricTile& fabric_tile, const bool& perimeter_cb) {
/* Get the tile module and instance */
FabricTileId curr_fabric_tile_id =
fabric_tile.find_tile_by_pb_coordinate(grid_coordinate);
@ -1392,7 +1392,7 @@ static int build_top_module_global_net_for_given_tile_module(
size_t grid_pin_height =
physical_tile->pin_height_offset[grid_pin_index];
std::vector<e_side> pin_sides = find_physical_tile_pin_side(
physical_tile, grid_pin_index, border_side);
physical_tile, grid_pin_index, border_side, perimeter_cb);
BasicPort grid_pin_info =
vpr_device_annotation.physical_tile_pin_port_info(physical_tile,
@ -1452,7 +1452,7 @@ static int build_top_module_global_net_from_tile_modules(
const TileGlobalPortId& tile_global_port,
const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids,
const size_t& layer, const vtr::Matrix<size_t>& tile_instance_ids,
const FabricTile& fabric_tile) {
const FabricTile& fabric_tile, const bool& perimeter_cb) {
int status = CMD_EXEC_SUCCESS;
std::map<e_side, std::vector<vtr::Point<size_t>>> io_coordinates =
@ -1530,8 +1530,8 @@ static int build_top_module_global_net_from_tile_modules(
status = build_top_module_global_net_for_given_tile_module(
module_manager, top_module, top_module_port, tile_annotation,
tile_global_port, tile_port, vpr_device_annotation, grids, layer,
vtr::Point<size_t>(ix, iy), NUM_SIDES, tile_instance_ids,
fabric_tile);
vtr::Point<size_t>(ix, iy), NUM_SIDES, tile_instance_ids, fabric_tile,
perimeter_cb);
if (CMD_EXEC_FATAL_ERROR == status) {
return status;
}
@ -1578,7 +1578,7 @@ static int build_top_module_global_net_from_tile_modules(
status = build_top_module_global_net_for_given_tile_module(
module_manager, top_module, top_module_port, tile_annotation,
tile_global_port, tile_port, vpr_device_annotation, grids, layer,
io_coordinate, io_side, tile_instance_ids, fabric_tile);
io_coordinate, io_side, tile_instance_ids, fabric_tile, perimeter_cb);
if (CMD_EXEC_FATAL_ERROR == status) {
return status;
}
@ -1600,7 +1600,8 @@ static int add_top_module_global_ports_from_tile_modules(
const size_t& layer, const RRGraphView& rr_graph,
const DeviceRRGSB& device_rr_gsb,
const vtr::Matrix<size_t>& tile_instance_ids, const FabricTile& fabric_tile,
const ClockNetwork& clk_ntwk, const RRClockSpatialLookup& rr_clock_lookup) {
const ClockNetwork& clk_ntwk, const RRClockSpatialLookup& rr_clock_lookup,
const bool& perimeter_cb) {
int status = CMD_EXEC_SUCCESS;
/* Add the global ports which are NOT yet added to the top-level module
@ -1657,7 +1658,7 @@ static int add_top_module_global_ports_from_tile_modules(
status = build_top_module_global_net_from_tile_modules(
module_manager, top_module, top_module_port, tile_annotation,
tile_global_port, vpr_device_annotation, grids, layer,
tile_instance_ids, fabric_tile);
tile_instance_ids, fabric_tile, perimeter_cb);
}
if (status == CMD_EXEC_FATAL_ERROR) {
return status;
@ -1905,7 +1906,7 @@ int build_top_module_tile_child_instances(
const FabricTile& fabric_tile, const ConfigProtocol& config_protocol,
const CircuitModelId& sram_model, const FabricKey& fabric_key,
const bool& group_config_block, const bool& name_module_using_index,
const bool& frame_view, const bool& verbose) {
const bool& perimeter_cb, const bool& frame_view, const bool& verbose) {
int status = CMD_EXEC_SUCCESS;
vtr::Matrix<size_t> tile_instance_ids;
status = add_top_module_tile_instances(module_manager, top_module,
@ -1942,7 +1943,7 @@ int build_top_module_tile_child_instances(
status = add_top_module_global_ports_from_tile_modules(
module_manager, top_module, tile_annotation, vpr_device_annotation, grids,
layer, rr_graph, device_rr_gsb, tile_instance_ids, fabric_tile, clk_ntwk,
rr_clock_lookup);
rr_clock_lookup, perimeter_cb);
if (CMD_EXEC_FATAL_ERROR == status) {
return status;
}

2
openfpga/src/fabric/build_top_module_child_tile_instance.h
View File

@ -44,7 +44,7 @@ int build_top_module_tile_child_instances(
const FabricTile& fabric_tile, const ConfigProtocol& config_protocol,
const CircuitModelId& sram_model, const FabricKey& fabric_key,
const bool& group_config_block, const bool& name_module_using_index,
const bool& frame_view, const bool& verbose);
const bool& perimeter_cb, const bool& frame_view, const bool& verbose);
} /* end namespace openfpga */

49
openfpga/src/fabric/build_top_module_connection.cpp
View File

@ -753,13 +753,24 @@ static void add_top_module_nets_connect_sb_and_cb(
* is_cb_exist() FOr RIGHT and BOTTOM side, find the adjacent RRGSB and then
* use is_cb_exist()
*/
if (TOP == side_manager.get_side() || LEFT == side_manager.get_side()) {
if (BOTTOM == side_manager.get_side() || LEFT == side_manager.get_side()) {
if (false == rr_gsb.is_cb_exist(cb_type)) {
continue;
}
}
if (RIGHT == side_manager.get_side() || BOTTOM == side_manager.get_side()) {
if (RIGHT == side_manager.get_side() || TOP == side_manager.get_side()) {
/* Only for the condition where cbs are on perimeter, the neighbour cb
* will be invalid Bypass in such case on finding neighbour cbs
*/
if (TOP == side_manager.get_side() &&
instance_sb_coordinate.y() == device_rr_gsb.get_gsb_range().y()) {
continue;
}
if (RIGHT == side_manager.get_side() &&
instance_sb_coordinate.x() == device_rr_gsb.get_gsb_range().x()) {
continue;
}
const RRGSB& adjacent_gsb =
device_rr_gsb.get_gsb(module_gsb_cb_coordinate);
if (false == adjacent_gsb.is_cb_exist(cb_type)) {
@ -945,7 +956,8 @@ static int build_top_module_global_net_for_given_grid_module(
const BasicPort& tile_port_to_connect,
const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids,
const size_t& layer, const vtr::Point<size_t>& grid_coordinate,
const e_side& border_side, const vtr::Matrix<size_t>& grid_instance_ids) {
const e_side& border_side, const vtr::Matrix<size_t>& grid_instance_ids,
const bool& perimeter_cb) {
t_physical_tile_type_ptr physical_tile = grids.get_physical_type(
t_physical_tile_loc(grid_coordinate.x(), grid_coordinate.y(), layer));
/* Find the module name for this type of grid */
@ -963,6 +975,7 @@ static int build_top_module_global_net_for_given_grid_module(
/* Walk through each instance considering the unique sub tile and capacity
* range, each instance may have an independent pin to be driven by a global
* net! */
int curr_sub_tile_start_pin_index = 0;
for (const t_sub_tile& sub_tile : physical_tile->sub_tiles) {
VTR_ASSERT(1 == sub_tile.equivalent_sites.size());
int grid_pin_start_index = physical_tile->num_pins;
@ -983,16 +996,15 @@ static int build_top_module_global_net_for_given_grid_module(
/* Port size must match!!! */
if (false == ref_tile_port.contained(tile_port_to_connect)) {
VTR_LOG_ERROR(
"Tile annotation '%s' port '%s[%lu:%lu]' is out of the range of "
"physical tile port '%s[%lu:%lu]'!",
"Tile annotation '%s' port '%s' is out of the range of "
"physical tile port '%s'!\n",
tile_annotation.global_port_name(tile_global_port).c_str(),
tile_port_to_connect.get_name().c_str(),
tile_port_to_connect.get_lsb(), tile_port_to_connect.get_msb(),
ref_tile_port.get_name().c_str(), ref_tile_port.get_lsb(),
ref_tile_port.get_msb());
tile_port_to_connect.to_verilog_string().c_str(),
ref_tile_port.to_verilog_string().c_str());
return CMD_EXEC_FATAL_ERROR;
}
grid_pin_start_index =
curr_sub_tile_start_pin_index +
(subtile_index - sub_tile.capacity.low) * sub_tile_num_pins +
tile_port.absolute_first_pin_index;
physical_tile_port = tile_port;
@ -1022,7 +1034,7 @@ static int build_top_module_global_net_for_given_grid_module(
size_t grid_pin_height =
physical_tile->pin_height_offset[grid_pin_index];
std::vector<e_side> pin_sides = find_physical_tile_pin_side(
physical_tile, grid_pin_index, border_side);
physical_tile, grid_pin_index, border_side, perimeter_cb);
BasicPort grid_pin_info =
vpr_device_annotation.physical_tile_pin_port_info(physical_tile,
@ -1067,6 +1079,9 @@ static int build_top_module_global_net_for_given_grid_module(
}
}
}
/* Note that the start pin index for a new type of tile should be calculated
* by the accumulated number of pins of previous sub tiles */
curr_sub_tile_start_pin_index += sub_tile.num_phy_pins;
}
return CMD_EXEC_SUCCESS;
@ -1080,7 +1095,8 @@ static int build_top_module_global_net_from_grid_modules(
const ModulePortId& top_module_port, const TileAnnotation& tile_annotation,
const TileGlobalPortId& tile_global_port,
const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids,
const size_t& layer, const vtr::Matrix<size_t>& grid_instance_ids) {
const size_t& layer, const vtr::Matrix<size_t>& grid_instance_ids,
const bool& perimeter_cb) {
int status = CMD_EXEC_SUCCESS;
std::map<e_side, std::vector<vtr::Point<size_t>>> io_coordinates =
@ -1127,7 +1143,7 @@ static int build_top_module_global_net_from_grid_modules(
if (true == out_of_range) {
VTR_LOG_ERROR(
"Coordinate (%lu, %lu) in tile annotation for tile '%s' is out of "
"range (%lu:%lu, %lu:%lu)!",
"range (%lu:%lu, %lu:%lu)!\n",
range.x(), range.y(), tile_name.c_str(), start_coord.x(), end_coord.x(),
start_coord.y(), end_coord.y());
return CMD_EXEC_FATAL_ERROR;
@ -1158,7 +1174,8 @@ static int build_top_module_global_net_from_grid_modules(
status = build_top_module_global_net_for_given_grid_module(
module_manager, top_module, top_module_port, tile_annotation,
tile_global_port, tile_port, vpr_device_annotation, grids, layer,
vtr::Point<size_t>(ix, iy), NUM_SIDES, grid_instance_ids);
vtr::Point<size_t>(ix, iy), NUM_SIDES, grid_instance_ids,
perimeter_cb);
if (CMD_EXEC_FATAL_ERROR == status) {
return status;
}
@ -1205,7 +1222,7 @@ static int build_top_module_global_net_from_grid_modules(
status = build_top_module_global_net_for_given_grid_module(
module_manager, top_module, top_module_port, tile_annotation,
tile_global_port, tile_port, vpr_device_annotation, grids, layer,
io_coordinate, io_side, grid_instance_ids);
io_coordinate, io_side, grid_instance_ids, perimeter_cb);
if (CMD_EXEC_FATAL_ERROR == status) {
return status;
}
@ -1306,7 +1323,7 @@ int add_top_module_global_ports_from_grid_modules(
const DeviceRRGSB& device_rr_gsb,
const std::map<t_rr_type, vtr::Matrix<size_t>>& cb_instance_ids,
const vtr::Matrix<size_t>& grid_instance_ids, const ClockNetwork& clk_ntwk,
const RRClockSpatialLookup& rr_clock_lookup) {
const RRClockSpatialLookup& rr_clock_lookup, const bool& perimeter_cb) {
int status = CMD_EXEC_SUCCESS;
/* Add the global ports which are NOT yet added to the top-level module
@ -1371,7 +1388,7 @@ int add_top_module_global_ports_from_grid_modules(
status = build_top_module_global_net_from_grid_modules(
module_manager, top_module, top_module_port, tile_annotation,
tile_global_port, vpr_device_annotation, grids, layer,
grid_instance_ids);
grid_instance_ids, perimeter_cb);
}
if (status == CMD_EXEC_FATAL_ERROR) {
return status;

2
openfpga/src/fabric/build_top_module_connection.h
View File

@ -42,7 +42,7 @@ int add_top_module_global_ports_from_grid_modules(
const DeviceRRGSB& device_rr_gsb,
const std::map<t_rr_type, vtr::Matrix<size_t>>& cb_instance_ids,
const vtr::Matrix<size_t>& grid_instance_ids, const ClockNetwork& clk_ntwk,
const RRClockSpatialLookup& rr_clock_lookup);
const RRClockSpatialLookup& rr_clock_lookup, const bool& perimeter_cb);
void add_top_module_nets_prog_clock(ModuleManager& module_manager,
const ModuleId& top_module,

28
openfpga/src/fabric/build_top_module_memory.cpp
View File

@ -141,7 +141,7 @@ static void organize_top_module_tile_memory_modules(
const vtr::Point<size_t>& tile_coord, const e_side& tile_border_side) {
vtr::Point<size_t> gsb_coord_range = device_rr_gsb.get_gsb_range();
vtr::Point<size_t> gsb_coord(tile_coord.x(), tile_coord.y() - 1);
vtr::Point<size_t> gsb_coord(tile_coord.x(), tile_coord.y());
/* We do NOT consider SB and CBs if the gsb is not in the range! */
if ((gsb_coord.x() < gsb_coord_range.x()) &&
@ -370,12 +370,13 @@ void build_top_module_configurable_regions(
* Note: the organization of inter-tile aims to reduce the wire length
* to connect between tiles. Therefore, it is organized as a snake
* where we can avoid long wires between rows and columns
* Note: Corner I/Os only occur when perimeter cb is allowed
*
* +--------------------------------------------------------+
* | +------+------+-----+------+ |
* | | I/O | I/O | ... | I/O | |
* | | TOP | TOP | | TOP | |
* | +------+------+-----+------+ |
* | +------+ +------+------+-----+------+ +------+ |
* | | I/O | | I/O | I/O | ... | I/O | | I/O | |
* | | LEFT | | TOP | TOP | | TOP | | TOP | |
* | +------+ +------+------+-----+------+ +------+ |
* | +---------------------------------->tail |
* | +------+ | +------+------+-----+------+ +------+ |
* | | | | | | | | | | | |
@ -397,10 +398,10 @@ void build_top_module_configurable_regions(
* | | LEFT | | [0] | [1] | | [i] | | |RIGHT | |
* | +------+ +------+------+-----+------+ | +------+ |
* +-------------------------------------------+ |
* +------+------+-----+------+ |
* | I/O | I/O | ... | I/O | |
* |BOTTOM|BOTTOM| |BOTTOM| |
* +------+------+-----+------+ |
* +------+ +------+------+-----+------+ +------+ |
* | I/O | | I/O | I/O | ... | I/O | | I/O | |
* |BOTTOM| |BOTTOM|BOTTOM| |BOTTOM| |RIGHT | |
* +------+ +------+------+-----+------+ +------+ |
* head >-----------------------------------------------+
*
* Inner tile connection:
@ -458,12 +459,12 @@ void organize_top_module_memory_modules(
std::map<e_side, std::vector<vtr::Point<size_t>>> io_coords;
/* BOTTOM side I/Os */
for (size_t ix = 1; ix < grids.width() - 1; ++ix) {
for (size_t ix = 0; ix < grids.width() - 1; ++ix) {
io_coords[BOTTOM].push_back(vtr::Point<size_t>(ix, 0));
}
/* RIGHT side I/Os */
for (size_t iy = 1; iy < grids.height() - 1; ++iy) {
for (size_t iy = 0; iy < grids.height() - 1; ++iy) {
io_coords[RIGHT].push_back(vtr::Point<size_t>(grids.width() - 1, iy));
}
@ -483,13 +484,12 @@ void organize_top_module_memory_modules(
* +--------+ +--------+
*
*/
for (size_t ix = grids.width() - 2; ix >= 1; --ix) {
for (size_t ix = grids.width() - 1; ix >= 1; --ix) {
io_coords[TOP].push_back(vtr::Point<size_t>(ix, grids.height() - 1));
}
io_coords[TOP].push_back(vtr::Point<size_t>(0, grids.height() - 1));
/* LEFT side I/Os */
for (size_t iy = grids.height() - 2; iy >= 1; --iy) {
for (size_t iy = grids.height() - 1; iy >= 1; --iy) {
io_coords[LEFT].push_back(vtr::Point<size_t>(0, iy));
}

8
openfpga/src/fabric/build_top_module_utils.cpp
View File

@ -100,13 +100,13 @@ vtr::Point<size_t> find_top_module_gsb_coordinate_by_sb_side(
vtr::Point<size_t> gsb_coordinate;
if ((TOP == sb_side) || (LEFT == sb_side)) {
if ((BOTTOM == sb_side) || (LEFT == sb_side)) {
gsb_coordinate.set_x(rr_gsb.get_x());
gsb_coordinate.set_y(rr_gsb.get_y());
return gsb_coordinate;
}
VTR_ASSERT((RIGHT == sb_side) || (BOTTOM == sb_side));
VTR_ASSERT((RIGHT == sb_side) || (TOP == sb_side));
/* RIGHT side: x + 1 */
if (RIGHT == sb_side) {
@ -115,9 +115,9 @@ vtr::Point<size_t> find_top_module_gsb_coordinate_by_sb_side(
}
/* BOTTOM side: y - 1 */
if (BOTTOM == sb_side) {
if (TOP == sb_side) {
gsb_coordinate.set_x(rr_gsb.get_x());
gsb_coordinate.set_y(rr_gsb.get_y() - 1);
gsb_coordinate.set_y(rr_gsb.get_y() + 1);
}
return gsb_coordinate;

9
openfpga/src/fpga_verilog/fabric_verilog_options.cpp
View File

@ -21,6 +21,7 @@ FabricVerilogOption::FabricVerilogOption() {
default_net_type_ = VERILOG_DEFAULT_NET_TYPE_NONE;
time_stamp_ = true;
use_relative_path_ = false;
constant_undriven_inputs_ = false;
verbose_output_ = false;
}
@ -53,6 +54,10 @@ e_verilog_default_net_type FabricVerilogOption::default_net_type() const {
return default_net_type_;
}
bool FabricVerilogOption::constant_undriven_inputs() const {
return constant_undriven_inputs_;
}
bool FabricVerilogOption::verbose_output() const { return verbose_output_; }
/******************************************************************************
@ -106,6 +111,10 @@ void FabricVerilogOption::set_default_net_type(
}
}
void FabricVerilogOption::set_constant_undriven_inputs(const bool& enabled) {
constant_undriven_inputs_ = enabled;
}
void FabricVerilogOption::set_verbose_output(const bool& enabled) {
verbose_output_ = enabled;
}

3
openfpga/src/fpga_verilog/fabric_verilog_options.h
View File

@ -28,6 +28,7 @@ class FabricVerilogOption {
bool compress_routing() const;
e_verilog_default_net_type default_net_type() const;
bool print_user_defined_template() const;
bool constant_undriven_inputs() const;
bool verbose_output() const;
public: /* Public mutators */
@ -39,6 +40,7 @@ class FabricVerilogOption {
void set_compress_routing(const bool& enabled);
void set_print_user_defined_template(const bool& enabled);
void set_default_net_type(const std::string& default_net_type);
void set_constant_undriven_inputs(const bool& enabled);
void set_verbose_output(const bool& enabled);
private: /* Internal Data */
@ -50,6 +52,7 @@ class FabricVerilogOption {
e_verilog_default_net_type default_net_type_;
bool time_stamp_;
bool use_relative_path_;
bool constant_undriven_inputs_;
bool verbose_output_;
};

13
openfpga/src/fpga_verilog/verilog_grid.cpp
View File

@ -114,6 +114,7 @@ static void print_verilog_primitive_block(
/* Write the verilog module */
write_verilog_module_to_file(fp, module_manager, primitive_module, true,
options.constant_undriven_inputs(),
options.default_net_type());
/* Close file handler */
@ -232,9 +233,9 @@ static void rec_print_verilog_logical_tile(
std::string(physical_pb_type->name) + " -----"));
/* Write the verilog module */
write_verilog_module_to_file(fp, module_manager, pb_module,
options.explicit_port_mapping(),
options.default_net_type());
write_verilog_module_to_file(
fp, module_manager, pb_module, options.explicit_port_mapping(),
options.constant_undriven_inputs(), options.default_net_type());
print_verilog_comment(
fp,
@ -346,9 +347,9 @@ static void print_verilog_physical_tile_netlist(
print_verilog_comment(
fp, std::string("----- BEGIN Grid Verilog module: " +
module_manager.module_name(grid_module) + " -----"));
write_verilog_module_to_file(fp, module_manager, grid_module,
options.explicit_port_mapping(),
options.default_net_type());
write_verilog_module_to_file(
fp, module_manager, grid_module, options.explicit_port_mapping(),
options.constant_undriven_inputs(), options.default_net_type());
print_verilog_comment(
fp, std::string("----- END Grid Verilog module: " +

2
openfpga/src/fpga_verilog/verilog_lut.cpp
View File

@ -63,7 +63,7 @@ void print_verilog_submodule_luts(const ModuleManager& module_manager,
fp, module_manager, lut_module,
options.explicit_port_mapping() ||
circuit_lib.dump_explicit_port_map(lut_model),
options.default_net_type());
options.constant_undriven_inputs(), options.default_net_type());
}
/* Close the file handler */

12
openfpga/src/fpga_verilog/verilog_memory.cpp
View File

@ -61,7 +61,7 @@ static void print_verilog_mux_memory_module(
fp, module_manager, mem_module,
options.explicit_port_mapping() ||
circuit_lib.dump_explicit_port_map(mux_model),
options.default_net_type());
options.constant_undriven_inputs(), options.default_net_type());
/* Add an empty line as a splitter */
fp << std::endl;
@ -84,7 +84,7 @@ static void print_verilog_mux_memory_module(
fp, module_manager, feedthru_mem_module,
options.explicit_port_mapping() ||
circuit_lib.dump_explicit_port_map(mux_model),
options.default_net_type());
options.constant_undriven_inputs(), options.default_net_type());
/* Add an empty line as a splitter */
fp << std::endl;
@ -208,6 +208,7 @@ void print_verilog_submodule_memories(
write_verilog_module_to_file(fp, module_manager, mem_module,
options.explicit_port_mapping() ||
circuit_lib.dump_explicit_port_map(model),
options.constant_undriven_inputs(),
options.default_net_type());
/* Add an empty line as a splitter */
@ -228,6 +229,7 @@ void print_verilog_submodule_memories(
write_verilog_module_to_file(fp, module_manager, feedthru_mem_module,
options.explicit_port_mapping() ||
circuit_lib.dump_explicit_port_map(model),
options.constant_undriven_inputs(),
options.default_net_type());
/* Add an empty line as a splitter */
@ -239,9 +241,9 @@ void print_verilog_submodule_memories(
for (ModuleId mem_group_module : module_manager.modules_by_usage(
ModuleManager::e_module_usage_type::MODULE_CONFIG_GROUP)) {
/* Write the module content in Verilog format */
write_verilog_module_to_file(fp, module_manager, mem_group_module,
options.explicit_port_mapping(),
options.default_net_type());
write_verilog_module_to_file(
fp, module_manager, mem_group_module, options.explicit_port_mapping(),
options.constant_undriven_inputs(), options.default_net_type());
/* Add an empty line as a splitter */
fp << std::endl;

122
openfpga/src/fpga_verilog/verilog_module_writer.cpp
View File

@ -139,6 +139,66 @@ static BasicPort generate_verilog_port_for_module_net(
return port_to_return;
}
/********************************************************************
* Find all the undriven nets that are going to be local wires
* And organize it in a vector of ports
* Verilog wire writter function will use the output of this function
* to write up local wire declaration in Verilog format
*******************************************************************/
static void find_verilog_module_local_undriven_wires(
std::map<std::string, std::vector<BasicPort>>& local_wires,
const ModuleManager& module_manager, const ModuleId& module_id,
const std::vector<ModuleManager::e_module_port_type>& port_type_blacklist) {
/* Local wires could also happen for undriven ports of child module */
for (const ModuleId& child : module_manager.child_modules(module_id)) {
for (size_t instance :
module_manager.child_module_instances(module_id, child)) {
for (const ModulePortId& child_port_id :
module_manager.module_ports(child)) {
BasicPort child_port = module_manager.module_port(child, child_port_id);
ModuleManager::e_module_port_type child_port_type =
module_manager.port_type(child, child_port_id);
bool filter_out = false;
for (ModuleManager::e_module_port_type curr_port_type :
port_type_blacklist) {
if (child_port_type == curr_port_type) {
filter_out = true;
break;
}
}
if (filter_out) {
continue;
}
std::vector<size_t> undriven_pins;
for (size_t child_pin : child_port.pins()) {
/* Find the net linked to the pin */
ModuleNetId net = module_manager.module_instance_port_net(
module_id, child, instance, child_port_id, child_pin);
/* We only care undriven ports */
if (ModuleNetId::INVALID() == net) {
undriven_pins.push_back(child_pin);
}
}
if (true == undriven_pins.empty()) {
continue;
}
/* Reach here, we need a local wire, we will create a port only for the
* undriven pins of the port! */
BasicPort instance_port;
instance_port.set_name(generate_verilog_undriven_local_wire_name(
module_manager, module_id, child, instance, child_port_id));
/* We give the same port name as child module, this case happens to
* global ports */
instance_port.set_width(
*std::min_element(undriven_pins.begin(), undriven_pins.end()),
*std::max_element(undriven_pins.begin(), undriven_pins.end()));
local_wires[instance_port.get_name()].push_back(instance_port);
}
}
}
}
/********************************************************************
* Find all the nets that are going to be local wires
* And organize it in a vector of ports
@ -206,41 +266,9 @@ find_verilog_module_local_wires(const ModuleManager& module_manager,
}
}
/* Local wires could also happen for undriven ports of child module */
for (const ModuleId& child : module_manager.child_modules(module_id)) {
for (size_t instance :
module_manager.child_module_instances(module_id, child)) {
for (const ModulePortId& child_port_id :
module_manager.module_ports(child)) {
BasicPort child_port = module_manager.module_port(child, child_port_id);
std::vector<size_t> undriven_pins;
for (size_t child_pin : child_port.pins()) {
/* Find the net linked to the pin */
ModuleNetId net = module_manager.module_instance_port_net(
module_id, child, instance, child_port_id, child_pin);
/* We only care undriven ports */
if (ModuleNetId::INVALID() == net) {
undriven_pins.push_back(child_pin);
}
}
if (true == undriven_pins.empty()) {
continue;
}
/* Reach here, we need a local wire, we will create a port only for the
* undriven pins of the port! */
BasicPort instance_port;
instance_port.set_name(generate_verilog_undriven_local_wire_name(
module_manager, module_id, child, instance, child_port_id));
/* We give the same port name as child module, this case happens to
* global ports */
instance_port.set_width(
*std::min_element(undriven_pins.begin(), undriven_pins.end()),
*std::max_element(undriven_pins.begin(), undriven_pins.end()));
local_wires[instance_port.get_name()].push_back(instance_port);
}
}
}
find_verilog_module_local_undriven_wires(
local_wires, module_manager, module_id,
std::vector<ModuleManager::e_module_port_type>());
return local_wires;
}
@ -545,6 +573,7 @@ static void write_verilog_instance_to_file(std::fstream& fp,
void write_verilog_module_to_file(
std::fstream& fp, const ModuleManager& module_manager,
const ModuleId& module_id, const bool& use_explicit_port_map,
const bool& constant_local_undriven_wires,
const e_verilog_default_net_type& default_net_type) {
VTR_ASSERT(true == valid_file_stream(fp));
@ -575,6 +604,29 @@ void write_verilog_module_to_file(
}
}
/* Use constant to drive undriven local wires */
if (constant_local_undriven_wires) {
std::vector<ModuleManager::e_module_port_type> blacklist = {
ModuleManager::e_module_port_type::MODULE_GLOBAL_PORT,
ModuleManager::e_module_port_type::MODULE_GPIN_PORT,
ModuleManager::e_module_port_type::MODULE_GPOUT_PORT,
ModuleManager::e_module_port_type::MODULE_GPIO_PORT,
ModuleManager::e_module_port_type::MODULE_INOUT_PORT,
ModuleManager::e_module_port_type::MODULE_OUTPUT_PORT,
ModuleManager::e_module_port_type::MODULE_CLOCK_PORT};
std::map<std::string, std::vector<BasicPort>> local_undriven_wires;
find_verilog_module_local_undriven_wires(
local_undriven_wires, module_manager, module_id, blacklist);
for (std::pair<std::string, std::vector<BasicPort>> port_group :
local_undriven_wires) {
for (const BasicPort& local_undriven_wire : port_group.second) {
print_verilog_wire_constant_values(
fp, local_undriven_wire,
std::vector<size_t>(local_undriven_wire.get_width(), 0));
}
}
}
/* Print an empty line as splitter */
fp << std::endl;

1
openfpga/src/fpga_verilog/verilog_module_writer.h
View File

@ -19,6 +19,7 @@ namespace openfpga {
void write_verilog_module_to_file(
std::fstream& fp, const ModuleManager& module_manager,
const ModuleId& module_id, const bool& use_explicit_port_map,
const bool& constant_local_undriven_wires,
const e_verilog_default_net_type& default_net_type);
} /* end namespace openfpga */

4
openfpga/src/fpga_verilog/verilog_mux.cpp
View File

@ -679,7 +679,7 @@ static void generate_verilog_mux_branch_module(
fp, module_manager, mux_module,
use_explicit_port_map ||
circuit_lib.dump_explicit_port_map(mux_model),
default_net_type);
false, default_net_type);
/* Add an empty line as a splitter */
fp << std::endl;
} else {
@ -1423,7 +1423,7 @@ static void generate_verilog_mux_module(
circuit_lib.dump_explicit_port_map(mux_model) ||
circuit_lib.dump_explicit_port_map(
circuit_lib.pass_gate_logic_model(mux_model))),
default_net_type);
false, default_net_type);
/* Add an empty line as a splitter */
fp << std::endl;
break;

12
openfpga/src/fpga_verilog/verilog_routing.cpp
View File

@ -115,9 +115,9 @@ static void print_verilog_routing_connection_box_unique_module(
VTR_ASSERT(true == module_manager.valid_module_id(cb_module));
/* Write the verilog module */
write_verilog_module_to_file(fp, module_manager, cb_module,
options.explicit_port_mapping(),
options.default_net_type());
write_verilog_module_to_file(
fp, module_manager, cb_module, options.explicit_port_mapping(),
options.constant_undriven_inputs(), options.default_net_type());
/* Add an empty line as a splitter */
fp << std::endl;
@ -236,9 +236,9 @@ static void print_verilog_routing_switch_box_unique_module(
VTR_ASSERT(true == module_manager.valid_module_id(sb_module));
/* Write the verilog module */
write_verilog_module_to_file(fp, module_manager, sb_module,
options.explicit_port_mapping(),
options.default_net_type());
write_verilog_module_to_file(
fp, module_manager, sb_module, options.explicit_port_mapping(),
options.constant_undriven_inputs(), options.default_net_type());
/* Close file handler */
fp.close();

12
openfpga/src/fpga_verilog/verilog_shift_register_banks.cpp
View File

@ -56,9 +56,9 @@ void print_verilog_submodule_shift_register_banks(
for (const ModuleId& sr_module : blwl_sr_banks.bl_bank_unique_modules()) {
VTR_ASSERT(true == module_manager.valid_module_id(sr_module));
/* Write the module content in Verilog format */
write_verilog_module_to_file(fp, module_manager, sr_module,
options.explicit_port_mapping(),
options.default_net_type());
write_verilog_module_to_file(
fp, module_manager, sr_module, options.explicit_port_mapping(),
options.constant_undriven_inputs(), options.default_net_type());
/* Add an empty line as a splitter */
fp << std::endl;
@ -67,9 +67,9 @@ void print_verilog_submodule_shift_register_banks(
for (const ModuleId& sr_module : blwl_sr_banks.wl_bank_unique_modules()) {
VTR_ASSERT(true == module_manager.valid_module_id(sr_module));
/* Write the module content in Verilog format */
write_verilog_module_to_file(fp, module_manager, sr_module,
options.explicit_port_mapping(),
options.default_net_type());
write_verilog_module_to_file(
fp, module_manager, sr_module, options.explicit_port_mapping(),
options.constant_undriven_inputs(), options.default_net_type());
/* Add an empty line as a splitter */
fp << std::endl;

6
openfpga/src/fpga_verilog/verilog_tile.cpp
View File

@ -58,9 +58,9 @@ static int print_verilog_tile_module_netlist(
options.time_stamp());
/* Write the module content in Verilog format */
write_verilog_module_to_file(fp, module_manager, tile_module,
options.explicit_port_mapping(),
options.default_net_type());
write_verilog_module_to_file(
fp, module_manager, tile_module, options.explicit_port_mapping(),
options.constant_undriven_inputs(), options.default_net_type());
/* Add an empty line as a splitter */
fp << std::endl;

12
openfpga/src/fpga_verilog/verilog_top_module.cpp
View File

@ -61,9 +61,9 @@ void print_verilog_core_module(NetlistManager& netlist_manager,
options.time_stamp());
/* Write the module content in Verilog format */
write_verilog_module_to_file(fp, module_manager, core_module,
options.explicit_port_mapping(),
options.default_net_type());
write_verilog_module_to_file(
fp, module_manager, core_module, options.explicit_port_mapping(),
options.constant_undriven_inputs(), options.default_net_type());
/* Add an empty line as a splitter */
fp << std::endl;
@ -127,9 +127,9 @@ void print_verilog_top_module(NetlistManager& netlist_manager,
fp, std::string("Top-level Verilog module for FPGA"), options.time_stamp());
/* Write the module content in Verilog format */
write_verilog_module_to_file(fp, module_manager, top_module,
options.explicit_port_mapping(),
options.default_net_type());
write_verilog_module_to_file(
fp, module_manager, top_module, options.explicit_port_mapping(),
options.constant_undriven_inputs(), options.default_net_type());
/* Add an empty line as a splitter */
fp << std::endl;

36
openfpga/src/utils/openfpga_physical_tile_utils.cpp
View File

@ -27,7 +27,7 @@ namespace openfpga {
*******************************************************************/
std::vector<e_side> find_physical_tile_pin_side(
t_physical_tile_type_ptr physical_tile, const int& physical_pin,
const e_side& border_side) {
const e_side& border_side, const bool& perimeter_cb) {
std::vector<e_side> pin_sides;
for (const e_side& side_cand : {TOP, RIGHT, BOTTOM, LEFT}) {
int pin_width_offset = physical_tile->pin_width_offset[physical_pin];
@ -40,17 +40,21 @@ std::vector<e_side> find_physical_tile_pin_side(
/* For regular grid, we should have pin only one side!
* I/O grids: VPR creates the grid with duplicated pins on every side
* but the expected side (only used side) will be opposite side of the border
* side!
* - In regular cases: the expected side (only used side) will be on the
* opposite to the border side!
* - When perimeter cb is on, the expected sides can be on any sides except
* the border side. But we only expect 1 side
*/
if (NUM_SIDES == border_side) {
VTR_ASSERT(1 == pin_sides.size());
} else {
} else if (!perimeter_cb) {
SideManager side_manager(border_side);
VTR_ASSERT(pin_sides.end() != std::find(pin_sides.begin(), pin_sides.end(),
side_manager.get_opposite()));
pin_sides.clear();
pin_sides.push_back(side_manager.get_opposite());
} else {
VTR_ASSERT(1 == pin_sides.size() && pin_sides[0] != border_side);
}
return pin_sides;
@ -141,9 +145,6 @@ int find_physical_tile_pin_index(t_physical_tile_type_ptr physical_tile,
}
PortParser tile_parser(pin_tokens[0]);
BasicPort tile_info = tile_parser.port();
if (tile_info.get_name() != std::string(physical_tile->name)) {
return pin_idx;
}
if (!tile_info.is_valid()) {
VTR_LOG_ERROR(
"Invalid pin name '%s' whose subtile index is not valid, expect [0, "
@ -159,13 +160,6 @@ int find_physical_tile_pin_index(t_physical_tile_type_ptr physical_tile,
pin_name.c_str());
exit(1);
}
if (tile_info.get_msb() > size_t(physical_tile->capacity) - 1) {
VTR_LOG_ERROR(
"Invalid pin name '%s' whose subtile index is out of range, expect [0, "
"%lu]\n",
pin_name.c_str(), physical_tile->capacity - 1);
exit(1);
}
/* precheck: return unfound pin if the pin index does not match */
PortParser pin_parser(pin_tokens[1]);
BasicPort pin_info = pin_parser.port();
@ -180,9 +174,18 @@ int find_physical_tile_pin_index(t_physical_tile_type_ptr physical_tile,
/* Spot the subtile by using the index */
for (const t_sub_tile& sub_tile : physical_tile->sub_tiles) {
if (!sub_tile.capacity.is_in_range(tile_info.get_lsb())) {
/* Bypass unmatched subtiles*/
if (tile_info.get_name() != std::string(sub_tile.name)) {
continue;
}
if (!sub_tile.capacity.is_in_range(tile_info.get_lsb())) {
VTR_LOG_ERROR(
"Invalid pin name '%s' whose subtile index is out of range, expect "
"[%lu, "
"%lu]\n",
pin_name.c_str(), sub_tile.capacity.low, sub_tile.capacity.high);
exit(1);
}
for (const t_physical_tile_port& sub_tile_port : sub_tile.ports) {
if (std::string(sub_tile_port.name) != pin_info.get_name()) {
continue;
@ -204,7 +207,8 @@ int find_physical_tile_pin_index(t_physical_tile_type_ptr physical_tile,
/* Reach here, we get the port we want, return the accumulated index */
size_t accumulated_pin_idx =
sub_tile_port.absolute_first_pin_index +
sub_tile.num_phy_pins * (tile_info.get_lsb() - sub_tile.capacity.low) +
(sub_tile.num_phy_pins / sub_tile.capacity.total()) *
(tile_info.get_lsb() - sub_tile.capacity.low) +
pin_info.get_lsb();
return accumulated_pin_idx;
}

2
openfpga/src/utils/openfpga_physical_tile_utils.h
View File

@ -20,7 +20,7 @@ namespace openfpga {
std::vector<e_side> find_physical_tile_pin_side(
t_physical_tile_type_ptr physical_tile, const int& physical_pin,
const e_side& border_side);
const e_side& border_side, const bool& perimeter_cb);
float find_physical_tile_pin_Fc(t_physical_tile_type_ptr type, const int& pin);

204
openfpga_flow/openfpga_arch/k4_N4_40nm_ClkNtwk_registerable_io_cc_openfpga.xml Normal file
View File

@ -0,0 +1,204 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml
- General purpose logic block
- K = 6, N = 10, I = 40
- Single mode
- Routing architecture
- L = 4, fc_in = 0.15, fc_out = 0.1
-->
<openfpga_architecture>
<technology_library>
<device_library>
<device_model name="logic" type="transistor">
<lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
<design vdd="0.9" pn_ratio="2"/>
<pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
<nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
</device_model>
<device_model name="io" type="transistor">
<lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
<design vdd="2.5" pn_ratio="3"/>
<pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
<nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
</device_model>
</device_library>
<variation_library>
<variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
<variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
</variation_library>
</technology_library>
<circuit_library>
<circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
<design_technology type="cmos" topology="inverter" size="1"/>
<device_technology device_model_name="logic"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
10e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</circuit_model>
<circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
<design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
<device_technology device_model_name="logic"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
10e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</circuit_model>
<circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
<design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
<device_technology device_model_name="logic"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
10e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</circuit_model>
<circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
<design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
<device_technology device_model_name="logic"/>
<input_buffer exist="false"/>
<output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/>
<port type="input" prefix="sel" size="1"/>
<port type="input" prefix="selb" size="1"/>
<port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="in sel selb" out_port="out">
10e-12 5e-12 5e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in sel selb" out_port="out">
10e-12 5e-12 5e-12
</delay_matrix>
</circuit_model>
<circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
<design_technology type="cmos"/>
<input_buffer exist="false"/>
<output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/>
<input_buffer exist="false"/>
<output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model>
<circuit_model type="mux" name="mux_tree" prefix="mux_tree" dump_structural_verilog="true">
<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1"/>
</circuit_model>
<circuit_model type="mux" name="mux_tree_tapbuf" prefix="mux_tree_tapbuf" is_default="true" dump_structural_verilog="true">
<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="tap_buf4"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1"/>
</circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="false" default_val="0"/>
</circuit_model>
<circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>
<lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
<lut_input_buffer exist="true" circuit_model_name="buf4"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="4"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="16"/>
</circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="DFF" prefix="DFF" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/>
<port type="output" prefix="QN" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="inout" prefix="PAD" size="1" is_global="true" is_io="true" is_data_io="true"/>
<port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="DFF" default_val="1"/>
<port type="input" prefix="outpad" lib_name="A" size="1"/>
<port type="output" prefix="inpad" lib_name="Y" size="1"/>
</circuit_model>
</circuit_library>
<configuration_protocol>
<organization type="scan_chain" circuit_model_name="DFF"/>
</configuration_protocol>
<connection_block>
<switch name="ipin_cblock" circuit_model_name="mux_tree_tapbuf"/>
</connection_block>
<switch_block>
<switch name="0" circuit_model_name="mux_tree_tapbuf"/>
</switch_block>
<routing_segment>
<segment name="L1" circuit_model_name="chan_segment"/>
<segment name="L4" circuit_model_name="chan_segment"/>
</routing_segment>
<tile_annotations>
<global_port name="clk" is_clock="true" default_val="0" clock_arch_tree_name="clk_tree_2lvl">
<tile name="clb" port="clk" x="-1" y="-1"/>
<tile name="io_top" port="clk" x="-1" y="-1"/>
<tile name="io_right" port="clk" x="-1" y="-1"/>
<tile name="io_bottom" port="clk" x="-1" y="-1"/>
<tile name="io_left" port="clk" x="-1" y="-1"/>
</global_port>
</tile_annotations>
<pb_type_annotations>
<!-- physical pb_type binding in complex block IO -->
<pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
<pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/>
<pb_type name="io[physical].ff" circuit_model_name="DFFSRQ"/>
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[inpad_registered].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[inpad_registered].ff" physical_pb_type_name="io[physical].ff"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified -->
<pb_type name="clb">
<!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
<interconnect name="crossbar" circuit_model_name="mux_tree"/>
</pb_type>
<pb_type name="clb.fle[n1_lut4].ble4.lut4" circuit_model_name="lut4"/>
<pb_type name="clb.fle[n1_lut4].ble4.ff" circuit_model_name="DFFSRQ"/>
<!-- End physical pb_type binding in complex block IO -->
</pb_type_annotations>
</openfpga_architecture>

204
openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_PerimeterCb_registerable_io_cc_openfpga.xml Normal file
View File

@ -0,0 +1,204 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml
- General purpose logic block
- K = 6, N = 10, I = 40
- Single mode
- Routing architecture
- L = 4, fc_in = 0.15, fc_out = 0.1
-->
<openfpga_architecture>
<technology_library>
<device_library>
<device_model name="logic" type="transistor">
<lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
<design vdd="0.9" pn_ratio="2"/>
<pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
<nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
</device_model>
<device_model name="io" type="transistor">
<lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
<design vdd="2.5" pn_ratio="3"/>
<pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
<nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
</device_model>
</device_library>
<variation_library>
<variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
<variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
</variation_library>
</technology_library>
<circuit_library>
<circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
<design_technology type="cmos" topology="inverter" size="1"/>
<device_technology device_model_name="logic"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
10e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</circuit_model>
<circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
<design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
<device_technology device_model_name="logic"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
10e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</circuit_model>
<circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
<design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
<device_technology device_model_name="logic"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
10e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</circuit_model>
<circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
<design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
<device_technology device_model_name="logic"/>
<input_buffer exist="false"/>
<output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/>
<port type="input" prefix="sel" size="1"/>
<port type="input" prefix="selb" size="1"/>
<port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="in sel selb" out_port="out">
10e-12 5e-12 5e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in sel selb" out_port="out">
10e-12 5e-12 5e-12
</delay_matrix>
</circuit_model>
<circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
<design_technology type="cmos"/>
<input_buffer exist="false"/>
<output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/>
<input_buffer exist="false"/>
<output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model>
<circuit_model type="mux" name="mux_tree" prefix="mux_tree" dump_structural_verilog="true">
<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1"/>
</circuit_model>
<circuit_model type="mux" name="mux_tree_tapbuf" prefix="mux_tree_tapbuf" is_default="true" dump_structural_verilog="true">
<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="tap_buf4"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1"/>
</circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="false" default_val="0"/>
</circuit_model>
<circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>
<lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
<lut_input_buffer exist="true" circuit_model_name="buf4"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="4"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="16"/>
</circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="DFF" prefix="DFF" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/>
<port type="output" prefix="QN" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="inout" prefix="PAD" size="1" is_global="true" is_io="true" is_data_io="true"/>
<port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="DFF" default_val="1"/>
<port type="input" prefix="outpad" lib_name="A" size="1"/>
<port type="output" prefix="inpad" lib_name="Y" size="1"/>
</circuit_model>
</circuit_library>
<configuration_protocol>
<organization type="scan_chain" circuit_model_name="DFF"/>
</configuration_protocol>
<connection_block>
<switch name="ipin_cblock" circuit_model_name="mux_tree_tapbuf"/>
</connection_block>
<switch_block>
<switch name="0" circuit_model_name="mux_tree_tapbuf"/>
</switch_block>
<routing_segment>
<segment name="L1" circuit_model_name="chan_segment"/>
<segment name="L4" circuit_model_name="chan_segment"/>
</routing_segment>
<tile_annotations>
<global_port name="clk" is_clock="true" default_val="0">
<tile name="clb" port="clk" x="-1" y="-1"/>
<tile name="io_top" port="clk" x="-1" y="-1"/>
<tile name="io_right" port="clk" x="-1" y="-1"/>
<tile name="io_bottom" port="clk" x="-1" y="-1"/>
<tile name="io_left" port="clk" x="-1" y="-1"/>
</global_port>
</tile_annotations>
<pb_type_annotations>
<!-- physical pb_type binding in complex block IO -->
<pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
<pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/>
<pb_type name="io[physical].ff" circuit_model_name="DFFSRQ"/>
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[inpad_registered].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[inpad_registered].ff" physical_pb_type_name="io[physical].ff"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified -->
<pb_type name="clb">
<!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
<interconnect name="crossbar" circuit_model_name="mux_tree"/>
</pb_type>
<pb_type name="clb.fle[n1_lut4].ble4.lut4" circuit_model_name="lut4"/>
<pb_type name="clb.fle[n1_lut4].ble4.ff" circuit_model_name="DFFSRQ"/>
<!-- End physical pb_type binding in complex block IO -->
</pb_type_annotations>
</openfpga_architecture>

6
openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_registerable_io_cc_openfpga.xml
View File

@ -195,10 +195,10 @@
<pb_type name="io[inpad_registered].ff" physical_pb_type_name="io[physical].ff"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<pb_type name="io_input" physical_mode_name="physical" idle_mode_name="inpad"/>
<pb_type name="io_input[physical].iopad" circuit_model_name="GPIN" mode_bits="1"/>
<pb_type name="io_input[physical].iopad" circuit_model_name="GPIN"/>
<pb_type name="io_input[physical].ff" circuit_model_name="DFFSRQ"/>
<pb_type name="io_input[inpad].inpad" physical_pb_type_name="io_input[physical].iopad" mode_bits="1"/>
<pb_type name="io_input[inpad_registered].inpad" physical_pb_type_name="io_input[physical].iopad" mode_bits="1"/>
<pb_type name="io_input[inpad].inpad" physical_pb_type_name="io_input[physical].iopad"/>
<pb_type name="io_input[inpad_registered].inpad" physical_pb_type_name="io_input[physical].iopad"/>
<pb_type name="io_input[inpad_registered].ff" physical_pb_type_name="io_input[physical].ff"/>
<!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB -->

5
openfpga_flow/regression_test_scripts/basic_reg_test.sh
View File

@ -190,10 +190,15 @@ run-task basic_tests/tile_organization/tileable_io $@
echo -e "Testing tiles with I/O consisting of subtiles";
run-task basic_tests/tile_organization/io_subtile $@
run-task basic_tests/tile_organization/io_subtile_strong $@
echo -e "Testing tiles with routing tracks around I/O";
run-task basic_tests/tile_organization/perimeter_cb $@
echo -e "Testing tile grouping on a homogeneous FPGA fabric (Full testbench)";
run-task basic_tests/tile_organization/homo_fabric_tile $@
run-task basic_tests/tile_organization/homo_fabric_tile_bl $@
echo -e "Testing tile grouping on a homogeneous FPGA fabric (Preconfigured testbench)";
run-task basic_tests/tile_organization/fabric_tile_global_tile_clock_io_subtile $@
run-task basic_tests/tile_organization/fabric_tile_perimeter_cb_global_tile_clock $@
run-task basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile $@
run-task basic_tests/tile_organization/homo_fabric_tile_preconfig $@
run-task basic_tests/tile_organization/homo_fabric_tile_2x2_preconfig $@
run-task basic_tests/tile_organization/homo_fabric_tile_4x4_preconfig $@

2
openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock_subtile/config/task.conf
View File

@ -20,7 +20,7 @@ openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scrip
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_registerable_io_cc_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
openfpga_vpr_device_layout=2x2_hybrid_io
openfpga_vpr_route_chan_width=60
openfpga_vpr_route_chan_width=20
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTileClk_registerable_io_40nm.xml

2
openfpga_flow/tasks/basic_tests/k4_series/k4n4_ecb/config/task.conf
View File

@ -22,7 +22,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio
openfpga_vpr_device_layout=2x2
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_ecb_tileable_TileOrgzBr_40nm.xml
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_ecb_tileable_TileOrgzBl_40nm.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif

56
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc
View File

@ -57,16 +57,24 @@ set_disable_timing gfpga_pad_GPIO_PAD[31]
set_disable_timing set[0]
set_disable_timing reset[0]
set_disable_timing prog_clk[0]
set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
@ -77,6 +85,10 @@ set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
@ -91,30 +103,18 @@ set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q

840
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/ccff_timing.sdc
View File

@ -11,346 +11,6 @@
#############################################
set_units -time ns
set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFF_2_/D 5
@ -465,84 +125,8 @@ set_max_delay -from fpga_top/sb_0__0_/mem_right_track_22/DFF_1_/Q -to fpga_top/s
set_min_delay -from fpga_top/sb_0__0_/mem_right_track_22/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_24/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__0_/mem_right_track_24/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_24/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__0_/mem_right_track_24/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_24/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__0_/mem_right_track_24/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__0_/mem_right_track_24/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__0_/mem_right_track_24/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__0_/mem_right_track_24/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_2_/D 5
@ -725,8 +309,424 @@ set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_0_/Q -to fpga_top/cbx_
set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_1_/D 5
set_min_delay -from fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_2_/D 5

56
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/disable_configurable_memory_outputs.sdc
View File

@ -6,16 +6,24 @@
# Organization: University of Utah
#############################################
set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
@ -26,6 +34,10 @@ set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
@ -40,30 +52,18 @@ set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q

256
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_bitstream.bit
View File

@ -197,18 +197,7 @@
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
@ -243,8 +232,19 @@
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
@ -267,67 +267,6 @@
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
@ -423,34 +362,61 @@
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
@ -485,19 +451,8 @@
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
@ -515,16 +470,61 @@
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

716
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_bitstream.xml
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File diff suppressed because it is too large Load Diff

14
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fpga_top.v
View File

@ -162,7 +162,7 @@ wire [0:12] sb_1__1__0_chany_bottom_out;
.bottom_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_),
.bottom_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_),
.bottom_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_),
.ccff_head(cbx_1__1__0_ccff_tail),
.ccff_head(grid_io_right_0_ccff_tail),
.bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_),
.bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_),
.bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_),
@ -206,7 +206,7 @@ wire [0:12] sb_1__1__0_chany_bottom_out;
.top_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_),
.top_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_),
.top_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_),
.ccff_head(ccff_head),
.ccff_head(cbx_1__0__0_ccff_tail),
.top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_),
.top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_),
.top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_),
@ -284,7 +284,7 @@ wire [0:12] sb_1__1__0_chany_bottom_out;
.right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_5__pin_inpad_0_),
.right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_6__pin_inpad_0_),
.right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_7__pin_inpad_0_),
.ccff_head(sb_0__1__0_ccff_tail),
.ccff_head(ccff_head),
.chany_top_out(sb_0__0__0_chany_top_out[0:12]),
.chanx_right_out(sb_0__0__0_chanx_right_out[0:12]),
.ccff_tail(sb_0__0__0_ccff_tail));
@ -338,7 +338,7 @@ wire [0:12] sb_1__1__0_chany_bottom_out;
.left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_5__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_6__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_7__pin_inpad_0_),
.ccff_head(grid_io_left_0_ccff_tail),
.ccff_head(sb_0__0__0_ccff_tail),
.chany_top_out(sb_1__0__0_chany_top_out[0:12]),
.chanx_left_out(sb_1__0__0_chanx_left_out[0:12]),
.ccff_tail(sb_1__0__0_ccff_tail));
@ -365,7 +365,7 @@ wire [0:12] sb_1__1__0_chany_bottom_out;
.left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_6__pin_inpad_0_),
.left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_7__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_2_),
.ccff_head(grid_io_right_0_ccff_tail),
.ccff_head(grid_io_left_0_ccff_tail),
.chany_bottom_out(sb_1__1__0_chany_bottom_out[0:12]),
.chanx_left_out(sb_1__1__0_chanx_left_out[0:12]),
.ccff_tail(sb_1__1__0_ccff_tail));
@ -414,7 +414,7 @@ wire [0:12] sb_1__1__0_chany_bottom_out;
.prog_clk(prog_clk),
.chany_bottom_in(sb_0__0__0_chany_top_out[0:12]),
.chany_top_in(sb_0__1__0_chany_bottom_out[0:12]),
.ccff_head(sb_0__0__0_ccff_tail),
.ccff_head(sb_0__1__0_ccff_tail),
.chany_bottom_out(cby_0__1__0_chany_bottom_out[0:12]),
.chany_top_out(cby_0__1__0_chany_top_out[0:12]),
.right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_0__1__0_right_grid_left_width_0_height_0_subtile_0__pin_I_3_),
@ -433,7 +433,7 @@ wire [0:12] sb_1__1__0_chany_bottom_out;
.prog_clk(prog_clk),
.chany_bottom_in(sb_1__0__0_chany_top_out[0:12]),
.chany_top_in(sb_1__1__0_chany_bottom_out[0:12]),
.ccff_head(cbx_1__0__0_ccff_tail),
.ccff_head(cbx_1__1__0_ccff_tail),
.chany_bottom_out(cby_1__1__0_chany_bottom_out[0:12]),
.chany_top_out(cby_1__1__0_chany_top_out[0:12]),
.right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_),

120
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml/cby_0__1_.xml
View File

@ -1,82 +1,82 @@
<rr_cb x="0" y="1" num_sides="4">
<IPIN side="right" index="0" node_id="83" mux_size="6">
<driver_node type="CHANY" side="top" node_id="201" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="202" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="213" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="214" index="13" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="225" index="24" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="226" index="25" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="201" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="202" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="213" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="214" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="225" index="24" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="226" index="25" segment_id="0"/>
</IPIN>
<IPIN side="right" index="1" node_id="84" mux_size="6">
<driver_node type="CHANY" side="top" node_id="201" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="202" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="203" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="204" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="215" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="216" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="201" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="202" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="203" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="204" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="215" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="216" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" node_id="56" mux_size="6">
<driver_node type="CHANY" side="top" node_id="203" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="204" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="205" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="206" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="217" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="218" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="203" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="204" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="205" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="206" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="217" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="218" index="17" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" node_id="57" mux_size="6">
<driver_node type="CHANY" side="top" node_id="205" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="206" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="207" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="208" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="219" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="220" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="205" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="206" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="207" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="208" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="219" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="220" index="19" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" node_id="58" mux_size="6">
<driver_node type="CHANY" side="top" node_id="207" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="208" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="209" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="210" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="221" index="20" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="222" index="21" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="207" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="208" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="209" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="210" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="221" index="20" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="222" index="21" segment_id="0"/>
</IPIN>
<IPIN side="left" index="3" node_id="59" mux_size="6">
<driver_node type="CHANY" side="top" node_id="209" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="210" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="211" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="212" index="11" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="223" index="22" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="224" index="23" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="209" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="210" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="211" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="212" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="223" index="22" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="224" index="23" segment_id="0"/>
</IPIN>
<IPIN side="left" index="4" node_id="60" mux_size="6">
<driver_node type="CHANY" side="top" node_id="211" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="212" index="11" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="213" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="214" index="13" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="225" index="24" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="226" index="25" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="211" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="212" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="213" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="214" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="225" index="24" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="226" index="25" segment_id="0"/>
</IPIN>
<IPIN side="left" index="5" node_id="61" mux_size="6">
<driver_node type="CHANY" side="top" node_id="201" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="202" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="213" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="214" index="13" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="215" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="216" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="201" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="202" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="213" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="214" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="215" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="216" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="6" node_id="62" mux_size="6">
<driver_node type="CHANY" side="top" node_id="203" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="204" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="215" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="216" index="15" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="217" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="218" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="203" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="204" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="215" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="216" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="217" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="218" index="17" segment_id="0"/>
</IPIN>
<IPIN side="left" index="7" node_id="63" mux_size="6">
<driver_node type="CHANY" side="top" node_id="205" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="206" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="217" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="218" index="17" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="219" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="220" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="205" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="206" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="217" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="218" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="219" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="220" index="19" segment_id="0"/>
</IPIN>
</rr_cb>

132
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml/cby_1__1_.xml
View File

@ -1,90 +1,90 @@
<rr_cb x="1" y="1" num_sides="4">
<IPIN side="right" index="0" node_id="109" mux_size="6">
<driver_node type="CHANY" side="top" node_id="227" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="228" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="239" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="240" index="13" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="251" index="24" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="252" index="25" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="227" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="228" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="239" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="240" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="251" index="24" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="252" index="25" segment_id="0"/>
</IPIN>
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120
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__1_.xml
View File

@ -1,82 +1,82 @@
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132
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__1_.xml
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@ -1,90 +1,90 @@
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<driver_node type="CHANY" side="bottom" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="15" segment_id="0"/>
</IPIN>
<IPIN side="right" index="2" mux_size="6">
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="17" segment_id="0"/>
</IPIN>
<IPIN side="right" index="3" mux_size="6">
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="19" segment_id="0"/>
</IPIN>
<IPIN side="right" index="4" mux_size="6">
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" index="20" segment_id="0"/>
<driver_node type="CHANY" side="top" index="21" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="20" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="21" segment_id="0"/>
</IPIN>
<IPIN side="right" index="5" mux_size="6">
<driver_node type="CHANY" side="top" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
<driver_node type="CHANY" side="top" index="22" segment_id="0"/>
<driver_node type="CHANY" side="top" index="23" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="22" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="23" segment_id="0"/>
</IPIN>
<IPIN side="right" index="6" mux_size="6">
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
<driver_node type="CHANY" side="top" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" index="13" segment_id="0"/>
<driver_node type="CHANY" side="top" index="24" segment_id="0"/>
<driver_node type="CHANY" side="top" index="25" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="24" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="25" segment_id="0"/>
</IPIN>
<IPIN side="right" index="7" mux_size="6">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" index="13" segment_id="0"/>
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" mux_size="6">
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
<driver_node type="CHANY" side="top" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="17" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" mux_size="6">
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" index="17" segment_id="0"/>
<driver_node type="CHANY" side="top" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="19" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" mux_size="6">
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" index="19" segment_id="0"/>
<driver_node type="CHANY" side="top" index="20" segment_id="0"/>
<driver_node type="CHANY" side="top" index="21" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="20" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="21" segment_id="0"/>
</IPIN>
</rr_cb>

108
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc
View File

@ -153,48 +153,44 @@ set_disable_timing gfpga_pad_GPIO_PAD[127]
set_disable_timing set[0]
set_disable_timing reset[0]
set_disable_timing prog_clk[0]
set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q
@ -207,12 +203,16 @@ set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logica
set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
@ -221,6 +221,14 @@ set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
@ -231,6 +239,8 @@ set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q
@ -247,6 +257,14 @@ set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/mem_fle_
set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/mem_fle_*_in_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q
@ -255,32 +273,16 @@ set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
@ -293,8 +295,6 @@ set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
##################################################
# Disable timing for Connection block cbx_1__0_
##################################################

6708
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/ccff_timing.sdc
View File

File diff suppressed because it is too large Load Diff

108
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/disable_configurable_memory_outputs.sdc
View File

@ -6,48 +6,44 @@
# Organization: University of Utah
#############################################
set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q
@ -60,12 +56,16 @@ set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logica
set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
@ -74,6 +74,14 @@ set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
@ -84,6 +92,8 @@ set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q
@ -100,6 +110,14 @@ set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/mem_fle_
set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/mem_fle_*_in_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q
@ -108,32 +126,16 @@ set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
@ -146,5 +148,3 @@ set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN

284
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_bitstream.bit
View File

@ -221,6 +221,8 @@
0
0
0
1
1
0
0
0
@ -621,6 +623,9 @@
0
0
0
1
1
1
0
0
0
@ -804,7 +809,6 @@
0
0
0
1
0
0
0
@ -828,8 +832,6 @@
0
0
0
1
1
0
0
0
@ -840,9 +842,7 @@
0
0
0
1
0
1
0
0
0
@ -864,7 +864,6 @@
0
0
0
1
0
0
0
@ -877,9 +876,6 @@
0
0
0
1
1
1
0
0
0
@ -898,6 +894,8 @@
0
0
0
1
1
0
0
0
@ -910,6 +908,7 @@
0
0
0
1
0
0
0
@ -922,13 +921,15 @@
0
0
0
1
1
1
0
0
0
0
0
0
1
0
0
0
@ -939,13 +940,9 @@
0
0
0
1
0
1
0
1
0
1
0
0
0
@ -975,6 +972,7 @@
0
0
0
1
0
0
0
@ -985,9 +983,13 @@
0
0
0
1
0
1
0
1
0
1
0
0
0
@ -1057,8 +1059,6 @@
0
0
0
1
1
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0
0
@ -1075,6 +1075,7 @@
0
0
0
1
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0
@ -1098,6 +1099,8 @@
0
0
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1
1
0
0
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@ -1108,7 +1111,9 @@
0
0
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1
0
1
0
0
0
@ -1234,8 +1239,6 @@
0
0
0
1
1
0
0
0
@ -1263,9 +1266,7 @@
0
0
0
1
0
1
0
0
0
@ -1277,6 +1278,8 @@
0
0
0
1
1
0
0
0
@ -1723,9 +1726,6 @@
0
0
0
1
1
1
0
0
0
@ -1979,6 +1979,14 @@
0
0
0
1
1
1
0
0
0
0
0
0
0
0
@ -2360,7 +2368,7 @@
0
0
1
1
0
1
0
0
@ -2562,7 +2570,6 @@
0
0
0
1
0
0
0
@ -2593,6 +2600,15 @@
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
@ -2817,7 +2833,6 @@
0
0
0
1
1
0
0
@ -3054,6 +3069,9 @@
0
0
0
1
1
1
0
0
0
@ -3552,6 +3570,10 @@
0
0
0
0
0
0
0
1
1
1
@ -3779,7 +3801,78 @@
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
@ -3819,24 +3912,6 @@
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
@ -3858,12 +3933,22 @@
0
0
0
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
@ -3899,18 +3984,8 @@
0
0
0
1
1
0
0
1
1
1
1
1
1
1
1
0
0
0
@ -3944,6 +4019,14 @@
0
0
0
1
1
1
1
1
1
1
1
0
0
0
@ -3987,14 +4070,7 @@
0
0
0
1
1
1
1
1
1
0
1
0
0
0
@ -4024,6 +4100,11 @@
1
1
1
1
1
1
1
1
0
0
0
@ -4071,21 +4152,6 @@
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
@ -4133,8 +4199,6 @@
0
0
0
1
1
0
0
0
@ -4147,67 +4211,3 @@
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

8124
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_bitstream.xml
View File

File diff suppressed because it is too large Load Diff

104
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fpga_top.v
View File

@ -807,7 +807,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.bottom_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__4__0_top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_),
.bottom_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__4__0_top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_),
.bottom_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__4__0_top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_),
.ccff_head(cbx_1__4__0_ccff_tail),
.ccff_head(grid_io_top_1_ccff_tail),
.bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_),
.bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_),
.bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_),
@ -829,7 +829,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.bottom_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__4__1_top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_),
.bottom_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__4__1_top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_),
.bottom_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__4__1_top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_),
.ccff_head(cbx_1__4__1_ccff_tail),
.ccff_head(grid_io_top_2_ccff_tail),
.bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_1_bottom_width_0_height_0_subtile_0__pin_inpad_0_),
.bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_1_bottom_width_0_height_0_subtile_1__pin_inpad_0_),
.bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_1_bottom_width_0_height_0_subtile_2__pin_inpad_0_),
@ -851,7 +851,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.bottom_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__4__2_top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_),
.bottom_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__4__2_top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_),
.bottom_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__4__2_top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_),
.ccff_head(cbx_1__4__2_ccff_tail),
.ccff_head(grid_io_top_3_ccff_tail),
.bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_2_bottom_width_0_height_0_subtile_0__pin_inpad_0_),
.bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_2_bottom_width_0_height_0_subtile_1__pin_inpad_0_),
.bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_2_bottom_width_0_height_0_subtile_2__pin_inpad_0_),
@ -873,7 +873,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.bottom_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__4__3_top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_),
.bottom_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__4__3_top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_),
.bottom_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__4__3_top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_),
.ccff_head(cbx_1__4__3_ccff_tail),
.ccff_head(grid_io_right_0_ccff_tail),
.bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_3_bottom_width_0_height_0_subtile_0__pin_inpad_0_),
.bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_3_bottom_width_0_height_0_subtile_1__pin_inpad_0_),
.bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_3_bottom_width_0_height_0_subtile_2__pin_inpad_0_),
@ -983,7 +983,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.top_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_),
.top_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_),
.top_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_),
.ccff_head(grid_io_bottom_1_ccff_tail),
.ccff_head(cbx_1__0__3_ccff_tail),
.top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_),
.top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_),
.top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_),
@ -1005,7 +1005,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.top_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_),
.top_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_),
.top_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_),
.ccff_head(grid_io_bottom_2_ccff_tail),
.ccff_head(cbx_1__0__2_ccff_tail),
.top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_0__pin_inpad_0_),
.top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_1__pin_inpad_0_),
.top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_2__pin_inpad_0_),
@ -1027,7 +1027,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.top_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_),
.top_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_),
.top_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_),
.ccff_head(grid_io_bottom_3_ccff_tail),
.ccff_head(cbx_1__0__1_ccff_tail),
.top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_2_top_width_0_height_0_subtile_0__pin_inpad_0_),
.top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_2_top_width_0_height_0_subtile_1__pin_inpad_0_),
.top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_2_top_width_0_height_0_subtile_2__pin_inpad_0_),
@ -1049,7 +1049,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.top_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_),
.top_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_),
.top_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_),
.ccff_head(ccff_head),
.ccff_head(cbx_1__0__0_ccff_tail),
.top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_3_top_width_0_height_0_subtile_0__pin_inpad_0_),
.top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_3_top_width_0_height_0_subtile_1__pin_inpad_0_),
.top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_3_top_width_0_height_0_subtile_2__pin_inpad_0_),
@ -1538,7 +1538,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_3_top_width_0_height_0_subtile_5__pin_inpad_0_),
.right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_3_top_width_0_height_0_subtile_6__pin_inpad_0_),
.right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_3_top_width_0_height_0_subtile_7__pin_inpad_0_),
.ccff_head(grid_io_left_1_ccff_tail),
.ccff_head(ccff_head),
.chany_top_out(sb_0__0__0_chany_top_out[0:9]),
.chanx_right_out(sb_0__0__0_chanx_right_out[0:9]),
.ccff_tail(sb_0__0__0_ccff_tail));
@ -1568,7 +1568,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_5__pin_inpad_0_),
.bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_6__pin_inpad_0_),
.bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_7__pin_inpad_0_),
.ccff_head(grid_io_left_2_ccff_tail),
.ccff_head(grid_io_left_1_ccff_tail),
.chany_top_out(sb_0__1__0_chany_top_out[0:9]),
.chanx_right_out(sb_0__1__0_chanx_right_out[0:9]),
.chany_bottom_out(sb_0__1__0_chany_bottom_out[0:9]),
@ -1599,7 +1599,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_left_1_right_width_0_height_0_subtile_5__pin_inpad_0_),
.bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_left_1_right_width_0_height_0_subtile_6__pin_inpad_0_),
.bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_left_1_right_width_0_height_0_subtile_7__pin_inpad_0_),
.ccff_head(grid_io_left_3_ccff_tail),
.ccff_head(grid_io_left_2_ccff_tail),
.chany_top_out(sb_0__1__1_chany_top_out[0:9]),
.chanx_right_out(sb_0__1__1_chanx_right_out[0:9]),
.chany_bottom_out(sb_0__1__1_chany_bottom_out[0:9]),
@ -1630,7 +1630,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_left_2_right_width_0_height_0_subtile_5__pin_inpad_0_),
.bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_left_2_right_width_0_height_0_subtile_6__pin_inpad_0_),
.bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_left_2_right_width_0_height_0_subtile_7__pin_inpad_0_),
.ccff_head(sb_0__4__0_ccff_tail),
.ccff_head(grid_io_left_3_ccff_tail),
.chany_top_out(sb_0__1__2_chany_top_out[0:9]),
.chanx_right_out(sb_0__1__2_chanx_right_out[0:9]),
.chany_bottom_out(sb_0__1__2_chany_bottom_out[0:9]),
@ -1688,7 +1688,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_3_top_width_0_height_0_subtile_5__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_3_top_width_0_height_0_subtile_6__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_3_top_width_0_height_0_subtile_7__pin_inpad_0_),
.ccff_head(grid_io_left_0_ccff_tail),
.ccff_head(sb_0__0__0_ccff_tail),
.chany_top_out(sb_1__0__0_chany_top_out[0:9]),
.chanx_right_out(sb_1__0__0_chanx_right_out[0:9]),
.chanx_left_out(sb_1__0__0_chanx_left_out[0:9]),
@ -1719,7 +1719,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_2_top_width_0_height_0_subtile_5__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_2_top_width_0_height_0_subtile_6__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_2_top_width_0_height_0_subtile_7__pin_inpad_0_),
.ccff_head(grid_clb_0_ccff_tail),
.ccff_head(grid_io_bottom_3_ccff_tail),
.chany_top_out(sb_1__0__1_chany_top_out[0:9]),
.chanx_right_out(sb_1__0__1_chanx_right_out[0:9]),
.chanx_left_out(sb_1__0__1_chanx_left_out[0:9]),
@ -1750,7 +1750,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_5__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_6__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_7__pin_inpad_0_),
.ccff_head(grid_clb_4_ccff_tail),
.ccff_head(grid_io_bottom_2_ccff_tail),
.chany_top_out(sb_1__0__2_chany_top_out[0:9]),
.chanx_right_out(sb_1__0__2_chanx_right_out[0:9]),
.chanx_left_out(sb_1__0__2_chanx_left_out[0:9]),
@ -1770,7 +1770,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.chanx_left_in(cbx_1__1__0_chanx_right_out[0:9]),
.left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_1_bottom_width_0_height_0_subtile_0__pin_O_0_),
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_2_),
.ccff_head(grid_clb_5_ccff_tail),
.ccff_head(grid_io_left_0_ccff_tail),
.chany_top_out(sb_1__1__0_chany_top_out[0:9]),
.chanx_right_out(sb_1__1__0_chanx_right_out[0:9]),
.chany_bottom_out(sb_1__1__0_chany_bottom_out[0:9]),
@ -1791,7 +1791,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.chanx_left_in(cbx_1__1__1_chanx_right_out[0:9]),
.left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_2_bottom_width_0_height_0_subtile_0__pin_O_0_),
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_2_),
.ccff_head(grid_clb_1_ccff_tail),
.ccff_head(grid_clb_5_ccff_tail),
.chany_top_out(sb_1__1__1_chany_top_out[0:9]),
.chanx_right_out(sb_1__1__1_chanx_right_out[0:9]),
.chany_bottom_out(sb_1__1__1_chany_bottom_out[0:9]),
@ -1812,7 +1812,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.chanx_left_in(cbx_1__1__2_chanx_right_out[0:9]),
.left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_3_bottom_width_0_height_0_subtile_0__pin_O_0_),
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_2_),
.ccff_head(grid_clb_7_ccff_tail),
.ccff_head(grid_clb_1_ccff_tail),
.chany_top_out(sb_1__1__2_chany_top_out[0:9]),
.chanx_right_out(sb_1__1__2_chanx_right_out[0:9]),
.chany_bottom_out(sb_1__1__2_chany_bottom_out[0:9]),
@ -1833,7 +1833,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.chanx_left_in(cbx_1__1__3_chanx_right_out[0:9]),
.left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_5_bottom_width_0_height_0_subtile_0__pin_O_0_),
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_2_),
.ccff_head(grid_clb_9_ccff_tail),
.ccff_head(grid_clb_0_ccff_tail),
.chany_top_out(sb_1__1__3_chany_top_out[0:9]),
.chanx_right_out(sb_1__1__3_chanx_right_out[0:9]),
.chany_bottom_out(sb_1__1__3_chany_bottom_out[0:9]),
@ -1854,7 +1854,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.chanx_left_in(cbx_1__1__4_chanx_right_out[0:9]),
.left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_6_bottom_width_0_height_0_subtile_0__pin_O_0_),
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_2_),
.ccff_head(grid_clb_2_ccff_tail),
.ccff_head(grid_clb_9_ccff_tail),
.chany_top_out(sb_1__1__4_chany_top_out[0:9]),
.chanx_right_out(sb_1__1__4_chanx_right_out[0:9]),
.chany_bottom_out(sb_1__1__4_chany_bottom_out[0:9]),
@ -1875,7 +1875,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.chanx_left_in(cbx_1__1__5_chanx_right_out[0:9]),
.left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_7_bottom_width_0_height_0_subtile_0__pin_O_0_),
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_2_),
.ccff_head(grid_clb_11_ccff_tail),
.ccff_head(grid_clb_2_ccff_tail),
.chany_top_out(sb_1__1__5_chany_top_out[0:9]),
.chanx_right_out(sb_1__1__5_chanx_right_out[0:9]),
.chany_bottom_out(sb_1__1__5_chany_bottom_out[0:9]),
@ -1896,7 +1896,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.chanx_left_in(cbx_1__1__6_chanx_right_out[0:9]),
.left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_9_bottom_width_0_height_0_subtile_0__pin_O_0_),
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_2_),
.ccff_head(grid_clb_13_ccff_tail),
.ccff_head(grid_clb_4_ccff_tail),
.chany_top_out(sb_1__1__6_chany_top_out[0:9]),
.chanx_right_out(sb_1__1__6_chanx_right_out[0:9]),
.chany_bottom_out(sb_1__1__6_chany_bottom_out[0:9]),
@ -1917,7 +1917,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.chanx_left_in(cbx_1__1__7_chanx_right_out[0:9]),
.left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_10_bottom_width_0_height_0_subtile_0__pin_O_0_),
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_2_),
.ccff_head(grid_clb_6_ccff_tail),
.ccff_head(grid_clb_13_ccff_tail),
.chany_top_out(sb_1__1__7_chany_top_out[0:9]),
.chanx_right_out(sb_1__1__7_chanx_right_out[0:9]),
.chany_bottom_out(sb_1__1__7_chany_bottom_out[0:9]),
@ -1938,7 +1938,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.chanx_left_in(cbx_1__1__8_chanx_right_out[0:9]),
.left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_11_bottom_width_0_height_0_subtile_0__pin_O_0_),
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_2_),
.ccff_head(grid_clb_15_ccff_tail),
.ccff_head(grid_clb_6_ccff_tail),
.chany_top_out(sb_1__1__8_chany_top_out[0:9]),
.chanx_right_out(sb_1__1__8_chanx_right_out[0:9]),
.chany_bottom_out(sb_1__1__8_chany_bottom_out[0:9]),
@ -1970,7 +1970,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_6__pin_inpad_0_),
.left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_7__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_2_),
.ccff_head(grid_io_top_1_ccff_tail),
.ccff_head(grid_clb_7_ccff_tail),
.chanx_right_out(sb_1__4__0_chanx_right_out[0:9]),
.chany_bottom_out(sb_1__4__0_chany_bottom_out[0:9]),
.chanx_left_out(sb_1__4__0_chanx_left_out[0:9]),
@ -2001,7 +2001,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_top_1_bottom_width_0_height_0_subtile_6__pin_inpad_0_),
.left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_top_1_bottom_width_0_height_0_subtile_7__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_2_),
.ccff_head(grid_io_top_2_ccff_tail),
.ccff_head(grid_clb_11_ccff_tail),
.chanx_right_out(sb_1__4__1_chanx_right_out[0:9]),
.chany_bottom_out(sb_1__4__1_chany_bottom_out[0:9]),
.chanx_left_out(sb_1__4__1_chanx_left_out[0:9]),
@ -2032,7 +2032,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_top_2_bottom_width_0_height_0_subtile_6__pin_inpad_0_),
.left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_top_2_bottom_width_0_height_0_subtile_7__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_2_),
.ccff_head(grid_io_top_3_ccff_tail),
.ccff_head(grid_clb_15_ccff_tail),
.chanx_right_out(sb_1__4__2_chanx_right_out[0:9]),
.chany_bottom_out(sb_1__4__2_chany_bottom_out[0:9]),
.chanx_left_out(sb_1__4__2_chanx_left_out[0:9]),
@ -2060,7 +2060,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_5__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_6__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_7__pin_inpad_0_),
.ccff_head(grid_clb_8_ccff_tail),
.ccff_head(grid_io_bottom_1_ccff_tail),
.chany_top_out(sb_4__0__0_chany_top_out[0:9]),
.chanx_left_out(sb_4__0__0_chanx_left_out[0:9]),
.ccff_tail(sb_4__0__0_ccff_tail));
@ -2090,7 +2090,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.chanx_left_in(cbx_1__1__9_chanx_right_out[0:9]),
.left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_13_bottom_width_0_height_0_subtile_0__pin_O_0_),
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_2_),
.ccff_head(grid_clb_12_ccff_tail),
.ccff_head(grid_clb_8_ccff_tail),
.chany_top_out(sb_4__1__0_chany_top_out[0:9]),
.chany_bottom_out(sb_4__1__0_chany_bottom_out[0:9]),
.chanx_left_out(sb_4__1__0_chanx_left_out[0:9]),
@ -2121,7 +2121,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.chanx_left_in(cbx_1__1__10_chanx_right_out[0:9]),
.left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_14_bottom_width_0_height_0_subtile_0__pin_O_0_),
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_2_),
.ccff_head(grid_clb_10_ccff_tail),
.ccff_head(grid_clb_12_ccff_tail),
.chany_top_out(sb_4__1__1_chany_top_out[0:9]),
.chany_bottom_out(sb_4__1__1_chany_bottom_out[0:9]),
.chanx_left_out(sb_4__1__1_chanx_left_out[0:9]),
@ -2152,7 +2152,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.chanx_left_in(cbx_1__1__11_chanx_right_out[0:9]),
.left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_15_bottom_width_0_height_0_subtile_0__pin_O_0_),
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_2_),
.ccff_head(grid_clb_14_ccff_tail),
.ccff_head(grid_clb_10_ccff_tail),
.chany_top_out(sb_4__1__2_chany_top_out[0:9]),
.chany_bottom_out(sb_4__1__2_chany_bottom_out[0:9]),
.chanx_left_out(sb_4__1__2_chanx_left_out[0:9]),
@ -2180,7 +2180,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_top_3_bottom_width_0_height_0_subtile_6__pin_inpad_0_),
.left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_top_3_bottom_width_0_height_0_subtile_7__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_2_),
.ccff_head(grid_io_right_0_ccff_tail),
.ccff_head(grid_clb_14_ccff_tail),
.chany_bottom_out(sb_4__4__0_chany_bottom_out[0:9]),
.chanx_left_out(sb_4__4__0_chanx_left_out[0:9]),
.ccff_tail(sb_4__4__0_ccff_tail));
@ -2529,7 +2529,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.prog_clk(prog_clk),
.chany_bottom_in(sb_0__0__0_chany_top_out[0:9]),
.chany_top_in(sb_0__1__0_chany_bottom_out[0:9]),
.ccff_head(sb_0__0__0_ccff_tail),
.ccff_head(sb_0__1__0_ccff_tail),
.chany_bottom_out(cby_0__1__0_chany_bottom_out[0:9]),
.chany_top_out(cby_0__1__0_chany_top_out[0:9]),
.right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_0__1__0_right_grid_left_width_0_height_0_subtile_0__pin_I_3_),
@ -2548,7 +2548,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.prog_clk(prog_clk),
.chany_bottom_in(sb_0__1__0_chany_top_out[0:9]),
.chany_top_in(sb_0__1__1_chany_bottom_out[0:9]),
.ccff_head(sb_0__1__0_ccff_tail),
.ccff_head(sb_0__1__1_ccff_tail),
.chany_bottom_out(cby_0__1__1_chany_bottom_out[0:9]),
.chany_top_out(cby_0__1__1_chany_top_out[0:9]),
.right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_0__1__1_right_grid_left_width_0_height_0_subtile_0__pin_I_3_),
@ -2567,7 +2567,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.prog_clk(prog_clk),
.chany_bottom_in(sb_0__1__1_chany_top_out[0:9]),
.chany_top_in(sb_0__1__2_chany_bottom_out[0:9]),
.ccff_head(sb_0__1__1_ccff_tail),
.ccff_head(sb_0__1__2_ccff_tail),
.chany_bottom_out(cby_0__1__2_chany_bottom_out[0:9]),
.chany_top_out(cby_0__1__2_chany_top_out[0:9]),
.right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_0__1__2_right_grid_left_width_0_height_0_subtile_0__pin_I_3_),
@ -2586,7 +2586,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.prog_clk(prog_clk),
.chany_bottom_in(sb_0__1__2_chany_top_out[0:9]),
.chany_top_in(sb_0__4__0_chany_bottom_out[0:9]),
.ccff_head(sb_0__1__2_ccff_tail),
.ccff_head(sb_0__4__0_ccff_tail),
.chany_bottom_out(cby_0__1__3_chany_bottom_out[0:9]),
.chany_top_out(cby_0__1__3_chany_top_out[0:9]),
.right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_0__1__3_right_grid_left_width_0_height_0_subtile_0__pin_I_3_),
@ -2605,7 +2605,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.prog_clk(prog_clk),
.chany_bottom_in(sb_1__0__0_chany_top_out[0:9]),
.chany_top_in(sb_1__1__0_chany_bottom_out[0:9]),
.ccff_head(cbx_1__0__0_ccff_tail),
.ccff_head(cbx_1__1__0_ccff_tail),
.chany_bottom_out(cby_1__1__0_chany_bottom_out[0:9]),
.chany_top_out(cby_1__1__0_chany_top_out[0:9]),
.right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_0__pin_I_3_),
@ -2619,7 +2619,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.prog_clk(prog_clk),
.chany_bottom_in(sb_1__1__0_chany_top_out[0:9]),
.chany_top_in(sb_1__1__1_chany_bottom_out[0:9]),
.ccff_head(cbx_1__1__0_ccff_tail),
.ccff_head(cbx_1__1__1_ccff_tail),
.chany_bottom_out(cby_1__1__1_chany_bottom_out[0:9]),
.chany_top_out(cby_1__1__1_chany_top_out[0:9]),
.right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_1__1__1_right_grid_left_width_0_height_0_subtile_0__pin_I_3_),
@ -2633,7 +2633,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.prog_clk(prog_clk),
.chany_bottom_in(sb_1__1__1_chany_top_out[0:9]),
.chany_top_in(sb_1__1__2_chany_bottom_out[0:9]),
.ccff_head(cbx_1__1__1_ccff_tail),
.ccff_head(cbx_1__1__2_ccff_tail),
.chany_bottom_out(cby_1__1__2_chany_bottom_out[0:9]),
.chany_top_out(cby_1__1__2_chany_top_out[0:9]),
.right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_1__1__2_right_grid_left_width_0_height_0_subtile_0__pin_I_3_),
@ -2647,7 +2647,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.prog_clk(prog_clk),
.chany_bottom_in(sb_1__1__2_chany_top_out[0:9]),
.chany_top_in(sb_1__4__0_chany_bottom_out[0:9]),
.ccff_head(cbx_1__1__2_ccff_tail),
.ccff_head(cbx_1__4__0_ccff_tail),
.chany_bottom_out(cby_1__1__3_chany_bottom_out[0:9]),
.chany_top_out(cby_1__1__3_chany_top_out[0:9]),
.right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_1__1__3_right_grid_left_width_0_height_0_subtile_0__pin_I_3_),
@ -2661,7 +2661,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.prog_clk(prog_clk),
.chany_bottom_in(sb_1__0__1_chany_top_out[0:9]),
.chany_top_in(sb_1__1__3_chany_bottom_out[0:9]),
.ccff_head(cbx_1__0__1_ccff_tail),
.ccff_head(cbx_1__1__3_ccff_tail),
.chany_bottom_out(cby_1__1__4_chany_bottom_out[0:9]),
.chany_top_out(cby_1__1__4_chany_top_out[0:9]),
.right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_1__1__4_right_grid_left_width_0_height_0_subtile_0__pin_I_3_),
@ -2675,7 +2675,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.prog_clk(prog_clk),
.chany_bottom_in(sb_1__1__3_chany_top_out[0:9]),
.chany_top_in(sb_1__1__4_chany_bottom_out[0:9]),
.ccff_head(cbx_1__1__3_ccff_tail),
.ccff_head(cbx_1__1__4_ccff_tail),
.chany_bottom_out(cby_1__1__5_chany_bottom_out[0:9]),
.chany_top_out(cby_1__1__5_chany_top_out[0:9]),
.right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_1__1__5_right_grid_left_width_0_height_0_subtile_0__pin_I_3_),
@ -2689,7 +2689,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.prog_clk(prog_clk),
.chany_bottom_in(sb_1__1__4_chany_top_out[0:9]),
.chany_top_in(sb_1__1__5_chany_bottom_out[0:9]),
.ccff_head(cbx_1__1__4_ccff_tail),
.ccff_head(cbx_1__1__5_ccff_tail),
.chany_bottom_out(cby_1__1__6_chany_bottom_out[0:9]),
.chany_top_out(cby_1__1__6_chany_top_out[0:9]),
.right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_1__1__6_right_grid_left_width_0_height_0_subtile_0__pin_I_3_),
@ -2703,7 +2703,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.prog_clk(prog_clk),
.chany_bottom_in(sb_1__1__5_chany_top_out[0:9]),
.chany_top_in(sb_1__4__1_chany_bottom_out[0:9]),
.ccff_head(cbx_1__1__5_ccff_tail),
.ccff_head(cbx_1__4__1_ccff_tail),
.chany_bottom_out(cby_1__1__7_chany_bottom_out[0:9]),
.chany_top_out(cby_1__1__7_chany_top_out[0:9]),
.right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_1__1__7_right_grid_left_width_0_height_0_subtile_0__pin_I_3_),
@ -2717,7 +2717,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.prog_clk(prog_clk),
.chany_bottom_in(sb_1__0__2_chany_top_out[0:9]),
.chany_top_in(sb_1__1__6_chany_bottom_out[0:9]),
.ccff_head(cbx_1__0__2_ccff_tail),
.ccff_head(cbx_1__1__6_ccff_tail),
.chany_bottom_out(cby_1__1__8_chany_bottom_out[0:9]),
.chany_top_out(cby_1__1__8_chany_top_out[0:9]),
.right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_1__1__8_right_grid_left_width_0_height_0_subtile_0__pin_I_3_),
@ -2731,7 +2731,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.prog_clk(prog_clk),
.chany_bottom_in(sb_1__1__6_chany_top_out[0:9]),
.chany_top_in(sb_1__1__7_chany_bottom_out[0:9]),
.ccff_head(cbx_1__1__6_ccff_tail),
.ccff_head(cbx_1__1__7_ccff_tail),
.chany_bottom_out(cby_1__1__9_chany_bottom_out[0:9]),
.chany_top_out(cby_1__1__9_chany_top_out[0:9]),
.right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_1__1__9_right_grid_left_width_0_height_0_subtile_0__pin_I_3_),
@ -2745,7 +2745,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.prog_clk(prog_clk),
.chany_bottom_in(sb_1__1__7_chany_top_out[0:9]),
.chany_top_in(sb_1__1__8_chany_bottom_out[0:9]),
.ccff_head(cbx_1__1__7_ccff_tail),
.ccff_head(cbx_1__1__8_ccff_tail),
.chany_bottom_out(cby_1__1__10_chany_bottom_out[0:9]),
.chany_top_out(cby_1__1__10_chany_top_out[0:9]),
.right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_1__1__10_right_grid_left_width_0_height_0_subtile_0__pin_I_3_),
@ -2759,7 +2759,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.prog_clk(prog_clk),
.chany_bottom_in(sb_1__1__8_chany_top_out[0:9]),
.chany_top_in(sb_1__4__2_chany_bottom_out[0:9]),
.ccff_head(cbx_1__1__8_ccff_tail),
.ccff_head(cbx_1__4__2_ccff_tail),
.chany_bottom_out(cby_1__1__11_chany_bottom_out[0:9]),
.chany_top_out(cby_1__1__11_chany_top_out[0:9]),
.right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_1__1__11_right_grid_left_width_0_height_0_subtile_0__pin_I_3_),
@ -2773,7 +2773,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.prog_clk(prog_clk),
.chany_bottom_in(sb_4__0__0_chany_top_out[0:9]),
.chany_top_in(sb_4__1__0_chany_bottom_out[0:9]),
.ccff_head(cbx_1__0__3_ccff_tail),
.ccff_head(cbx_1__1__9_ccff_tail),
.chany_bottom_out(cby_4__1__0_chany_bottom_out[0:9]),
.chany_top_out(cby_4__1__0_chany_top_out[0:9]),
.right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_4__1__0_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_),
@ -2793,7 +2793,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.prog_clk(prog_clk),
.chany_bottom_in(sb_4__1__0_chany_top_out[0:9]),
.chany_top_in(sb_4__1__1_chany_bottom_out[0:9]),
.ccff_head(cbx_1__1__9_ccff_tail),
.ccff_head(cbx_1__1__10_ccff_tail),
.chany_bottom_out(cby_4__1__1_chany_bottom_out[0:9]),
.chany_top_out(cby_4__1__1_chany_top_out[0:9]),
.right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_4__1__1_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_),
@ -2813,7 +2813,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.prog_clk(prog_clk),
.chany_bottom_in(sb_4__1__1_chany_top_out[0:9]),
.chany_top_in(sb_4__1__2_chany_bottom_out[0:9]),
.ccff_head(cbx_1__1__10_ccff_tail),
.ccff_head(cbx_1__1__11_ccff_tail),
.chany_bottom_out(cby_4__1__2_chany_bottom_out[0:9]),
.chany_top_out(cby_4__1__2_chany_top_out[0:9]),
.right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_4__1__2_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_),
@ -2833,7 +2833,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.prog_clk(prog_clk),
.chany_bottom_in(sb_4__1__2_chany_top_out[0:9]),
.chany_top_in(sb_4__4__0_chany_bottom_out[0:9]),
.ccff_head(cbx_1__1__11_ccff_tail),
.ccff_head(cbx_1__4__3_ccff_tail),
.chany_bottom_out(cby_4__1__3_chany_bottom_out[0:9]),
.chany_top_out(cby_4__1__3_chany_top_out[0:9]),
.right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_4__1__3_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_),

76
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_0__1_.xml
View File

@ -1,60 +1,60 @@
<rr_cb x="0" y="1" num_sides="4">
<IPIN side="right" index="0" node_id="179" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1038" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1039" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1048" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1049" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1038" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1039" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1048" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1049" index="11" segment_id="0"/>
</IPIN>
<IPIN side="right" index="1" node_id="180" mux_size="2">
<driver_node type="CHANY" side="top" node_id="1040" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1041" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1040" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1041" index="3" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" node_id="152" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1042" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1043" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1052" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1053" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1042" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1043" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1052" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1053" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" node_id="153" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1044" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1045" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1054" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1055" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1044" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1045" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1054" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1055" index="17" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" node_id="154" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1046" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1047" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1056" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1057" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1046" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1047" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1056" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1057" index="19" segment_id="0"/>
</IPIN>
<IPIN side="left" index="3" node_id="155" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1038" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1039" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1048" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1049" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1038" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1039" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1048" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1049" index="11" segment_id="0"/>
</IPIN>
<IPIN side="left" index="4" node_id="156" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1040" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1041" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1050" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1051" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1040" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1041" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1050" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1051" index="13" segment_id="0"/>
</IPIN>
<IPIN side="left" index="5" node_id="157" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1042" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1043" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1052" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1053" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1042" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1043" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1052" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1053" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="6" node_id="158" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1044" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1045" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1054" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1055" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1044" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1045" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1054" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1055" index="17" segment_id="0"/>
</IPIN>
<IPIN side="left" index="7" node_id="159" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1046" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1047" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1056" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1057" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1046" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1047" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1056" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1057" index="19" segment_id="0"/>
</IPIN>
</rr_cb>

76
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_0__2_.xml
View File

@ -1,60 +1,60 @@
<rr_cb x="0" y="2" num_sides="4">
<IPIN side="right" index="0" node_id="327" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1058" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1041" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1046" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1051" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1058" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1041" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1046" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1051" index="11" segment_id="0"/>
</IPIN>
<IPIN side="right" index="1" node_id="328" mux_size="2">
<driver_node type="CHANY" side="top" node_id="1038" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1043" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1038" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1043" index="3" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" node_id="300" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1040" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1045" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1050" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1061" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1040" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1045" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1050" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1061" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" node_id="301" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1042" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1059" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1062" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1057" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1042" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1059" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1062" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1057" index="17" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" node_id="302" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1060" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1049" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1054" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1063" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1060" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1049" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1054" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1063" index="19" segment_id="0"/>
</IPIN>
<IPIN side="left" index="3" node_id="303" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1058" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1041" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1046" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1051" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1058" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1041" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1046" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1051" index="11" segment_id="0"/>
</IPIN>
<IPIN side="left" index="4" node_id="304" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1038" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1043" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1048" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1053" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1038" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1043" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1048" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1053" index="13" segment_id="0"/>
</IPIN>
<IPIN side="left" index="5" node_id="305" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1040" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1045" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1050" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1061" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1040" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1045" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1050" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1061" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="6" node_id="306" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1042" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1059" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1062" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1057" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1042" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1059" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1062" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1057" index="17" segment_id="0"/>
</IPIN>
<IPIN side="left" index="7" node_id="307" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1060" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1049" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1054" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1063" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1060" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1049" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1054" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1063" index="19" segment_id="0"/>
</IPIN>
</rr_cb>

76
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_0__3_.xml
View File

@ -1,60 +1,60 @@
<rr_cb x="0" y="3" num_sides="4">
<IPIN side="right" index="0" node_id="475" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1064" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1043" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1060" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1053" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1064" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1043" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1060" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1053" index="11" segment_id="0"/>
</IPIN>
<IPIN side="right" index="1" node_id="476" mux_size="2">
<driver_node type="CHANY" side="top" node_id="1058" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1045" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1058" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1045" index="3" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" node_id="448" mux_size="4">
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</rr_cb>

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@ -1,60 +1,60 @@
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openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_1__1_.xml
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@ -1,26 +1,26 @@
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openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_1__2_.xml
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@ -1,26 +1,26 @@
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openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_1__3_.xml
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@ -1,26 +1,26 @@
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</IPIN>
</rr_cb>

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<rr_cb x="1" y="4" num_sides="4">
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</IPIN>
</rr_cb>

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<rr_cb x="2" y="1" num_sides="4">
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</IPIN>
</rr_cb>

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@ -1,26 +1,26 @@
<rr_cb x="2" y="2" num_sides="4">
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</IPIN>
</rr_cb>

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@ -1,26 +1,26 @@
<rr_cb x="2" y="3" num_sides="4">
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</rr_cb>

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openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_2__4_.xml
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<rr_cb x="2" y="4" num_sides="4">
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</rr_cb>

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@ -1,26 +1,26 @@
<rr_cb x="3" y="1" num_sides="4">
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</rr_cb>

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openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_3__2_.xml
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@ -1,26 +1,26 @@
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</IPIN>
</rr_cb>

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@ -1,26 +1,26 @@
<rr_cb x="3" y="3" num_sides="4">
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</IPIN>
</rr_cb>

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openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_3__4_.xml
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@ -1,26 +1,26 @@
<rr_cb x="3" y="4" num_sides="4">
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</IPIN>
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</IPIN>
</rr_cb>

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@ -1,64 +1,64 @@
<rr_cb x="4" y="1" num_sides="4">
<IPIN side="right" index="0" node_id="268" mux_size="4">
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</IPIN>
</rr_cb>

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@ -1,64 +1,64 @@
<rr_cb x="4" y="2" num_sides="4">
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</IPIN>
</rr_cb>

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@ -1,64 +1,64 @@
<rr_cb x="4" y="3" num_sides="4">
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</rr_cb>

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@ -1,64 +1,64 @@
<rr_cb x="4" y="4" num_sides="4">
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</rr_cb>

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openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__1_.xml
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@ -1,60 +1,60 @@
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</IPIN>
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</IPIN>
<IPIN side="left" index="6" mux_size="4">
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</IPIN>
<IPIN side="left" index="7" mux_size="4">
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</IPIN>
</rr_cb>

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@ -1,60 +1,60 @@
<rr_cb x="0" y="2" num_sides="4">
<IPIN side="right" index="0" mux_size="4">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
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</IPIN>
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</IPIN>
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</IPIN>
<IPIN side="left" index="2" mux_size="4">
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<IPIN side="left" index="6" mux_size="4">
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</IPIN>
<IPIN side="left" index="7" mux_size="4">
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</IPIN>
</rr_cb>

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@ -1,60 +1,60 @@
<rr_cb x="0" y="3" num_sides="4">
<IPIN side="right" index="0" mux_size="4">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
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</IPIN>
<IPIN side="right" index="1" mux_size="2">
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</IPIN>
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</IPIN>
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</IPIN>
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</IPIN>
</rr_cb>

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@ -1,60 +1,60 @@
<rr_cb x="0" y="4" num_sides="4">
<IPIN side="right" index="0" mux_size="4">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
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</IPIN>
<IPIN side="right" index="1" mux_size="2">
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</IPIN>
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</IPIN>
</rr_cb>

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@ -1,26 +1,26 @@
<rr_cb x="1" y="1" num_sides="4">
<IPIN side="right" index="0" mux_size="4">
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<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" mux_size="2">
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="7" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" mux_size="2">
<driver_node type="CHANY" side="top" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="9" segment_id="0"/>
</IPIN>
</rr_cb>

28
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__2_.xml
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@ -1,26 +1,26 @@
<rr_cb x="1" y="2" num_sides="4">
<IPIN side="right" index="0" mux_size="4">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="11" segment_id="0"/>
</IPIN>
<IPIN side="right" index="1" mux_size="2">
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="3" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" mux_size="4">
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" mux_size="2">
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="7" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" mux_size="2">
<driver_node type="CHANY" side="top" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="9" segment_id="0"/>
</IPIN>
</rr_cb>

28
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__3_.xml
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@ -1,26 +1,26 @@
<rr_cb x="1" y="3" num_sides="4">
<IPIN side="right" index="0" mux_size="4">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="11" segment_id="0"/>
</IPIN>
<IPIN side="right" index="1" mux_size="2">
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="3" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" mux_size="4">
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" mux_size="2">
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="7" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" mux_size="2">
<driver_node type="CHANY" side="top" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="9" segment_id="0"/>
</IPIN>
</rr_cb>

28
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__4_.xml
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@ -1,26 +1,26 @@
<rr_cb x="1" y="4" num_sides="4">
<IPIN side="right" index="0" mux_size="4">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="11" segment_id="0"/>
</IPIN>
<IPIN side="right" index="1" mux_size="2">
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="3" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" mux_size="4">
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" mux_size="2">
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="7" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" mux_size="2">
<driver_node type="CHANY" side="top" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="9" segment_id="0"/>
</IPIN>
</rr_cb>

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