From 60f0c087d87d6f11069aa8cfcdf9d5b3d2a89fc8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 3 Jul 2024 16:54:34 -0700 Subject: [PATCH 01/91] [lib] update vtr to latest --- vtr-verilog-to-routing | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index 6a4f0cac3..3095c28d3 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit 6a4f0cac3b180bdb78f53f58c9f3f23912858173 +Subproject commit 3095c28d3c2795e8042710d54f941be76ab1819d From f681c6a903a18f0de6c53be6574441a8b0f7a4d5 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 3 Jul 2024 17:04:06 -0700 Subject: [PATCH 02/91] [core] update API call due to vtr upgrade --- .../src/annotation/append_clock_rr_graph.cpp | 25 ++++++++++++------- 1 file changed, 16 insertions(+), 9 deletions(-) diff --git a/openfpga/src/annotation/append_clock_rr_graph.cpp b/openfpga/src/annotation/append_clock_rr_graph.cpp index d5f325ca6..d05fd136d 100644 --- a/openfpga/src/annotation/append_clock_rr_graph.cpp +++ b/openfpga/src/annotation/append_clock_rr_graph.cpp @@ -45,6 +45,7 @@ static size_t estimate_clock_rr_graph_num_chan_nodes( *******************************************************************/ static size_t estimate_clock_rr_graph_num_nodes(const DeviceGrid& grids, const size_t& layer, + const bool& perimeter_cb, const bool& through_channel, const ClockNetwork& clk_ntwk) { size_t num_nodes = 0; @@ -55,7 +56,7 @@ static size_t estimate_clock_rr_graph_num_nodes(const DeviceGrid& grids, /* Bypass if the routing channel does not exist when through channels are * not allowed */ if ((false == through_channel) && - (false == is_chanx_exist(grids, layer, chanx_coord))) { + (false == is_chanx_exist(grids, layer, chanx_coord, perimeter_cb))) { continue; } /* Estimate the routing tracks required by clock routing only */ @@ -69,7 +70,7 @@ static size_t estimate_clock_rr_graph_num_nodes(const DeviceGrid& grids, /* Bypass if the routing channel does not exist when through channel are * not allowed */ if ((false == through_channel) && - (false == is_chany_exist(grids, layer, chany_coord))) { + (false == is_chany_exist(grids, layer, chany_coord, perimeter_cb))) { continue; } /* Estimate the routing tracks required by clock routing only */ @@ -151,7 +152,9 @@ static void add_rr_graph_block_clock_nodes( static void add_rr_graph_clock_nodes( RRGraphBuilder& rr_graph_builder, RRClockSpatialLookup& clk_rr_lookup, const RRGraphView& rr_graph_view, const DeviceGrid& grids, - const size_t& layer, const bool& through_channel, + const size_t& layer, + const bool& perimeter_cb, + const bool& through_channel, const ClockNetwork& clk_ntwk, const bool& verbose) { /* Pre-allocate memory: Must do otherwise data will be messed up! */ clk_rr_lookup.reserve_nodes(grids.width(), grids.height(), @@ -165,7 +168,7 @@ static void add_rr_graph_clock_nodes( /* Bypass if the routing channel does not exist when through channels are * not allowed */ if ((false == through_channel) && - (false == is_chanx_exist(grids, layer, chanx_coord))) { + (false == is_chanx_exist(grids, layer, chanx_coord, perimeter_cb))) { continue; } add_rr_graph_block_clock_nodes( @@ -187,7 +190,7 @@ static void add_rr_graph_clock_nodes( /* Bypass if the routing channel does not exist when through channel are * not allowed */ if ((false == through_channel) && - (false == is_chany_exist(grids, layer, chany_coord))) { + (false == is_chany_exist(grids, layer, chany_coord, perimeter_cb))) { continue; } add_rr_graph_block_clock_nodes( @@ -729,7 +732,9 @@ static int add_rr_graph_opin2clk_edges( static void add_rr_graph_clock_edges( RRGraphBuilder& rr_graph_builder, size_t& num_edges_to_create, const RRClockSpatialLookup& clk_rr_lookup, const RRGraphView& rr_graph_view, - const DeviceGrid& grids, const size_t& layer, const bool& through_channel, + const DeviceGrid& grids, const size_t& layer, + const bool& perimeter_cb, + const bool& through_channel, const ClockNetwork& clk_ntwk, const bool& verbose) { /* Add edges which is driven by X-direction clock routing tracks */ for (size_t iy = 0; iy < grids.height() - 1; ++iy) { @@ -738,7 +743,7 @@ static void add_rr_graph_clock_edges( /* Bypass if the routing channel does not exist when through channels are * not allowed */ if ((false == through_channel) && - (false == is_chanx_exist(grids, layer, chanx_coord))) { + (false == is_chanx_exist(grids, layer, chanx_coord, perimeter_cb))) { continue; } add_rr_graph_block_clock_edges(rr_graph_builder, num_edges_to_create, @@ -754,7 +759,7 @@ static void add_rr_graph_clock_edges( /* Bypass if the routing channel does not exist when through channel are * not allowed */ if ((false == through_channel) && - (false == is_chany_exist(grids, layer, chany_coord))) { + (false == is_chany_exist(grids, layer, chany_coord, perimeter_cb))) { continue; } add_rr_graph_block_clock_edges(rr_graph_builder, num_edges_to_create, @@ -793,7 +798,7 @@ int append_clock_rr_graph(DeviceContext& vpr_device_ctx, /* Estimate the number of nodes and pre-allocate */ size_t orig_num_nodes = vpr_device_ctx.rr_graph.num_nodes(); size_t num_clock_nodes = estimate_clock_rr_graph_num_nodes( - vpr_device_ctx.grid, 0, vpr_device_ctx.arch->through_channel, clk_ntwk); + vpr_device_ctx.grid, 0, vpr_device_ctx.arch->perimeter_cb, vpr_device_ctx.arch->through_channel, clk_ntwk); vpr_device_ctx.rr_graph_builder.unlock_storage(); vpr_device_ctx.rr_graph_builder.reserve_nodes(num_clock_nodes + orig_num_nodes); @@ -805,6 +810,7 @@ int append_clock_rr_graph(DeviceContext& vpr_device_ctx, /* Add clock nodes */ add_rr_graph_clock_nodes(vpr_device_ctx.rr_graph_builder, clk_rr_lookup, vpr_device_ctx.rr_graph, vpr_device_ctx.grid, 0, + vpr_device_ctx.arch->perimeter_cb, vpr_device_ctx.arch->through_channel, clk_ntwk, verbose); VTR_LOGV(verbose, @@ -820,6 +826,7 @@ int append_clock_rr_graph(DeviceContext& vpr_device_ctx, vpr_device_ctx.rr_graph_builder, num_clock_edges, static_cast(clk_rr_lookup), vpr_device_ctx.rr_graph, vpr_device_ctx.grid, 0, + vpr_device_ctx.arch->perimeter_cb, vpr_device_ctx.arch->through_channel, clk_ntwk, verbose); VTR_LOGV(verbose, "Added %lu clock edges to routing " From a27325d987f55f6c85e3fe3d3af4737f7be5eb28 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 3 Jul 2024 17:05:27 -0700 Subject: [PATCH 03/91] [core] code format --- .../src/annotation/append_clock_rr_graph.cpp | 27 +++++++++---------- 1 file changed, 12 insertions(+), 15 deletions(-) diff --git a/openfpga/src/annotation/append_clock_rr_graph.cpp b/openfpga/src/annotation/append_clock_rr_graph.cpp index d05fd136d..ffe49e146 100644 --- a/openfpga/src/annotation/append_clock_rr_graph.cpp +++ b/openfpga/src/annotation/append_clock_rr_graph.cpp @@ -152,9 +152,7 @@ static void add_rr_graph_block_clock_nodes( static void add_rr_graph_clock_nodes( RRGraphBuilder& rr_graph_builder, RRClockSpatialLookup& clk_rr_lookup, const RRGraphView& rr_graph_view, const DeviceGrid& grids, - const size_t& layer, - const bool& perimeter_cb, - const bool& through_channel, + const size_t& layer, const bool& perimeter_cb, const bool& through_channel, const ClockNetwork& clk_ntwk, const bool& verbose) { /* Pre-allocate memory: Must do otherwise data will be messed up! */ clk_rr_lookup.reserve_nodes(grids.width(), grids.height(), @@ -732,10 +730,9 @@ static int add_rr_graph_opin2clk_edges( static void add_rr_graph_clock_edges( RRGraphBuilder& rr_graph_builder, size_t& num_edges_to_create, const RRClockSpatialLookup& clk_rr_lookup, const RRGraphView& rr_graph_view, - const DeviceGrid& grids, const size_t& layer, - const bool& perimeter_cb, - const bool& through_channel, - const ClockNetwork& clk_ntwk, const bool& verbose) { + const DeviceGrid& grids, const size_t& layer, const bool& perimeter_cb, + const bool& through_channel, const ClockNetwork& clk_ntwk, + const bool& verbose) { /* Add edges which is driven by X-direction clock routing tracks */ for (size_t iy = 0; iy < grids.height() - 1; ++iy) { for (size_t ix = 1; ix < grids.width() - 1; ++ix) { @@ -798,7 +795,8 @@ int append_clock_rr_graph(DeviceContext& vpr_device_ctx, /* Estimate the number of nodes and pre-allocate */ size_t orig_num_nodes = vpr_device_ctx.rr_graph.num_nodes(); size_t num_clock_nodes = estimate_clock_rr_graph_num_nodes( - vpr_device_ctx.grid, 0, vpr_device_ctx.arch->perimeter_cb, vpr_device_ctx.arch->through_channel, clk_ntwk); + vpr_device_ctx.grid, 0, vpr_device_ctx.arch->perimeter_cb, + vpr_device_ctx.arch->through_channel, clk_ntwk); vpr_device_ctx.rr_graph_builder.unlock_storage(); vpr_device_ctx.rr_graph_builder.reserve_nodes(num_clock_nodes + orig_num_nodes); @@ -808,11 +806,10 @@ int append_clock_rr_graph(DeviceContext& vpr_device_ctx, num_clock_nodes, (float)(num_clock_nodes / orig_num_nodes)); /* Add clock nodes */ - add_rr_graph_clock_nodes(vpr_device_ctx.rr_graph_builder, clk_rr_lookup, - vpr_device_ctx.rr_graph, vpr_device_ctx.grid, 0, - vpr_device_ctx.arch->perimeter_cb, - vpr_device_ctx.arch->through_channel, clk_ntwk, - verbose); + add_rr_graph_clock_nodes( + vpr_device_ctx.rr_graph_builder, clk_rr_lookup, vpr_device_ctx.rr_graph, + vpr_device_ctx.grid, 0, vpr_device_ctx.arch->perimeter_cb, + vpr_device_ctx.arch->through_channel, clk_ntwk, verbose); VTR_LOGV(verbose, "Added %lu clock nodes to routing " "resource graph.\n", @@ -826,8 +823,8 @@ int append_clock_rr_graph(DeviceContext& vpr_device_ctx, vpr_device_ctx.rr_graph_builder, num_clock_edges, static_cast(clk_rr_lookup), vpr_device_ctx.rr_graph, vpr_device_ctx.grid, 0, - vpr_device_ctx.arch->perimeter_cb, - vpr_device_ctx.arch->through_channel, clk_ntwk, verbose); + vpr_device_ctx.arch->perimeter_cb, vpr_device_ctx.arch->through_channel, + clk_ntwk, verbose); VTR_LOGV(verbose, "Added %lu clock edges to routing " "resource graph.\n", From a78fddc3cbd43fcb869bf84df73e2e72e7e32e41 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 3 Jul 2024 19:59:24 -0700 Subject: [PATCH 04/91] [test] add a new testcase to validate perimeter cb --- .../regression_test_scripts/basic_reg_test.sh | 2 ++ .../perimeter_cb/config/task.conf | 36 +++++++++++++++++++ openfpga_flow/vpr_arch/README.md | 1 + 3 files changed, 39 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/tile_organization/perimeter_cb/config/task.conf diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index 72f1c01d6..e8902632c 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -190,6 +190,8 @@ run-task basic_tests/tile_organization/tileable_io $@ echo -e "Testing tiles with I/O consisting of subtiles"; run-task basic_tests/tile_organization/io_subtile $@ run-task basic_tests/tile_organization/io_subtile_strong $@ +echo -e "Testing tiles with routing tracks around I/O"; +run-task basic_tests/tile_organization/perimeter_cb $@ echo -e "Testing tile grouping on a homogeneous FPGA fabric (Full testbench)"; run-task basic_tests/tile_organization/homo_fabric_tile $@ echo -e "Testing tile grouping on a homogeneous FPGA fabric (Preconfigured testbench)"; diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/perimeter_cb/config/task.conf b/openfpga_flow/tasks/basic_tests/tile_organization/perimeter_cb/config/task.conf new file mode 100644 index 000000000..4e6a514f3 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/tile_organization/perimeter_cb/config/task.conf @@ -0,0 +1,36 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_IoSubtile_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout=3x3 + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = or2 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/vpr_arch/README.md b/openfpga_flow/vpr_arch/README.md index 7f8a000b5..2c69935c6 100644 --- a/openfpga_flow/vpr_arch/README.md +++ b/openfpga_flow/vpr_arch/README.md @@ -23,6 +23,7 @@ Please reveal the following architecture features in the names to help quickly s - reduced\_io: If I/Os only appear a certain or multiple sides of FPGAs - registerable\_io: If I/Os are registerable (can be either combinational or sequential) - IoSubtile: If I/O block contains sub tiles (more compact with a higher density of I/Os) +- PerimeterCb: If connection blocks can occur on perimeter I/Os (I/O tile has more routability) - CustomIoLoc: Use OpenFPGA's extended custom I/O location syntax - rstOnLut: The reset signal of CLB can feed LUT inputs through a local routing architecture - localClkGen: The clock signal of CLB can be generated by internal programmable resources From 3d19e10611a335378ae4e33725320c16dd1b8ee2 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 3 Jul 2024 21:48:37 -0700 Subject: [PATCH 05/91] [lib] update vtr --- vtr-verilog-to-routing | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index 3095c28d3..64bbd2454 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit 3095c28d3c2795e8042710d54f941be76ab1819d +Subproject commit 64bbd2454e81ea4790b27a7846cd5e454f5bc3f9 From bc94e08c77cdef86b84149f11892e02bd00bfb53 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 3 Jul 2024 22:28:22 -0700 Subject: [PATCH 06/91] [lib] update vtr and fixing some bugs in annotate gsb when perimeter_cb is enabled --- openfpga/src/annotation/annotate_rr_graph.cpp | 11 +++++++++-- vtr-verilog-to-routing | 2 +- 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/openfpga/src/annotation/annotate_rr_graph.cpp b/openfpga/src/annotation/annotate_rr_graph.cpp index 291d9cd9b..613364de2 100644 --- a/openfpga/src/annotation/annotate_rr_graph.cpp +++ b/openfpga/src/annotation/annotate_rr_graph.cpp @@ -420,6 +420,9 @@ void annotate_device_rr_gsb(const DeviceContext& vpr_device_ctx, */ vtr::Point gsb_range(vpr_device_ctx.grid.width() - 1, vpr_device_ctx.grid.height() - 1); + if (vpr_device_ctx.arch->perimeter_cb) { + gsb_range.set(vpr_device_ctx.grid.width(), vpr_device_ctx.grid.height()); + } device_rr_gsb.reserve(gsb_range); VTR_LOGV(verbose_output, "Start annotation GSB up to [%lu][%lu]\n", @@ -434,10 +437,14 @@ void annotate_device_rr_gsb(const DeviceContext& vpr_device_ctx, * the GSBs at the borderside correctly sort drive_rr_nodes should be * called if required by users */ + vtr::Point sub_gsb_range(vpr_device_ctx.grid.width() - 2, + vpr_device_ctx.grid.height() - 2); + if (vpr_device_ctx.arch->perimeter_cb) { + sub_gsb_range.set(vpr_device_ctx.grid.width() - 1, vpr_device_ctx.grid.height() - 1); + } const RRGSB& rr_gsb = build_rr_gsb(vpr_device_ctx, - vtr::Point(vpr_device_ctx.grid.width() - 2, - vpr_device_ctx.grid.height() - 2), + sub_gsb_range, layer, vtr::Point(ix, iy), include_clock); /* Add to device_rr_gsb */ vtr::Point gsb_coordinate = rr_gsb.get_sb_coordinate(); diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index 64bbd2454..7aa23041f 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit 64bbd2454e81ea4790b27a7846cd5e454f5bc3f9 +Subproject commit 7aa23041f18ce07a10b62fa7459166f613d039d2 From e06b53658c333e3284814bfe00bf88e97ecc5dd8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 3 Jul 2024 22:33:48 -0700 Subject: [PATCH 07/91] [lib] update vtr --- vtr-verilog-to-routing | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index 7aa23041f..97c106cd8 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit 7aa23041f18ce07a10b62fa7459166f613d039d2 +Subproject commit 97c106cd89bcd3c4a6d29dfea5101cd15554d3f3 From 550ce0c3901b4b2bcf524fbff6a379447b3f923f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 4 Jul 2024 10:58:44 -0700 Subject: [PATCH 08/91] [core] fixed the bug on build gsb when cbs are on perimeters --- openfpga/src/annotation/annotate_rr_graph.cpp | 32 +++++++++++++++---- 1 file changed, 26 insertions(+), 6 deletions(-) diff --git a/openfpga/src/annotation/annotate_rr_graph.cpp b/openfpga/src/annotation/annotate_rr_graph.cpp index 613364de2..badeca9de 100644 --- a/openfpga/src/annotation/annotate_rr_graph.cpp +++ b/openfpga/src/annotation/annotate_rr_graph.cpp @@ -126,7 +126,12 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, switch (side) { case TOP: /* TOP = 0 */ - /* For the border, we should take special care */ + /* For the border, we should take special care + * For the fabric where no cbs are on perimeter tiles (y = H - 1), + * the the border should be on the y = H - 2 + * For the fabric where cbs are on perimeter tiles, + * the border should be on the y = H - 1 + */ if (gsb_coord.y() == gsb_range.y()) { rr_gsb.clear_one_side(side_manager.get_side()); break; @@ -157,7 +162,12 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, break; case RIGHT: /* RIGHT = 1 */ - /* For the border, we should take special care */ + /* For the border, we should take special care + * For the fabric where no cbs are on perimeter tiles (x = W - 1), + * the the border should be on the x = W - 2 + * For the fabric where cbs are on perimeter tiles, + * the border should be on the x = W - 1 + */ if (gsb_coord.x() == gsb_range.x()) { rr_gsb.clear_one_side(side_manager.get_side()); break; @@ -189,8 +199,13 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, gsb_coord.x() + 1, gsb_coord.y(), OPIN, opin_grid_side[1]); break; case BOTTOM: /* BOTTOM = 2*/ - /* For the border, we should take special care */ - if (gsb_coord.y() == 0) { + /* For the border, we should take special care + * For the fabric where no cbs are on perimeter tiles (y = 0), + * the the border should be on the y = 0 + * For the fabric where cbs are on perimeter tiles, + * the border should be on the y = - 1, leading to no border + */ + if (!vpr_device_ctx.arch->perimeter_cb && gsb_coord.y() == 0) { rr_gsb.clear_one_side(side_manager.get_side()); break; } @@ -220,8 +235,13 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, gsb_coord.y(), OPIN, opin_grid_side[1]); break; case LEFT: /* LEFT = 3 */ - /* For the border, we should take special care */ - if (gsb_coord.x() == 0) { + /* For the border, we should take special care + * For the fabric where no cbs are on perimeter tiles (x = 0), + * the the border should be on the x = 0 + * For the fabric where cbs are on perimeter tiles, + * the border should be on the x = - 1, leading to no border + */ + if (!vpr_device_ctx.arch->perimeter_cb && gsb_coord.x() == 0) { rr_gsb.clear_one_side(side_manager.get_side()); break; } From 724c14d1f7fe53c200060429ea328a031e4f6759 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 4 Jul 2024 11:09:01 -0700 Subject: [PATCH 09/91] [core] fixed a bug on build top module connections on perimeter gsb when cbs occur --- openfpga/src/fabric/build_top_module_connection.cpp | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/openfpga/src/fabric/build_top_module_connection.cpp b/openfpga/src/fabric/build_top_module_connection.cpp index e6a98cd46..38b0491a9 100644 --- a/openfpga/src/fabric/build_top_module_connection.cpp +++ b/openfpga/src/fabric/build_top_module_connection.cpp @@ -760,6 +760,12 @@ static void add_top_module_nets_connect_sb_and_cb( } if (RIGHT == side_manager.get_side() || BOTTOM == side_manager.get_side()) { + /* Only for the condition where cbs are on perimeter, the neighbour cb will be invalid + * Bypass in such case on finding neighbour cbs + */ + if (instance_sb_coordinate.x() == device_rr_gsb.get_gsb_range().x() || instance_sb_coordinate.y() == 0) { + continue; + } const RRGSB& adjacent_gsb = device_rr_gsb.get_gsb(module_gsb_cb_coordinate); if (false == adjacent_gsb.is_cb_exist(cb_type)) { From 93649a12440db99d450f9bd7b93c891e5ce04559 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 4 Jul 2024 12:16:32 -0700 Subject: [PATCH 10/91] [lib] update vtr --- vtr-verilog-to-routing | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index 97c106cd8..b172d26a0 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit 97c106cd89bcd3c4a6d29dfea5101cd15554d3f3 +Subproject commit b172d26a0c75dbabdaf78fc37d6260f74f22ff4c From 5736f45f769b552b3912b1dbf8a3c79cbbbf9366 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 4 Jul 2024 12:18:20 -0700 Subject: [PATCH 11/91] [lib] update vtr --- vtr-verilog-to-routing | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index b172d26a0..ae9eb2dbb 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit b172d26a0c75dbabdaf78fc37d6260f74f22ff4c +Subproject commit ae9eb2dbb0e685d6a2bff11d01713498f12e2b27 From 48590df452c13f7e559a9375d32bec30d23b2e3e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 4 Jul 2024 12:20:20 -0700 Subject: [PATCH 12/91] [lib] update vtr --- vtr-verilog-to-routing | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index ae9eb2dbb..159bea4ff 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit ae9eb2dbb0e685d6a2bff11d01713498f12e2b27 +Subproject commit 159bea4ff7e2df8eedaa219cf1765b5dee1921f1 From a7178823047d6283775ccb906febd4193ca83a17 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 4 Jul 2024 12:44:48 -0700 Subject: [PATCH 13/91] [core] now when perimeter_cb is on, I/O pins can access three sides of routing tracks --- openfpga/src/fabric/build_device_module.cpp | 2 +- .../build_grid_module_duplicated_pins.cpp | 20 +++++++------ .../build_grid_module_duplicated_pins.h | 6 ++-- .../src/fabric/build_grid_module_utils.cpp | 18 +++++++++--- openfpga/src/fabric/build_grid_module_utils.h | 4 +-- openfpga/src/fabric/build_grid_modules.cpp | 28 +++++++++++-------- openfpga/src/fabric/build_tile_modules.cpp | 15 ++++++---- openfpga/src/fabric/build_tile_modules.h | 1 + 8 files changed, 60 insertions(+), 34 deletions(-) diff --git a/openfpga/src/fabric/build_device_module.cpp b/openfpga/src/fabric/build_device_module.cpp index 757171c78..e03ee2510 100644 --- a/openfpga/src/fabric/build_device_module.cpp +++ b/openfpga/src/fabric/build_device_module.cpp @@ -128,7 +128,7 @@ int build_device_module_graph( openfpga_ctx.device_rr_gsb(), vpr_device_ctx.rr_graph, openfpga_ctx.arch().tile_annotations, openfpga_ctx.arch().circuit_lib, sram_model, openfpga_ctx.arch().config_protocol.type(), - name_module_using_index, frame_view, verbose); + name_module_using_index, vpr_device_ctx.arch->perimeter_cb, frame_view, verbose); } /* Build FPGA fabric top-level module */ diff --git a/openfpga/src/fabric/build_grid_module_duplicated_pins.cpp b/openfpga/src/fabric/build_grid_module_duplicated_pins.cpp index 32304bdc7..7e628e459 100644 --- a/openfpga/src/fabric/build_grid_module_duplicated_pins.cpp +++ b/openfpga/src/fabric/build_grid_module_duplicated_pins.cpp @@ -55,7 +55,8 @@ void add_grid_module_duplicated_pb_type_ports( ModuleManager& module_manager, const ModuleId& grid_module, const VprDeviceAnnotation& vpr_device_annotation, t_physical_tile_type_ptr grid_type_descriptor, - const TileAnnotation& tile_annotation, const e_side& border_side) { + const TileAnnotation& tile_annotation, const e_side& border_side, + const bool& perimeter_cb) { /* Ensure that we have a valid grid_type_descriptor */ VTR_ASSERT(false == is_empty_type(grid_type_descriptor)); @@ -66,7 +67,7 @@ void add_grid_module_duplicated_pb_type_ports( */ if (true == is_io_type(grid_type_descriptor)) { grid_pin_sides = - find_grid_module_pin_sides(grid_type_descriptor, border_side); + find_grid_module_pin_sides(grid_type_descriptor, border_side, perimeter_cb); } else { grid_pin_sides = {TOP, RIGHT, BOTTOM, LEFT}; } @@ -172,7 +173,9 @@ static void add_grid_module_net_connect_duplicated_pb_graph_pin( const size_t& child_inst_subtile_index, const VprDeviceAnnotation& vpr_device_annotation, t_physical_tile_type_ptr grid_type_descriptor, t_pb_graph_pin* pb_graph_pin, - const e_side& border_side, const e_pin2pin_interc_type& pin2pin_interc_type) { + const e_side& border_side, + const bool& perimeter_cb, + const e_pin2pin_interc_type& pin2pin_interc_type) { /* Make sure this is ONLY applied to output pins */ VTR_ASSERT(OUTPUT2OUTPUT_INTERC == pin2pin_interc_type); @@ -183,7 +186,7 @@ static void add_grid_module_net_connect_duplicated_pb_graph_pin( */ if (true == is_io_type(grid_type_descriptor)) { grid_pin_sides = - find_grid_module_pin_sides(grid_type_descriptor, border_side); + find_grid_module_pin_sides(grid_type_descriptor, border_side, perimeter_cb); } else { grid_pin_sides = {TOP, RIGHT, BOTTOM, LEFT}; } @@ -316,7 +319,8 @@ void add_grid_module_nets_connect_duplicated_pb_type_ports( const ModuleId& child_module, const size_t& child_instance, const t_sub_tile& sub_tile, const VprDeviceAnnotation& vpr_device_annotation, t_physical_tile_type_ptr grid_type_descriptor, - const TileAnnotation& tile_annotation, const e_side& border_side) { + const TileAnnotation& tile_annotation, const e_side& border_side, + const bool& perimeter_cb) { /* Ensure that we have a valid grid_type_descriptor */ VTR_ASSERT(false == is_empty_type(grid_type_descriptor)); @@ -334,7 +338,7 @@ void add_grid_module_nets_connect_duplicated_pb_type_ports( module_manager, grid_module, child_module, child_instance, child_inst_subtile_index, vpr_device_annotation, grid_type_descriptor, tile_annotation, &(top_pb_graph_node->input_pins[iport][ipin]), - border_side, INPUT2INPUT_INTERC); + border_side, perimeter_cb, INPUT2INPUT_INTERC); } } @@ -345,7 +349,7 @@ void add_grid_module_nets_connect_duplicated_pb_type_ports( module_manager, grid_module, child_module, child_instance, child_inst_subtile_index, vpr_device_annotation, grid_type_descriptor, &(top_pb_graph_node->output_pins[iport][ipin]), border_side, - OUTPUT2OUTPUT_INTERC); + perimeter_cb, OUTPUT2OUTPUT_INTERC); } } @@ -356,7 +360,7 @@ void add_grid_module_nets_connect_duplicated_pb_type_ports( module_manager, grid_module, child_module, child_instance, child_inst_subtile_index, vpr_device_annotation, grid_type_descriptor, tile_annotation, &(top_pb_graph_node->clock_pins[iport][ipin]), - border_side, INPUT2INPUT_INTERC); + border_side, perimeter_cb, INPUT2INPUT_INTERC); } } } diff --git a/openfpga/src/fabric/build_grid_module_duplicated_pins.h b/openfpga/src/fabric/build_grid_module_duplicated_pins.h index 4f2eafee2..9f95b7dd7 100644 --- a/openfpga/src/fabric/build_grid_module_duplicated_pins.h +++ b/openfpga/src/fabric/build_grid_module_duplicated_pins.h @@ -21,14 +21,16 @@ void add_grid_module_duplicated_pb_type_ports( ModuleManager& module_manager, const ModuleId& grid_module, const VprDeviceAnnotation& vpr_device_annotation, t_physical_tile_type_ptr grid_type_descriptor, - const TileAnnotation& tile_annotation, const e_side& border_side); + const TileAnnotation& tile_annotation, const e_side& border_side, + const bool& perimeter_cb); void add_grid_module_nets_connect_duplicated_pb_type_ports( ModuleManager& module_manager, const ModuleId& grid_module, const ModuleId& child_module, const size_t& child_instance, const t_sub_tile& sub_tile, const VprDeviceAnnotation& vpr_device_annotation, t_physical_tile_type_ptr grid_type_descriptor, - const TileAnnotation& tile_annotation, const e_side& border_side); + const TileAnnotation& tile_annotation, const e_side& border_side, + const bool& perimeter_cb); } /* end namespace openfpga */ diff --git a/openfpga/src/fabric/build_grid_module_utils.cpp b/openfpga/src/fabric/build_grid_module_utils.cpp index 3b3f14203..e78981ca2 100644 --- a/openfpga/src/fabric/build_grid_module_utils.cpp +++ b/openfpga/src/fabric/build_grid_module_utils.cpp @@ -24,7 +24,7 @@ namespace openfpga { * 5. I/O grids in the center part of FPGA can have ports on any side *******************************************************************/ std::vector find_grid_module_pin_sides( - t_physical_tile_type_ptr grid_type_descriptor, const e_side& border_side) { + t_physical_tile_type_ptr grid_type_descriptor, const e_side& border_side, const bool& perimeter_cb) { /* We must have an regular (non-I/O) type here */ VTR_ASSERT(true == is_io_type(grid_type_descriptor)); SideManager side_manager(border_side); @@ -33,7 +33,16 @@ std::vector find_grid_module_pin_sides( return {TOP, RIGHT, BOTTOM, LEFT}; } - return std::vector(1, side_manager.get_opposite()); + if (!perimeter_cb) { + return std::vector(1, side_manager.get_opposite()); + } + /* For cbs on perimeter, exclude the border side. All the other 3 sides are ok */ + std::vector pin_sides; + pin_sides.reserve(3); + for (e_side pin_side : {TOP, RIGHT, BOTTOM, LEFT}) { + pin_sides.push_back(pin_side); + } + return pin_sides; } /******************************************************************** @@ -47,7 +56,8 @@ void add_grid_module_net_connect_pb_graph_pin( const VprDeviceAnnotation& vpr_device_annotation, t_physical_tile_type_ptr grid_type_descriptor, const TileAnnotation& tile_annotation, t_pb_graph_pin* pb_graph_pin, - const e_side& border_side, const e_pin2pin_interc_type& pin2pin_interc_type) { + const e_side& border_side, const bool& perimeter_cb, + const e_pin2pin_interc_type& pin2pin_interc_type) { /* Find the pin side for I/O grids*/ std::vector grid_pin_sides; /* For I/O grids, we care only one side @@ -55,7 +65,7 @@ void add_grid_module_net_connect_pb_graph_pin( */ if (true == is_io_type(grid_type_descriptor)) { grid_pin_sides = - find_grid_module_pin_sides(grid_type_descriptor, border_side); + find_grid_module_pin_sides(grid_type_descriptor, border_side, perimeter_cb); } else { grid_pin_sides = {TOP, RIGHT, BOTTOM, LEFT}; } diff --git a/openfpga/src/fabric/build_grid_module_utils.h b/openfpga/src/fabric/build_grid_module_utils.h index a8d5f9d12..1051ae601 100644 --- a/openfpga/src/fabric/build_grid_module_utils.h +++ b/openfpga/src/fabric/build_grid_module_utils.h @@ -19,7 +19,7 @@ namespace openfpga { std::vector find_grid_module_pin_sides( - t_physical_tile_type_ptr grid_type_descriptor, const e_side& border_side); + t_physical_tile_type_ptr grid_type_descriptor, const e_side& border_side, const bool& perimeter_cb); void add_grid_module_net_connect_pb_graph_pin( ModuleManager& module_manager, const ModuleId& grid_module, @@ -28,7 +28,7 @@ void add_grid_module_net_connect_pb_graph_pin( const VprDeviceAnnotation& vpr_device_annotation, t_physical_tile_type_ptr grid_type_descriptor, const TileAnnotation& tile_annotation, t_pb_graph_pin* pb_graph_pin, - const e_side& border_side, + const e_side& border_side, const bool& perimeter_cb, const enum e_pin2pin_interc_type& pin2pin_interc_type); } /* end namespace openfpga */ diff --git a/openfpga/src/fabric/build_grid_modules.cpp b/openfpga/src/fabric/build_grid_modules.cpp index eaa24246b..8ffe94fda 100644 --- a/openfpga/src/fabric/build_grid_modules.cpp +++ b/openfpga/src/fabric/build_grid_modules.cpp @@ -42,7 +42,9 @@ static void add_grid_module_pb_type_ports( ModuleManager& module_manager, const ModuleId& grid_module, const VprDeviceAnnotation& vpr_device_annotation, t_physical_tile_type_ptr grid_type_descriptor, - const TileAnnotation& tile_annotation, const e_side& border_side) { + const TileAnnotation& tile_annotation, + const e_side& border_side, + const bool& perimeter_cb) { /* Ensure that we have a valid grid_type_descriptor */ VTR_ASSERT(nullptr != grid_type_descriptor); @@ -53,7 +55,7 @@ static void add_grid_module_pb_type_ports( */ if (true == is_io_type(grid_type_descriptor)) { grid_pin_sides = - find_grid_module_pin_sides(grid_type_descriptor, border_side); + find_grid_module_pin_sides(grid_type_descriptor, border_side, perimeter_cb); } else { grid_pin_sides = {TOP, RIGHT, BOTTOM, LEFT}; } @@ -125,7 +127,8 @@ static void add_grid_module_nets_connect_pb_type_ports( const ModuleId& child_module, const size_t& child_instance, const t_sub_tile& sub_tile, const VprDeviceAnnotation& vpr_device_annotation, t_physical_tile_type_ptr grid_type_descriptor, - const TileAnnotation& tile_annotation, const e_side& border_side) { + const TileAnnotation& tile_annotation, const e_side& border_side, + const bool& perimeter_cb) { /* Ensure that we have a valid grid_type_descriptor */ VTR_ASSERT(nullptr != grid_type_descriptor); @@ -144,7 +147,7 @@ static void add_grid_module_nets_connect_pb_type_ports( module_manager, grid_module, child_module, child_instance, child_inst_subtile_index, vpr_device_annotation, grid_type_descriptor, tile_annotation, &(top_pb_graph_node->input_pins[iport][ipin]), - border_side, INPUT2INPUT_INTERC); + border_side, perimeter_cb, INPUT2INPUT_INTERC); } } @@ -155,7 +158,7 @@ static void add_grid_module_nets_connect_pb_type_ports( module_manager, grid_module, child_module, child_instance, child_inst_subtile_index, vpr_device_annotation, grid_type_descriptor, tile_annotation, &(top_pb_graph_node->output_pins[iport][ipin]), - border_side, OUTPUT2OUTPUT_INTERC); + border_side, perimeter_cb, OUTPUT2OUTPUT_INTERC); } } @@ -166,7 +169,7 @@ static void add_grid_module_nets_connect_pb_type_ports( module_manager, grid_module, child_module, child_instance, child_inst_subtile_index, vpr_device_annotation, grid_type_descriptor, tile_annotation, &(top_pb_graph_node->clock_pins[iport][ipin]), - border_side, INPUT2INPUT_INTERC); + border_side, perimeter_cb, INPUT2INPUT_INTERC); } } } @@ -1168,6 +1171,7 @@ static int build_physical_tile_module( const TileAnnotation& tile_annotation, const e_side& border_side, const QLMemoryBankConfigSetting* ql_memory_bank_config_setting, const bool& duplicate_grid_pin, const bool& group_config_block, + const bool& perimeter_cb, const bool& verbose) { int status = CMD_EXEC_SUCCESS; /* Create a Module for the top-level physical block, and add to module manager @@ -1247,7 +1251,7 @@ static int build_physical_tile_module( /* Default way to add these ports by following the definition in pb_types */ add_grid_module_pb_type_ports(module_manager, grid_module, vpr_device_annotation, phy_block_type, - tile_annotation, border_side); + tile_annotation, border_side, perimeter_cb); /* Add module nets to connect the pb_type ports to sub modules */ for (const t_sub_tile& sub_tile : phy_block_type->sub_tiles) { VTR_ASSERT(sub_tile.equivalent_sites.size() == 1); @@ -1264,7 +1268,7 @@ static int build_physical_tile_module( module_manager.child_module_instances(grid_module, pb_module)) { add_grid_module_nets_connect_pb_type_ports( module_manager, grid_module, pb_module, child_instance, sub_tile, - vpr_device_annotation, phy_block_type, tile_annotation, border_side); + vpr_device_annotation, phy_block_type, tile_annotation, border_side, perimeter_cb); } } } else { @@ -1272,7 +1276,7 @@ static int build_physical_tile_module( /* Add these ports with duplication */ add_grid_module_duplicated_pb_type_ports( module_manager, grid_module, vpr_device_annotation, phy_block_type, - tile_annotation, border_side); + tile_annotation, border_side, perimeter_cb); /* Add module nets to connect the duplicated pb_type ports to sub modules */ for (const t_sub_tile& sub_tile : phy_block_type->sub_tiles) { @@ -1290,7 +1294,7 @@ static int build_physical_tile_module( module_manager.child_module_instances(grid_module, pb_module)) { add_grid_module_nets_connect_duplicated_pb_type_ports( module_manager, grid_module, pb_module, child_instance, sub_tile, - vpr_device_annotation, phy_block_type, tile_annotation, border_side); + vpr_device_annotation, phy_block_type, tile_annotation, border_side, perimeter_cb); } } } @@ -1436,7 +1440,7 @@ int build_grid_modules( module_manager, decoder_lib, device_annotation, circuit_lib, sram_orgz_type, sram_model, &physical_tile, tile_annotation, io_type_side, ql_memory_bank_config_setting, duplicate_grid_pin, - group_config_block, verbose); + group_config_block, device_ctx.arch->perimeter_cb, verbose); if (status != CMD_EXEC_SUCCESS) { return CMD_EXEC_FATAL_ERROR; } @@ -1446,7 +1450,7 @@ int build_grid_modules( status = build_physical_tile_module( module_manager, decoder_lib, device_annotation, circuit_lib, sram_orgz_type, sram_model, &physical_tile, tile_annotation, NUM_SIDES, - ql_memory_bank_config_setting, duplicate_grid_pin, group_config_block, + ql_memory_bank_config_setting, duplicate_grid_pin, group_config_block, device_ctx.arch->perimeter_cb, verbose); if (status != CMD_EXEC_SUCCESS) { return CMD_EXEC_FATAL_ERROR; diff --git a/openfpga/src/fabric/build_tile_modules.cpp b/openfpga/src/fabric/build_tile_modules.cpp index 74797aa39..f93cd07bf 100644 --- a/openfpga/src/fabric/build_tile_modules.cpp +++ b/openfpga/src/fabric/build_tile_modules.cpp @@ -1175,6 +1175,7 @@ static int build_tile_port_and_nets_from_pb( const TileAnnotation& tile_annotation, const vtr::Point& pb_coord, const std::vector& pb_instances, const FabricTile& fabric_tile, const FabricTileId& curr_fabric_tile_id, const size_t& ipb, + const bool& perimeter_cb, const bool& frame_view, const bool& verbose) { size_t pb_instance = pb_instances[ipb]; t_physical_tile_type_ptr phy_tile = grids.get_physical_type( @@ -1201,7 +1202,7 @@ static int build_tile_port_and_nets_from_pb( * Otherwise, we will iterate all the 4 sides */ if (true == is_io_type(phy_tile)) { - grid_pin_sides = find_grid_module_pin_sides(phy_tile, grid_side); + grid_pin_sides = find_grid_module_pin_sides(phy_tile, grid_side, perimeter_cb); } else { grid_pin_sides = {TOP, RIGHT, BOTTOM, LEFT}; } @@ -1378,6 +1379,7 @@ static int build_tile_module_ports_and_nets( const FabricTileId& fabric_tile_id, const std::vector& pb_instances, const std::map>& cb_instances, const std::vector& sb_instances, const bool& name_module_using_index, + const bool& perimeter_cb, const bool& frame_view, const bool& verbose) { int status_code = CMD_EXEC_SUCCESS; @@ -1441,7 +1443,7 @@ static int build_tile_module_ports_and_nets( status_code = build_tile_port_and_nets_from_pb( module_manager, tile_module, grids, layer, vpr_device_annotation, rr_graph_view, tile_annotation, pb_coord, pb_instances, fabric_tile, - fabric_tile_id, ipb, frame_view, verbose); + fabric_tile_id, ipb, perimeter_cb, frame_view, verbose); if (status_code != CMD_EXEC_SUCCESS) { return CMD_EXEC_FATAL_ERROR; } @@ -1487,7 +1489,9 @@ static int build_tile_module( const TileAnnotation& tile_annotation, const CircuitLibrary& circuit_lib, const CircuitModelId& sram_model, const e_config_protocol_type& sram_orgz_type, - const bool& name_module_using_index, const bool& frame_view, + const bool& name_module_using_index, + const bool& perimeter_cb, + const bool& frame_view, const bool& verbose) { int status_code = CMD_EXEC_SUCCESS; @@ -1635,7 +1639,7 @@ static int build_tile_module( module_manager, tile_module, grids, layer, vpr_device_annotation, device_rr_gsb, rr_graph_view, tile_annotation, fabric_tile, fabric_tile_id, pb_instances, cb_instances, sb_instances, name_module_using_index, - frame_view, verbose); + perimeter_cb, frame_view, verbose); /* Add global ports to the pb_module: * This is a much easier job after adding sub modules (instances), @@ -1709,6 +1713,7 @@ int build_tile_modules(ModuleManager& module_manager, const CircuitModelId& sram_model, const e_config_protocol_type& sram_orgz_type, const bool& name_module_using_index, + const bool& perimeter_cb, const bool& frame_view, const bool& verbose) { vtr::ScopedStartFinishTimer timer("Build tile modules for the FPGA fabric"); @@ -1722,7 +1727,7 @@ int build_tile_modules(ModuleManager& module_manager, module_manager, decoder_lib, fabric_tile, fabric_tile_id, grids, layer, vpr_device_annotation, device_rr_gsb, rr_graph_view, tile_annotation, circuit_lib, sram_model, sram_orgz_type, name_module_using_index, - frame_view, verbose); + perimeter_cb, frame_view, verbose); if (status_code != CMD_EXEC_SUCCESS) { return CMD_EXEC_FATAL_ERROR; } diff --git a/openfpga/src/fabric/build_tile_modules.h b/openfpga/src/fabric/build_tile_modules.h index 83f219610..e3a629808 100644 --- a/openfpga/src/fabric/build_tile_modules.h +++ b/openfpga/src/fabric/build_tile_modules.h @@ -36,6 +36,7 @@ int build_tile_modules(ModuleManager& module_manager, const CircuitModelId& sram_model, const e_config_protocol_type& sram_orgz_type, const bool& name_module_using_index, + const bool& perimeter_cb, const bool& frame_view, const bool& verbose); } /* end namespace openfpga */ From a3723b33b35a9482f8e8692aedbbe9379a7278de Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 4 Jul 2024 12:52:29 -0700 Subject: [PATCH 14/91] [core] fixed a minor bug --- openfpga/src/fabric/build_grid_module_utils.cpp | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/openfpga/src/fabric/build_grid_module_utils.cpp b/openfpga/src/fabric/build_grid_module_utils.cpp index e78981ca2..951e2429d 100644 --- a/openfpga/src/fabric/build_grid_module_utils.cpp +++ b/openfpga/src/fabric/build_grid_module_utils.cpp @@ -40,7 +40,9 @@ std::vector find_grid_module_pin_sides( std::vector pin_sides; pin_sides.reserve(3); for (e_side pin_side : {TOP, RIGHT, BOTTOM, LEFT}) { - pin_sides.push_back(pin_side); + if (pin_side != border_side) { + pin_sides.push_back(pin_side); + } } return pin_sides; } From b80ed8d15cf328e180319dafb433997a406b6b3e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 4 Jul 2024 12:58:16 -0700 Subject: [PATCH 15/91] [core] fixed a bug --- openfpga/src/fabric/build_top_module_connection.cpp | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/openfpga/src/fabric/build_top_module_connection.cpp b/openfpga/src/fabric/build_top_module_connection.cpp index 38b0491a9..2493c20c9 100644 --- a/openfpga/src/fabric/build_top_module_connection.cpp +++ b/openfpga/src/fabric/build_top_module_connection.cpp @@ -763,7 +763,10 @@ static void add_top_module_nets_connect_sb_and_cb( /* Only for the condition where cbs are on perimeter, the neighbour cb will be invalid * Bypass in such case on finding neighbour cbs */ - if (instance_sb_coordinate.x() == device_rr_gsb.get_gsb_range().x() || instance_sb_coordinate.y() == 0) { + if (BOTTOM == side_manager.get_side() && instance_sb_coordinate.y() == 0) { + continue; + } + if (RIGHT == side_manager.get_side() && instance_sb_coordinate.x() == device_rr_gsb.get_gsb_range().x()) { continue; } const RRGSB& adjacent_gsb = From 75407b1e8c0fafbfb6923fa4932f11a02f802973 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 4 Jul 2024 13:15:54 -0700 Subject: [PATCH 16/91] [lib] update vtr --- vtr-verilog-to-routing | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index 159bea4ff..fbbf53d82 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit 159bea4ff7e2df8eedaa219cf1765b5dee1921f1 +Subproject commit fbbf53d8207d55df8c6c62e1a0505f94ccba612a From d2a68ff9c5316b2a4db6941c0629ca6aebda48f2 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 4 Jul 2024 13:25:57 -0700 Subject: [PATCH 17/91] [core] now corner tile are considered as config child --- openfpga/src/fabric/build_top_module_memory.cpp | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/openfpga/src/fabric/build_top_module_memory.cpp b/openfpga/src/fabric/build_top_module_memory.cpp index 5dae3f0f4..302bd6675 100644 --- a/openfpga/src/fabric/build_top_module_memory.cpp +++ b/openfpga/src/fabric/build_top_module_memory.cpp @@ -458,12 +458,12 @@ void organize_top_module_memory_modules( std::map>> io_coords; /* BOTTOM side I/Os */ - for (size_t ix = 1; ix < grids.width() - 1; ++ix) { + for (size_t ix = 0; ix < grids.width() - 1; ++ix) { io_coords[BOTTOM].push_back(vtr::Point(ix, 0)); } /* RIGHT side I/Os */ - for (size_t iy = 1; iy < grids.height() - 1; ++iy) { + for (size_t iy = 0; iy < grids.height() - 1; ++iy) { io_coords[RIGHT].push_back(vtr::Point(grids.width() - 1, iy)); } @@ -483,13 +483,13 @@ void organize_top_module_memory_modules( * +--------+ +--------+ * */ - for (size_t ix = grids.width() - 2; ix >= 1; --ix) { + for (size_t ix = grids.width() - 1; ix >= 1; --ix) { io_coords[TOP].push_back(vtr::Point(ix, grids.height() - 1)); } io_coords[TOP].push_back(vtr::Point(0, grids.height() - 1)); /* LEFT side I/Os */ - for (size_t iy = grids.height() - 2; iy >= 1; --iy) { + for (size_t iy = grids.height() - 1; iy >= 1; --iy) { io_coords[LEFT].push_back(vtr::Point(0, iy)); } From 4b53e57c92a8c571ec68667ec59d2dd2a7383643 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 4 Jul 2024 13:33:04 -0700 Subject: [PATCH 18/91] [core] fixed a bug --- .../src/fabric/build_top_module_memory.cpp | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/openfpga/src/fabric/build_top_module_memory.cpp b/openfpga/src/fabric/build_top_module_memory.cpp index 302bd6675..47238685e 100644 --- a/openfpga/src/fabric/build_top_module_memory.cpp +++ b/openfpga/src/fabric/build_top_module_memory.cpp @@ -370,12 +370,13 @@ void build_top_module_configurable_regions( * Note: the organization of inter-tile aims to reduce the wire length * to connect between tiles. Therefore, it is organized as a snake * where we can avoid long wires between rows and columns + * Note: Corner I/Os only occur when perimeter cb is allowed * * +--------------------------------------------------------+ - * | +------+------+-----+------+ | - * | | I/O | I/O | ... | I/O | | - * | | TOP | TOP | | TOP | | - * | +------+------+-----+------+ | + * | +------+ +------+------+-----+------+ +------+ | + * | | I/O | | I/O | I/O | ... | I/O | | I/O | | + * | | LEFT | | TOP | TOP | | TOP | | TOP | | + * | +------+ +------+------+-----+------+ +------+ | * | +---------------------------------->tail | * | +------+ | +------+------+-----+------+ +------+ | * | | | | | | | | | | | | @@ -397,10 +398,10 @@ void build_top_module_configurable_regions( * | | LEFT | | [0] | [1] | | [i] | | |RIGHT | | * | +------+ +------+------+-----+------+ | +------+ | * +-------------------------------------------+ | - * +------+------+-----+------+ | - * | I/O | I/O | ... | I/O | | - * |BOTTOM|BOTTOM| |BOTTOM| | - * +------+------+-----+------+ | + * +------+ +------+------+-----+------+ +------+ | + * | I/O | | I/O | I/O | ... | I/O | | I/O | | + * |BOTTOM| |BOTTOM|BOTTOM| |BOTTOM| |RIGHT | | + * +------+ +------+------+-----+------+ +------+ | * head >-----------------------------------------------+ * * Inner tile connection: @@ -486,7 +487,6 @@ void organize_top_module_memory_modules( for (size_t ix = grids.width() - 1; ix >= 1; --ix) { io_coords[TOP].push_back(vtr::Point(ix, grids.height() - 1)); } - io_coords[TOP].push_back(vtr::Point(0, grids.height() - 1)); /* LEFT side I/Os */ for (size_t iy = grids.height() - 1; iy >= 1; --iy) { From a8850d4f0f10eb68b70520b536fb1a76414f9d66 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 4 Jul 2024 14:22:30 -0700 Subject: [PATCH 19/91] [core] now verbose mode is applicable to more build top module cb instances --- openfpga/src/fabric/build_top_module.cpp | 2 +- .../build_top_module_child_fine_grained_instance.cpp | 11 +++++++---- .../build_top_module_child_fine_grained_instance.h | 3 ++- 3 files changed, 10 insertions(+), 6 deletions(-) diff --git a/openfpga/src/fabric/build_top_module.cpp b/openfpga/src/fabric/build_top_module.cpp index 238004e4d..bce676019 100644 --- a/openfpga/src/fabric/build_top_module.cpp +++ b/openfpga/src/fabric/build_top_module.cpp @@ -79,7 +79,7 @@ int build_top_module( rr_clock_lookup, vpr_device_annotation, grids, layer, tile_annotation, rr_graph, device_rr_gsb, tile_direct, arch_direct, config_protocol, sram_model, frame_view, compact_routing_hierarchy, duplicate_grid_pin, - fabric_key, group_config_block); + fabric_key, group_config_block, verbose); } else { /* Build the tile instances under the top module */ status = build_top_module_tile_child_instances( diff --git a/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp b/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp index 7640a969c..e3abe7c07 100644 --- a/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp +++ b/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp @@ -244,7 +244,7 @@ static vtr::Matrix add_top_module_switch_block_instances( static vtr::Matrix add_top_module_connection_block_instances( ModuleManager& module_manager, const ModuleId& top_module, const DeviceRRGSB& device_rr_gsb, const t_rr_type& cb_type, - const bool& compact_routing_hierarchy) { + const bool& compact_routing_hierarchy, const bool& verbose) { vtr::ScopedStartFinishTimer timer( "Add connection block instances to top module"); @@ -264,6 +264,7 @@ static vtr::Matrix add_top_module_connection_block_instances( vtr::Point cb_coordinate(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); if (false == rr_gsb.is_cb_exist(cb_type)) { + VTR_LOGV(verbose, "Skip connnection block at (%lu, %lu) as it does not exist\n", cb_coordinate.x(), cb_coordinate.y()); continue; } /* If we use compact routing hierarchy, we should instanciate the unique @@ -295,6 +296,7 @@ static vtr::Matrix add_top_module_connection_block_instances( top_module, cb_module, cb_instance_ids[rr_gsb.get_cb_x(cb_type)][rr_gsb.get_cb_y(cb_type)], cb_instance_name); + VTR_LOGV(verbose, "Added connnection block '%s' (module '%s')\n", cb_instance_name.c_str(), cb_module_name.c_str()); } } @@ -445,7 +447,8 @@ int build_top_module_fine_grained_child_instances( const ConfigProtocol& config_protocol, const CircuitModelId& sram_model, const bool& frame_view, const bool& compact_routing_hierarchy, const bool& duplicate_grid_pin, const FabricKey& fabric_key, - const bool& group_config_block) { + const bool& group_config_block, + const bool& verbose) { int status = CMD_EXEC_SUCCESS; std::map> cb_instance_ids; @@ -460,10 +463,10 @@ int build_top_module_fine_grained_child_instances( /* Add all the CBX and CBYs across the fabric */ cb_instance_ids[CHANX] = add_top_module_connection_block_instances( module_manager, top_module, device_rr_gsb, CHANX, - compact_routing_hierarchy); + compact_routing_hierarchy, verbose); cb_instance_ids[CHANY] = add_top_module_connection_block_instances( module_manager, top_module, device_rr_gsb, CHANY, - compact_routing_hierarchy); + compact_routing_hierarchy, verbose); /* Update I/O children list */ add_top_module_io_children(module_manager, top_module, grids, layer, diff --git a/openfpga/src/fabric/build_top_module_child_fine_grained_instance.h b/openfpga/src/fabric/build_top_module_child_fine_grained_instance.h index f54e07c24..dd4f8e24d 100644 --- a/openfpga/src/fabric/build_top_module_child_fine_grained_instance.h +++ b/openfpga/src/fabric/build_top_module_child_fine_grained_instance.h @@ -44,7 +44,8 @@ int build_top_module_fine_grained_child_instances( const ConfigProtocol& config_protocol, const CircuitModelId& sram_model, const bool& frame_view, const bool& compact_routing_hierarchy, const bool& duplicate_grid_pin, const FabricKey& fabric_key, - const bool& group_config_block); + const bool& group_config_block, + const bool& verbose); } /* end namespace openfpga */ From f560fb83816b90844769fe6dc34fa878e3f5f833 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 4 Jul 2024 14:27:17 -0700 Subject: [PATCH 20/91] [core] more verbose --- .../fabric/build_top_module_child_fine_grained_instance.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp b/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp index e3abe7c07..3978339a2 100644 --- a/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp +++ b/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp @@ -264,7 +264,7 @@ static vtr::Matrix add_top_module_connection_block_instances( vtr::Point cb_coordinate(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); if (false == rr_gsb.is_cb_exist(cb_type)) { - VTR_LOGV(verbose, "Skip connnection block at (%lu, %lu) as it does not exist\n", cb_coordinate.x(), cb_coordinate.y()); + VTR_LOGV(verbose, "Skip %s connnection block at (%lu, %lu) as it does not exist\n", cb_type == CHANX ? "X-" : "Y-", cb_coordinate.x(), cb_coordinate.y()); continue; } /* If we use compact routing hierarchy, we should instanciate the unique @@ -296,7 +296,7 @@ static vtr::Matrix add_top_module_connection_block_instances( top_module, cb_module, cb_instance_ids[rr_gsb.get_cb_x(cb_type)][rr_gsb.get_cb_y(cb_type)], cb_instance_name); - VTR_LOGV(verbose, "Added connnection block '%s' (module '%s')\n", cb_instance_name.c_str(), cb_module_name.c_str()); + VTR_LOGV(verbose, "Added %s connnection block '%s' (module '%s')\n", cb_type == CHANX ? "X-" : "Y-", cb_instance_name.c_str(), cb_module_name.c_str()); } } From 6d798897fd60b0a1a204ce956e9229aa1f5a9039 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 4 Jul 2024 14:46:57 -0700 Subject: [PATCH 21/91] [lib] update vtr --- .../src/fabric/build_top_module_child_fine_grained_instance.cpp | 1 + vtr-verilog-to-routing | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp b/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp index 3978339a2..2e7a33182 100644 --- a/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp +++ b/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp @@ -261,6 +261,7 @@ static vtr::Matrix add_top_module_connection_block_instances( * We will skip those modules */ const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy); + VTR_LOGV(verbose, "Try to add %s connnection block at (%lu, %lu)\n", cb_type == CHANX ? "X-" : "Y-", ix, iy); vtr::Point cb_coordinate(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); if (false == rr_gsb.is_cb_exist(cb_type)) { diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index fbbf53d82..19fa43cc6 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit fbbf53d8207d55df8c6c62e1a0505f94ccba612a +Subproject commit 19fa43cc62bf7a38e4151c1c3867a760ba683719 From 93af72f1e362aa22a8dbbf0b734b9c7a9f703f0b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 4 Jul 2024 14:57:36 -0700 Subject: [PATCH 22/91] [lib] update vtr --- vtr-verilog-to-routing | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index 19fa43cc6..589b6bcd8 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit 19fa43cc62bf7a38e4151c1c3867a760ba683719 +Subproject commit 589b6bcd8bd37ac445c55239af02c757223f5d4f From 1dd03d0fddc71d8b2359d60fc60012379df8a96b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 4 Jul 2024 18:34:39 -0700 Subject: [PATCH 23/91] [core] on a new feature to connect undriven pins to ground --- .../fpga_verilog/verilog_module_writer.cpp | 100 ++++++++++++------ 1 file changed, 65 insertions(+), 35 deletions(-) diff --git a/openfpga/src/fpga_verilog/verilog_module_writer.cpp b/openfpga/src/fpga_verilog/verilog_module_writer.cpp index af901e592..7feaa1c28 100644 --- a/openfpga/src/fpga_verilog/verilog_module_writer.cpp +++ b/openfpga/src/fpga_verilog/verilog_module_writer.cpp @@ -139,6 +139,67 @@ static BasicPort generate_verilog_port_for_module_net( return port_to_return; } +/******************************************************************** + * Find all the undriven nets that are going to be local wires + * And organize it in a vector of ports + * Verilog wire writter function will use the output of this function + * to write up local wire declaration in Verilog format + *******************************************************************/ +static void +find_verilog_module_local_undriven_wires( + std::map>& local_wires; + const ModuleManager& module_manager, + const ModuleId& module_id, + const std::vector& port_type_blacklist) { + + /* Local wires could also happen for undriven ports of child module */ + for (const ModuleId& child : module_manager.child_modules(module_id)) { + for (size_t instance : + module_manager.child_module_instances(module_id, child)) { + for (const ModulePortId& child_port_id : + module_manager.module_ports(child)) { + BasicPort child_port = module_manager.module_port(child, child_port_id); + ModuleManager::e_module_port_type child_port_type = module_manager.port_type(child, child_port_id); + bool filter_out = false; + for (ModuleManager::e_module_port_type curr_port_type : port_type_blacklist) { + if (child_port_type == curr_port_type) { + filter_out = true; + break; + } + } + if (filter_out) { + continue; + } + std::vector undriven_pins; + for (size_t child_pin : child_port.pins()) { + /* Find the net linked to the pin */ + ModuleNetId net = module_manager.module_instance_port_net( + module_id, child, instance, child_port_id, child_pin); + /* We only care undriven ports */ + if (ModuleNetId::INVALID() == net) { + undriven_pins.push_back(child_pin); + } + } + if (true == undriven_pins.empty()) { + continue; + } + /* Reach here, we need a local wire, we will create a port only for the + * undriven pins of the port! */ + BasicPort instance_port; + instance_port.set_name(generate_verilog_undriven_local_wire_name( + module_manager, module_id, child, instance, child_port_id)); + /* We give the same port name as child module, this case happens to + * global ports */ + instance_port.set_width( + *std::min_element(undriven_pins.begin(), undriven_pins.end()), + *std::max_element(undriven_pins.begin(), undriven_pins.end())); + + local_wires[instance_port.get_name()].push_back(instance_port); + } + } + } +} + /******************************************************************** * Find all the nets that are going to be local wires * And organize it in a vector of ports @@ -206,41 +267,7 @@ find_verilog_module_local_wires(const ModuleManager& module_manager, } } - /* Local wires could also happen for undriven ports of child module */ - for (const ModuleId& child : module_manager.child_modules(module_id)) { - for (size_t instance : - module_manager.child_module_instances(module_id, child)) { - for (const ModulePortId& child_port_id : - module_manager.module_ports(child)) { - BasicPort child_port = module_manager.module_port(child, child_port_id); - std::vector undriven_pins; - for (size_t child_pin : child_port.pins()) { - /* Find the net linked to the pin */ - ModuleNetId net = module_manager.module_instance_port_net( - module_id, child, instance, child_port_id, child_pin); - /* We only care undriven ports */ - if (ModuleNetId::INVALID() == net) { - undriven_pins.push_back(child_pin); - } - } - if (true == undriven_pins.empty()) { - continue; - } - /* Reach here, we need a local wire, we will create a port only for the - * undriven pins of the port! */ - BasicPort instance_port; - instance_port.set_name(generate_verilog_undriven_local_wire_name( - module_manager, module_id, child, instance, child_port_id)); - /* We give the same port name as child module, this case happens to - * global ports */ - instance_port.set_width( - *std::min_element(undriven_pins.begin(), undriven_pins.end()), - *std::max_element(undriven_pins.begin(), undriven_pins.end())); - - local_wires[instance_port.get_name()].push_back(instance_port); - } - } - } + find_verilog_module_local_undriven_wires(local_wires, module_manager, module_id, std::vector()); return local_wires; } @@ -575,6 +602,9 @@ void write_verilog_module_to_file( } } + /* Use constant to drive undriven local wires */ + find_verilog_module_local_undriven_wires(local_wires, module_manager, module_id, std::vector()); + /* Print an empty line as splitter */ fp << std::endl; From 4e21bbb3f1bae2e15c018bf5dce54936b6be6313 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 4 Jul 2024 20:32:56 -0700 Subject: [PATCH 24/91] [core] now support constant undriven local wires in verilog writer --- .../fpga_verilog/fabric_verilog_options.cpp | 7 ++++++ .../src/fpga_verilog/fabric_verilog_options.h | 3 +++ openfpga/src/fpga_verilog/verilog_grid.cpp | 3 +++ openfpga/src/fpga_verilog/verilog_lut.cpp | 1 + openfpga/src/fpga_verilog/verilog_memory.cpp | 5 ++++ .../fpga_verilog/verilog_module_writer.cpp | 24 +++++++++++++++++-- .../src/fpga_verilog/verilog_module_writer.h | 1 + openfpga/src/fpga_verilog/verilog_mux.cpp | 2 ++ openfpga/src/fpga_verilog/verilog_routing.cpp | 2 ++ .../verilog_shift_register_banks.cpp | 2 ++ openfpga/src/fpga_verilog/verilog_tile.cpp | 1 + .../src/fpga_verilog/verilog_top_module.cpp | 2 ++ 12 files changed, 51 insertions(+), 2 deletions(-) diff --git a/openfpga/src/fpga_verilog/fabric_verilog_options.cpp b/openfpga/src/fpga_verilog/fabric_verilog_options.cpp index 17fdad397..44da5e47c 100644 --- a/openfpga/src/fpga_verilog/fabric_verilog_options.cpp +++ b/openfpga/src/fpga_verilog/fabric_verilog_options.cpp @@ -21,6 +21,7 @@ FabricVerilogOption::FabricVerilogOption() { default_net_type_ = VERILOG_DEFAULT_NET_TYPE_NONE; time_stamp_ = true; use_relative_path_ = false; + constant_undriven_inputs_ = false; verbose_output_ = false; } @@ -53,6 +54,8 @@ e_verilog_default_net_type FabricVerilogOption::default_net_type() const { return default_net_type_; } +bool FabricVerilogOption::constant_undriven_inputs() const { return constant_undriven_inputs_; } + bool FabricVerilogOption::verbose_output() const { return verbose_output_; } /****************************************************************************** @@ -106,6 +109,10 @@ void FabricVerilogOption::set_default_net_type( } } +void FabricVerilogOption::set_constant_undriven_inputs(const bool& enabled) { + constant_undriven_inputs_ = enabled; +} + void FabricVerilogOption::set_verbose_output(const bool& enabled) { verbose_output_ = enabled; } diff --git a/openfpga/src/fpga_verilog/fabric_verilog_options.h b/openfpga/src/fpga_verilog/fabric_verilog_options.h index dfa7844e9..c8d5cc5eb 100644 --- a/openfpga/src/fpga_verilog/fabric_verilog_options.h +++ b/openfpga/src/fpga_verilog/fabric_verilog_options.h @@ -28,6 +28,7 @@ class FabricVerilogOption { bool compress_routing() const; e_verilog_default_net_type default_net_type() const; bool print_user_defined_template() const; + bool constant_undriven_inputs() const; bool verbose_output() const; public: /* Public mutators */ @@ -39,6 +40,7 @@ class FabricVerilogOption { void set_compress_routing(const bool& enabled); void set_print_user_defined_template(const bool& enabled); void set_default_net_type(const std::string& default_net_type); + void set_constant_undriven_inputs(const bool& enabled); void set_verbose_output(const bool& enabled); private: /* Internal Data */ @@ -50,6 +52,7 @@ class FabricVerilogOption { e_verilog_default_net_type default_net_type_; bool time_stamp_; bool use_relative_path_; + bool constant_undriven_inputs_; bool verbose_output_; }; diff --git a/openfpga/src/fpga_verilog/verilog_grid.cpp b/openfpga/src/fpga_verilog/verilog_grid.cpp index 7d79f3a4d..7ccdd35d4 100644 --- a/openfpga/src/fpga_verilog/verilog_grid.cpp +++ b/openfpga/src/fpga_verilog/verilog_grid.cpp @@ -114,6 +114,7 @@ static void print_verilog_primitive_block( /* Write the verilog module */ write_verilog_module_to_file(fp, module_manager, primitive_module, true, + options.constant_undriven_inputs(), options.default_net_type()); /* Close file handler */ @@ -234,6 +235,7 @@ static void rec_print_verilog_logical_tile( /* Write the verilog module */ write_verilog_module_to_file(fp, module_manager, pb_module, options.explicit_port_mapping(), + options.constant_undriven_inputs(), options.default_net_type()); print_verilog_comment( @@ -348,6 +350,7 @@ static void print_verilog_physical_tile_netlist( module_manager.module_name(grid_module) + " -----")); write_verilog_module_to_file(fp, module_manager, grid_module, options.explicit_port_mapping(), + options.constant_undriven_inputs(), options.default_net_type()); print_verilog_comment( diff --git a/openfpga/src/fpga_verilog/verilog_lut.cpp b/openfpga/src/fpga_verilog/verilog_lut.cpp index fab9205e4..b20b1d07a 100644 --- a/openfpga/src/fpga_verilog/verilog_lut.cpp +++ b/openfpga/src/fpga_verilog/verilog_lut.cpp @@ -63,6 +63,7 @@ void print_verilog_submodule_luts(const ModuleManager& module_manager, fp, module_manager, lut_module, options.explicit_port_mapping() || circuit_lib.dump_explicit_port_map(lut_model), + options.constant_undriven_inputs(), options.default_net_type()); } diff --git a/openfpga/src/fpga_verilog/verilog_memory.cpp b/openfpga/src/fpga_verilog/verilog_memory.cpp index 8c56e5e8e..0e0972269 100644 --- a/openfpga/src/fpga_verilog/verilog_memory.cpp +++ b/openfpga/src/fpga_verilog/verilog_memory.cpp @@ -61,6 +61,7 @@ static void print_verilog_mux_memory_module( fp, module_manager, mem_module, options.explicit_port_mapping() || circuit_lib.dump_explicit_port_map(mux_model), + options.constant_undriven_inputs(), options.default_net_type()); /* Add an empty line as a splitter */ @@ -84,6 +85,7 @@ static void print_verilog_mux_memory_module( fp, module_manager, feedthru_mem_module, options.explicit_port_mapping() || circuit_lib.dump_explicit_port_map(mux_model), + options.constant_undriven_inputs(), options.default_net_type()); /* Add an empty line as a splitter */ @@ -208,6 +210,7 @@ void print_verilog_submodule_memories( write_verilog_module_to_file(fp, module_manager, mem_module, options.explicit_port_mapping() || circuit_lib.dump_explicit_port_map(model), + options.constant_undriven_inputs(), options.default_net_type()); /* Add an empty line as a splitter */ @@ -228,6 +231,7 @@ void print_verilog_submodule_memories( write_verilog_module_to_file(fp, module_manager, feedthru_mem_module, options.explicit_port_mapping() || circuit_lib.dump_explicit_port_map(model), + options.constant_undriven_inputs(), options.default_net_type()); /* Add an empty line as a splitter */ @@ -241,6 +245,7 @@ void print_verilog_submodule_memories( /* Write the module content in Verilog format */ write_verilog_module_to_file(fp, module_manager, mem_group_module, options.explicit_port_mapping(), + options.constant_undriven_inputs(), options.default_net_type()); /* Add an empty line as a splitter */ diff --git a/openfpga/src/fpga_verilog/verilog_module_writer.cpp b/openfpga/src/fpga_verilog/verilog_module_writer.cpp index 7feaa1c28..1c5ce17ad 100644 --- a/openfpga/src/fpga_verilog/verilog_module_writer.cpp +++ b/openfpga/src/fpga_verilog/verilog_module_writer.cpp @@ -147,7 +147,7 @@ static BasicPort generate_verilog_port_for_module_net( *******************************************************************/ static void find_verilog_module_local_undriven_wires( - std::map>& local_wires; + std::map>& local_wires, const ModuleManager& module_manager, const ModuleId& module_id, const std::vector& port_type_blacklist) { @@ -572,6 +572,7 @@ static void write_verilog_instance_to_file(std::fstream& fp, void write_verilog_module_to_file( std::fstream& fp, const ModuleManager& module_manager, const ModuleId& module_id, const bool& use_explicit_port_map, + const bool& constant_local_undriven_wires, const e_verilog_default_net_type& default_net_type) { VTR_ASSERT(true == valid_file_stream(fp)); @@ -603,7 +604,26 @@ void write_verilog_module_to_file( } /* Use constant to drive undriven local wires */ - find_verilog_module_local_undriven_wires(local_wires, module_manager, module_id, std::vector()); + if (constant_local_undriven_wires) { + std::vector blacklist = { + ModuleManager::e_module_port_type::MODULE_GLOBAL_PORT, + ModuleManager::e_module_port_type::MODULE_GPIN_PORT, + ModuleManager::e_module_port_type::MODULE_GPOUT_PORT, + ModuleManager::e_module_port_type::MODULE_GPIO_PORT, + ModuleManager::e_module_port_type::MODULE_INOUT_PORT, + ModuleManager::e_module_port_type::MODULE_OUTPUT_PORT, + ModuleManager::e_module_port_type::MODULE_CLOCK_PORT + }; + std::map> local_undriven_wires; + find_verilog_module_local_undriven_wires(local_undriven_wires, module_manager, module_id, blacklist); + for (std::pair> port_group : + local_undriven_wires) { + for (const BasicPort& local_undriven_wire : port_group.second) { + fp << generate_verilog_port_constant_values(local_undriven_wire, std::vector(local_undriven_wire.get_width(), 0), false) << ";" + << std::endl; + } + } + } /* Print an empty line as splitter */ fp << std::endl; diff --git a/openfpga/src/fpga_verilog/verilog_module_writer.h b/openfpga/src/fpga_verilog/verilog_module_writer.h index 8e11637a7..0657c3985 100644 --- a/openfpga/src/fpga_verilog/verilog_module_writer.h +++ b/openfpga/src/fpga_verilog/verilog_module_writer.h @@ -19,6 +19,7 @@ namespace openfpga { void write_verilog_module_to_file( std::fstream& fp, const ModuleManager& module_manager, const ModuleId& module_id, const bool& use_explicit_port_map, + const bool& constant_local_undriven_wires, const e_verilog_default_net_type& default_net_type); } /* end namespace openfpga */ diff --git a/openfpga/src/fpga_verilog/verilog_mux.cpp b/openfpga/src/fpga_verilog/verilog_mux.cpp index 6fd2b2df4..38fcc0224 100644 --- a/openfpga/src/fpga_verilog/verilog_mux.cpp +++ b/openfpga/src/fpga_verilog/verilog_mux.cpp @@ -679,6 +679,7 @@ static void generate_verilog_mux_branch_module( fp, module_manager, mux_module, use_explicit_port_map || circuit_lib.dump_explicit_port_map(mux_model), + false, default_net_type); /* Add an empty line as a splitter */ fp << std::endl; @@ -1423,6 +1424,7 @@ static void generate_verilog_mux_module( circuit_lib.dump_explicit_port_map(mux_model) || circuit_lib.dump_explicit_port_map( circuit_lib.pass_gate_logic_model(mux_model))), + false, default_net_type); /* Add an empty line as a splitter */ fp << std::endl; diff --git a/openfpga/src/fpga_verilog/verilog_routing.cpp b/openfpga/src/fpga_verilog/verilog_routing.cpp index dbe59e935..3826a2552 100644 --- a/openfpga/src/fpga_verilog/verilog_routing.cpp +++ b/openfpga/src/fpga_verilog/verilog_routing.cpp @@ -117,6 +117,7 @@ static void print_verilog_routing_connection_box_unique_module( /* Write the verilog module */ write_verilog_module_to_file(fp, module_manager, cb_module, options.explicit_port_mapping(), + options.constant_undriven_inputs(), options.default_net_type()); /* Add an empty line as a splitter */ @@ -238,6 +239,7 @@ static void print_verilog_routing_switch_box_unique_module( /* Write the verilog module */ write_verilog_module_to_file(fp, module_manager, sb_module, options.explicit_port_mapping(), + options.constant_undriven_inputs(), options.default_net_type()); /* Close file handler */ diff --git a/openfpga/src/fpga_verilog/verilog_shift_register_banks.cpp b/openfpga/src/fpga_verilog/verilog_shift_register_banks.cpp index f2c0e02e6..6d4707b1e 100644 --- a/openfpga/src/fpga_verilog/verilog_shift_register_banks.cpp +++ b/openfpga/src/fpga_verilog/verilog_shift_register_banks.cpp @@ -58,6 +58,7 @@ void print_verilog_submodule_shift_register_banks( /* Write the module content in Verilog format */ write_verilog_module_to_file(fp, module_manager, sr_module, options.explicit_port_mapping(), + options.constant_undriven_inputs(), options.default_net_type()); /* Add an empty line as a splitter */ @@ -69,6 +70,7 @@ void print_verilog_submodule_shift_register_banks( /* Write the module content in Verilog format */ write_verilog_module_to_file(fp, module_manager, sr_module, options.explicit_port_mapping(), + options.constant_undriven_inputs(), options.default_net_type()); /* Add an empty line as a splitter */ diff --git a/openfpga/src/fpga_verilog/verilog_tile.cpp b/openfpga/src/fpga_verilog/verilog_tile.cpp index da32fc58c..f6b10beaf 100644 --- a/openfpga/src/fpga_verilog/verilog_tile.cpp +++ b/openfpga/src/fpga_verilog/verilog_tile.cpp @@ -60,6 +60,7 @@ static int print_verilog_tile_module_netlist( /* Write the module content in Verilog format */ write_verilog_module_to_file(fp, module_manager, tile_module, options.explicit_port_mapping(), + options.constant_undriven_inputs(), options.default_net_type()); /* Add an empty line as a splitter */ diff --git a/openfpga/src/fpga_verilog/verilog_top_module.cpp b/openfpga/src/fpga_verilog/verilog_top_module.cpp index b8c302f21..60ed91956 100644 --- a/openfpga/src/fpga_verilog/verilog_top_module.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_module.cpp @@ -63,6 +63,7 @@ void print_verilog_core_module(NetlistManager& netlist_manager, /* Write the module content in Verilog format */ write_verilog_module_to_file(fp, module_manager, core_module, options.explicit_port_mapping(), + options.constant_undriven_inputs(), options.default_net_type()); /* Add an empty line as a splitter */ @@ -129,6 +130,7 @@ void print_verilog_top_module(NetlistManager& netlist_manager, /* Write the module content in Verilog format */ write_verilog_module_to_file(fp, module_manager, top_module, options.explicit_port_mapping(), + options.constant_undriven_inputs(), options.default_net_type()); /* Add an empty line as a splitter */ From 72ee39f178dcc583dcc4776c48ecb0bf2fbf27b9 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 4 Jul 2024 20:39:02 -0700 Subject: [PATCH 25/91] [core] add new command line option 'constant_undriven_inputs' --- openfpga/src/base/openfpga_verilog_command_template.h | 4 ++++ openfpga/src/base/openfpga_verilog_template.h | 11 +++++++++++ 2 files changed, 15 insertions(+) diff --git a/openfpga/src/base/openfpga_verilog_command_template.h b/openfpga/src/base/openfpga_verilog_command_template.h index 5fa7d6171..2cd03278e 100644 --- a/openfpga/src/base/openfpga_verilog_command_template.h +++ b/openfpga/src/base/openfpga_verilog_command_template.h @@ -30,6 +30,10 @@ ShellCommandId add_write_fabric_verilog_command_template( shell_cmd.set_option_short_name(output_opt, "f"); shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING); + /* Add an option '--constant_undriven_inputs' */ + shell_cmd.add_option("constant_undriven_inputs", false, + "Use constant gnd for undriven wires in Verilog netlists. Recommand to enable when there are boundary routing tracks in FPGA fabric"); + /* Add an option '--explicit_port_mapping' */ shell_cmd.add_option("explicit_port_mapping", false, "Use explicit port mapping in Verilog netlists"); diff --git a/openfpga/src/base/openfpga_verilog_template.h b/openfpga/src/base/openfpga_verilog_template.h index 2c9656eaa..53893fe62 100644 --- a/openfpga/src/base/openfpga_verilog_template.h +++ b/openfpga/src/base/openfpga_verilog_template.h @@ -28,6 +28,8 @@ int write_fabric_verilog_template(T& openfpga_ctx, const Command& cmd, CommandOptionId opt_output_dir = cmd.option("file"); CommandOptionId opt_explicit_port_mapping = cmd.option("explicit_port_mapping"); + CommandOptionId opt_constant_undriven_inputs = + cmd.option("constant_undriven_inputs"); CommandOptionId opt_include_timing = cmd.option("include_timing"); CommandOptionId opt_print_user_defined_template = cmd.option("print_user_defined_template"); @@ -56,6 +58,15 @@ int write_fabric_verilog_template(T& openfpga_ctx, const Command& cmd, } options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose)); options.set_compress_routing(openfpga_ctx.flow_manager().compress_routing()); + /* For perimeter cb, enable the constant undriven inputs, unless it is off by user */ + if (g_vpr_ctx.device().arch->perimeter_cb) { + options.set_constant_undriven_inputs(true); + VTR_LOG("Automatically enable the constant_undriven_input option as perimeter connection blocks are seen in FPGA fabric\n"); + if (!cmd_context.option_enable(cmd, opt_constant_undriven_inputs)) { + VTR_LOG("User forces to disable the constant_undriven_input option even when perimeter connection blocks are enabled\n"); + } + } + options.set_constant_undriven_inputs(cmd_context.option_enable(cmd, opt_constant_undriven_inputs)); return fpga_fabric_verilog( openfpga_ctx.mutable_module_graph(), From 1f8c2436efbb91b188adedb1dd0ddfcd39f13a40 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 4 Jul 2024 20:46:38 -0700 Subject: [PATCH 26/91] [core] now constant_undriven_inputs are force to enable when perimeter_cb is selected --- openfpga/src/base/openfpga_verilog_template.h | 6 ++---- openfpga/src/fpga_verilog/verilog_module_writer.cpp | 3 +-- 2 files changed, 3 insertions(+), 6 deletions(-) diff --git a/openfpga/src/base/openfpga_verilog_template.h b/openfpga/src/base/openfpga_verilog_template.h index 53893fe62..19109ce21 100644 --- a/openfpga/src/base/openfpga_verilog_template.h +++ b/openfpga/src/base/openfpga_verilog_template.h @@ -62,11 +62,9 @@ int write_fabric_verilog_template(T& openfpga_ctx, const Command& cmd, if (g_vpr_ctx.device().arch->perimeter_cb) { options.set_constant_undriven_inputs(true); VTR_LOG("Automatically enable the constant_undriven_input option as perimeter connection blocks are seen in FPGA fabric\n"); - if (!cmd_context.option_enable(cmd, opt_constant_undriven_inputs)) { - VTR_LOG("User forces to disable the constant_undriven_input option even when perimeter connection blocks are enabled\n"); - } + } else { + options.set_constant_undriven_inputs(cmd_context.option_enable(cmd, opt_constant_undriven_inputs)); } - options.set_constant_undriven_inputs(cmd_context.option_enable(cmd, opt_constant_undriven_inputs)); return fpga_fabric_verilog( openfpga_ctx.mutable_module_graph(), diff --git a/openfpga/src/fpga_verilog/verilog_module_writer.cpp b/openfpga/src/fpga_verilog/verilog_module_writer.cpp index 1c5ce17ad..3b52c2d87 100644 --- a/openfpga/src/fpga_verilog/verilog_module_writer.cpp +++ b/openfpga/src/fpga_verilog/verilog_module_writer.cpp @@ -619,8 +619,7 @@ void write_verilog_module_to_file( for (std::pair> port_group : local_undriven_wires) { for (const BasicPort& local_undriven_wire : port_group.second) { - fp << generate_verilog_port_constant_values(local_undriven_wire, std::vector(local_undriven_wire.get_width(), 0), false) << ";" - << std::endl; + print_verilog_wire_constant_values(fp, local_undriven_wire, std::vector(local_undriven_wire.get_width(), 0)); } } } From 5865aebf93c03c108ff61321a3000f8814a77245 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 4 Jul 2024 21:12:26 -0700 Subject: [PATCH 27/91] [test] add new arch --- ...N4_tileable_IoSubtile_PerimeterCb_40nm.xml | 345 ++++++++++++++++++ 1 file changed, 345 insertions(+) create mode 100644 openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml new file mode 100644 index 000000000..ee4d3cf11 --- /dev/null +++ b/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml @@ -0,0 +1,345 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + fpga_input_center[1:0].inpad + fpga_input_center[3:2].inpad + fpga_input_center[4:4].inpad + fpga_input_center[5:5].inpad + + + + + + + + + + fpga_output_center[1:0].outpad + + fpga_output_center[3:2].outpad + + + + + + + + + + + + + fpga_input[0:0].inpad + + fpga_input[1:1].inpad + fpga_input[2:3].inpad + + + + + + + + + + + + fpga_output[0:0].outpad + fpga_output[1:1].outpad + + + + + + + + + + + + fpga_input[0:0].inpad + + fpga_input[1:1].inpad + fpga_input[2:3].inpad + + + + + + + + + + + + fpga_output[0:0].outpad + fpga_output[1:1].outpad + + + + + + + + + + + + + + fpga_input.inpad + + + + + + + + + + + + + fpga_output.outpad + + + + + + + + + + + + + + fpga_input[0:1].inpad + fpga_input[2:3].inpad + + + + + + + + + + + + fpga_output[0:0].outpad + fpga_output[1:1].outpad + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From 4064c29d495016db9367b91584abf0540a2cd283 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 4 Jul 2024 21:23:15 -0700 Subject: [PATCH 28/91] [test] updating arch for perimeter cb --- ...N4_tileable_IoSubtile_PerimeterCb_40nm.xml | 30 +++++++++---------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml index ee4d3cf11..1af2645f1 100644 --- a/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml +++ b/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml @@ -65,10 +65,10 @@ - fpga_input[0:0].inpad + - fpga_input[1:1].inpad - fpga_input[2:3].inpad + + fpga_input[0:3].inpad @@ -80,8 +80,8 @@ - fpga_output[0:0].outpad - fpga_output[1:1].outpad + + fpga_output[0:1].outpad @@ -93,10 +93,10 @@ - fpga_input[0:0].inpad + fpga_input[0:3].inpad - fpga_input[1:1].inpad - fpga_input[2:3].inpad + + @@ -106,10 +106,10 @@ - + fpga_output[0:1].outpad - fpga_output[0:0].outpad - fpga_output[1:1].outpad + + @@ -150,8 +150,8 @@ - fpga_input[0:1].inpad - fpga_input[2:3].inpad + fpga_input[0:3].inpad + @@ -163,8 +163,8 @@ - fpga_output[0:0].outpad - fpga_output[1:1].outpad + fpga_output[0:1].outpad + From fe73e03c690b59d9f2b0c7bd679c57d614adfdc5 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 4 Jul 2024 21:31:43 -0700 Subject: [PATCH 29/91] [test] changing arch --- ...k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml index 1af2645f1..11b4d4d4e 100644 --- a/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml +++ b/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml @@ -67,8 +67,8 @@ - - fpga_input[0:3].inpad + fpga_input[0:1].inpad + fpga_input[2:3].inpad @@ -80,8 +80,8 @@ - - fpga_output[0:1].outpad + fpga_output[0:0].outpad + fpga_output[1:1].outpad @@ -150,9 +150,9 @@ - fpga_input[0:3].inpad + fpga_input[0:1].inpad - + fpga_input[2:3].inpad @@ -163,9 +163,9 @@ - fpga_output[0:1].outpad + fpga_output[0:0].outpad - + fpga_output[1:1].outpad From 47ba57a27c9d4ce697a7def4f1b51c48f3ef9af7 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 5 Jul 2024 10:16:50 -0700 Subject: [PATCH 30/91] [lib] update vtr --- vtr-verilog-to-routing | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index 589b6bcd8..ba0576d43 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit 589b6bcd8bd37ac445c55239af02c757223f5d4f +Subproject commit ba0576d43d1a019ff76d350b01332f0cc7bd32e3 From 266c2686d46154bed603d048d5b73942721fe9be Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 5 Jul 2024 10:32:33 -0700 Subject: [PATCH 31/91] [core] adapt new gsb coordinate system --- openfpga/src/annotation/annotate_rr_graph.cpp | 64 ++++++++++--------- 1 file changed, 34 insertions(+), 30 deletions(-) diff --git a/openfpga/src/annotation/annotate_rr_graph.cpp b/openfpga/src/annotation/annotate_rr_graph.cpp index badeca9de..8c721c5d0 100644 --- a/openfpga/src/annotation/annotate_rr_graph.cpp +++ b/openfpga/src/annotation/annotate_rr_graph.cpp @@ -98,7 +98,32 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, const vtr::Point& gsb_range, const size_t& layer, const vtr::Point& gsb_coord, + const bool& perimeter_cb, const bool& include_clock) { + /* Bounding box for GSB ranges on routing tracks. + * Note that when perimeter connection blocks are not allowed, + * - top side routing tracks for any GSB exist on y = [0, H-2) + * - right side routing tracks for any GSB exist on x = [0, W-2) + * - bottom side routing tracks for any GSB exist on y = [1, H-1) + * - left side routing tracks for any GSB exist on x = [1, W-1) + * Note that when perimeter connection blocks are allowed, + * - top side routing tracks for any GSB exist on y = [0, H-1) + * - right side routing tracks for any GSB exist on x = [0, W-1) + * - bottom side routing tracks for any GSB exist on y = [0, H) + * - left side routing tracks for any GSB exist on x = [0, W) + */ + std::map> track_range; + track_range[TOP] = vtr::Point(0, gsb_range.y(); + track_range[RIGHT] = vtr::Point(0, gsb_range.x()); + track_range[BOTTOM] = vtr::Point(1, gsb_range.y()); + track_range[LEFT] = vtr::Point(1, gsb_range.x()); + if (perimeter_cb) { + track_range[TOP] = vtr::Point(0, gsb_range.y() + 1); + track_range[RIGHT] = vtr::Point(0, gsb_range.x() + 1); + track_range[BOTTOM] = vtr::Point(0, gsb_range.y() + 2); + track_range[LEFT] = vtr::Point(0, gsb_range.x() + 2); + } + /* Create an object to return */ RRGSB rr_gsb; @@ -126,13 +151,7 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, switch (side) { case TOP: /* TOP = 0 */ - /* For the border, we should take special care - * For the fabric where no cbs are on perimeter tiles (y = H - 1), - * the the border should be on the y = H - 2 - * For the fabric where cbs are on perimeter tiles, - * the border should be on the y = H - 1 - */ - if (gsb_coord.y() == gsb_range.y()) { + if (track_range[side_manager.get_side()].x() > gsb_coordinate.y() || gsb_coordinate.y() >= track_range[side_manager.get_side()].y()) { rr_gsb.clear_one_side(side_manager.get_side()); break; } @@ -168,7 +187,7 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, * For the fabric where cbs are on perimeter tiles, * the border should be on the x = W - 1 */ - if (gsb_coord.x() == gsb_range.x()) { + if (track_range[side_manager.get_side()].x() > gsb_coordinate.x() || gsb_coordinate.x() >= track_range[side_manager.get_side()].y()) { rr_gsb.clear_one_side(side_manager.get_side()); break; } @@ -199,13 +218,7 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, gsb_coord.x() + 1, gsb_coord.y(), OPIN, opin_grid_side[1]); break; case BOTTOM: /* BOTTOM = 2*/ - /* For the border, we should take special care - * For the fabric where no cbs are on perimeter tiles (y = 0), - * the the border should be on the y = 0 - * For the fabric where cbs are on perimeter tiles, - * the border should be on the y = - 1, leading to no border - */ - if (!vpr_device_ctx.arch->perimeter_cb && gsb_coord.y() == 0) { + if (track_range[side_manager.get_side()].x() > gsb_coordinate.y() || gsb_coordinate.y() >= track_range[side_manager.get_side()].y()) { rr_gsb.clear_one_side(side_manager.get_side()); break; } @@ -235,13 +248,7 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, gsb_coord.y(), OPIN, opin_grid_side[1]); break; case LEFT: /* LEFT = 3 */ - /* For the border, we should take special care - * For the fabric where no cbs are on perimeter tiles (x = 0), - * the the border should be on the x = 0 - * For the fabric where cbs are on perimeter tiles, - * the border should be on the x = - 1, leading to no border - */ - if (!vpr_device_ctx.arch->perimeter_cb && gsb_coord.x() == 0) { + if (track_range[side_manager.get_side()].x() > gsb_coordinate.y() || gsb_coordinate.y() >= track_range[side_manager.get_side()].y()) { rr_gsb.clear_one_side(side_manager.get_side()); break; } @@ -355,9 +362,9 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, /* Check if TOP side chan width is 0 or not */ chan_side = TOP; /* Build the connection block: ipin and ipin_grid_side */ - /* LEFT side INPUT Pins of Grid[x+1][y+1] */ + /* LEFT side INPUT Pins of Grid[x+1][y] */ ix = rr_gsb.get_sb_x() + 1; - iy = rr_gsb.get_sb_y() + 1; + iy = rr_gsb.get_sb_y(); ipin_rr_node_grid_side = LEFT; break; case BOTTOM: /* BOTTOM = 2*/ @@ -375,9 +382,9 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, /* Check if left side chan width is 0 or not */ chan_side = TOP; /* Build the connection block: ipin and ipin_grid_side */ - /* RIGHT side INPUT Pins of Grid[x][y+1] */ + /* RIGHT side INPUT Pins of Grid[x][y] */ ix = rr_gsb.get_sb_x(); - iy = rr_gsb.get_sb_y() + 1; + iy = rr_gsb.get_sb_y(); ipin_rr_node_grid_side = RIGHT; break; default: @@ -459,13 +466,10 @@ void annotate_device_rr_gsb(const DeviceContext& vpr_device_ctx, */ vtr::Point sub_gsb_range(vpr_device_ctx.grid.width() - 2, vpr_device_ctx.grid.height() - 2); - if (vpr_device_ctx.arch->perimeter_cb) { - sub_gsb_range.set(vpr_device_ctx.grid.width() - 1, vpr_device_ctx.grid.height() - 1); - } const RRGSB& rr_gsb = build_rr_gsb(vpr_device_ctx, sub_gsb_range, - layer, vtr::Point(ix, iy), include_clock); + layer, vtr::Point(ix, iy), perimeter_cb, include_clock); /* Add to device_rr_gsb */ vtr::Point gsb_coordinate = rr_gsb.get_sb_coordinate(); device_rr_gsb.add_rr_gsb(gsb_coordinate, rr_gsb); From 1dc602a849468439118006783f26a90a53663f5d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 5 Jul 2024 10:38:26 -0700 Subject: [PATCH 32/91] [core] syntax --- openfpga/src/annotation/annotate_rr_graph.cpp | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/openfpga/src/annotation/annotate_rr_graph.cpp b/openfpga/src/annotation/annotate_rr_graph.cpp index 8c721c5d0..b811b3521 100644 --- a/openfpga/src/annotation/annotate_rr_graph.cpp +++ b/openfpga/src/annotation/annotate_rr_graph.cpp @@ -113,7 +113,7 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, * - left side routing tracks for any GSB exist on x = [0, W) */ std::map> track_range; - track_range[TOP] = vtr::Point(0, gsb_range.y(); + track_range[TOP] = vtr::Point(0, gsb_range.y()); track_range[RIGHT] = vtr::Point(0, gsb_range.x()); track_range[BOTTOM] = vtr::Point(1, gsb_range.y()); track_range[LEFT] = vtr::Point(1, gsb_range.x()); @@ -151,7 +151,7 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, switch (side) { case TOP: /* TOP = 0 */ - if (track_range[side_manager.get_side()].x() > gsb_coordinate.y() || gsb_coordinate.y() >= track_range[side_manager.get_side()].y()) { + if (track_range[side_manager.get_side()].x() > gsb_coord.y() || gsb_coord.y() >= track_range[side_manager.get_side()].y()) { rr_gsb.clear_one_side(side_manager.get_side()); break; } @@ -187,7 +187,7 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, * For the fabric where cbs are on perimeter tiles, * the border should be on the x = W - 1 */ - if (track_range[side_manager.get_side()].x() > gsb_coordinate.x() || gsb_coordinate.x() >= track_range[side_manager.get_side()].y()) { + if (track_range[side_manager.get_side()].x() > gsb_coord.x() || gsb_coord.x() >= track_range[side_manager.get_side()].y()) { rr_gsb.clear_one_side(side_manager.get_side()); break; } @@ -218,7 +218,7 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, gsb_coord.x() + 1, gsb_coord.y(), OPIN, opin_grid_side[1]); break; case BOTTOM: /* BOTTOM = 2*/ - if (track_range[side_manager.get_side()].x() > gsb_coordinate.y() || gsb_coordinate.y() >= track_range[side_manager.get_side()].y()) { + if (track_range[side_manager.get_side()].x() > gsb_coord.y() || gsb_coord.y() >= track_range[side_manager.get_side()].y()) { rr_gsb.clear_one_side(side_manager.get_side()); break; } @@ -248,7 +248,7 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, gsb_coord.y(), OPIN, opin_grid_side[1]); break; case LEFT: /* LEFT = 3 */ - if (track_range[side_manager.get_side()].x() > gsb_coordinate.y() || gsb_coordinate.y() >= track_range[side_manager.get_side()].y()) { + if (track_range[side_manager.get_side()].x() > gsb_coord.y() || gsb_coord.y() >= track_range[side_manager.get_side()].y()) { rr_gsb.clear_one_side(side_manager.get_side()); break; } @@ -469,7 +469,7 @@ void annotate_device_rr_gsb(const DeviceContext& vpr_device_ctx, const RRGSB& rr_gsb = build_rr_gsb(vpr_device_ctx, sub_gsb_range, - layer, vtr::Point(ix, iy), perimeter_cb, include_clock); + layer, vtr::Point(ix, iy), vpr_device_ctx.arch->perimeter_cb, include_clock); /* Add to device_rr_gsb */ vtr::Point gsb_coordinate = rr_gsb.get_sb_coordinate(); device_rr_gsb.add_rr_gsb(gsb_coordinate, rr_gsb); From b6e89b8943a09975cfb3084e2820aa806bcffae3 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 5 Jul 2024 10:52:35 -0700 Subject: [PATCH 33/91] [lib] update vtr --- vtr-verilog-to-routing | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index ba0576d43..826a10be4 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit ba0576d43d1a019ff76d350b01332f0cc7bd32e3 +Subproject commit 826a10be4e6e45976f64ea3a0f6503516a8d777d From ba1482f53335c676eac64b669b1a41075ebe1c5f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 5 Jul 2024 11:01:31 -0700 Subject: [PATCH 34/91] [lib] update vtr --- vtr-verilog-to-routing | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index 826a10be4..b06f2ee34 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit 826a10be4e6e45976f64ea3a0f6503516a8d777d +Subproject commit b06f2ee34036a8c981a2c202ec06251c1bb2b81a From f6adca15452405bcbb63adcfae4315ead242cd12 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 5 Jul 2024 11:02:01 -0700 Subject: [PATCH 35/91] [core] fixed a bug --- openfpga/src/annotation/annotate_rr_graph.cpp | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/openfpga/src/annotation/annotate_rr_graph.cpp b/openfpga/src/annotation/annotate_rr_graph.cpp index b811b3521..d0833ae19 100644 --- a/openfpga/src/annotation/annotate_rr_graph.cpp +++ b/openfpga/src/annotation/annotate_rr_graph.cpp @@ -151,7 +151,7 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, switch (side) { case TOP: /* TOP = 0 */ - if (track_range[side_manager.get_side()].x() > gsb_coord.y() || gsb_coord.y() >= track_range[side_manager.get_side()].y()) { + if (track_range[side_manager.get_side()].x() > gsb_coord.y() || gsb_coord.y() > track_range[side_manager.get_side()].y()) { rr_gsb.clear_one_side(side_manager.get_side()); break; } @@ -187,7 +187,7 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, * For the fabric where cbs are on perimeter tiles, * the border should be on the x = W - 1 */ - if (track_range[side_manager.get_side()].x() > gsb_coord.x() || gsb_coord.x() >= track_range[side_manager.get_side()].y()) { + if (track_range[side_manager.get_side()].x() > gsb_coord.x() || gsb_coord.x() > track_range[side_manager.get_side()].y()) { rr_gsb.clear_one_side(side_manager.get_side()); break; } @@ -218,7 +218,7 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, gsb_coord.x() + 1, gsb_coord.y(), OPIN, opin_grid_side[1]); break; case BOTTOM: /* BOTTOM = 2*/ - if (track_range[side_manager.get_side()].x() > gsb_coord.y() || gsb_coord.y() >= track_range[side_manager.get_side()].y()) { + if (track_range[side_manager.get_side()].x() > gsb_coord.y() || gsb_coord.y() > track_range[side_manager.get_side()].y()) { rr_gsb.clear_one_side(side_manager.get_side()); break; } @@ -248,7 +248,7 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, gsb_coord.y(), OPIN, opin_grid_side[1]); break; case LEFT: /* LEFT = 3 */ - if (track_range[side_manager.get_side()].x() > gsb_coord.y() || gsb_coord.y() >= track_range[side_manager.get_side()].y()) { + if (track_range[side_manager.get_side()].x() > gsb_coord.y() || gsb_coord.y() > track_range[side_manager.get_side()].y()) { rr_gsb.clear_one_side(side_manager.get_side()); break; } From fdbc427f70aea0cd1bfe98e4be8e70edc2b931ea Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 5 Jul 2024 11:17:05 -0700 Subject: [PATCH 36/91] [core] debug --- openfpga/src/annotation/annotate_rr_graph.cpp | 8 ++++---- vtr-verilog-to-routing | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/openfpga/src/annotation/annotate_rr_graph.cpp b/openfpga/src/annotation/annotate_rr_graph.cpp index d0833ae19..78ff7c356 100644 --- a/openfpga/src/annotation/annotate_rr_graph.cpp +++ b/openfpga/src/annotation/annotate_rr_graph.cpp @@ -115,13 +115,13 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, std::map> track_range; track_range[TOP] = vtr::Point(0, gsb_range.y()); track_range[RIGHT] = vtr::Point(0, gsb_range.x()); - track_range[BOTTOM] = vtr::Point(1, gsb_range.y()); - track_range[LEFT] = vtr::Point(1, gsb_range.x()); + track_range[BOTTOM] = vtr::Point(0, gsb_range.y()); + track_range[LEFT] = vtr::Point(0, gsb_range.x()); if (perimeter_cb) { track_range[TOP] = vtr::Point(0, gsb_range.y() + 1); track_range[RIGHT] = vtr::Point(0, gsb_range.x() + 1); - track_range[BOTTOM] = vtr::Point(0, gsb_range.y() + 2); - track_range[LEFT] = vtr::Point(0, gsb_range.x() + 2); + track_range[BOTTOM] = vtr::Point(0, gsb_range.y() + 1); + track_range[LEFT] = vtr::Point(0, gsb_range.x() + 1); } /* Create an object to return */ diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index b06f2ee34..de0d0bc21 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit b06f2ee34036a8c981a2c202ec06251c1bb2b81a +Subproject commit de0d0bc214419cae53c10e6a1349d4ae251625f8 From e5d75cc51e92a78875f0271cab07a90596230886 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 5 Jul 2024 11:47:04 -0700 Subject: [PATCH 37/91] [lib] update vtr --- vtr-verilog-to-routing | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index de0d0bc21..0a1bc20b0 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit de0d0bc214419cae53c10e6a1349d4ae251625f8 +Subproject commit 0a1bc20b08da6ad0d0fbf5fe9e931b1bbdac09a1 From 46e3b4b0712a2de61346b6812190ee549a42d6d7 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 5 Jul 2024 11:50:41 -0700 Subject: [PATCH 38/91] [core] debug --- openfpga/src/annotation/annotate_rr_graph.cpp | 42 +++---------------- 1 file changed, 6 insertions(+), 36 deletions(-) diff --git a/openfpga/src/annotation/annotate_rr_graph.cpp b/openfpga/src/annotation/annotate_rr_graph.cpp index 78ff7c356..915dae2fd 100644 --- a/openfpga/src/annotation/annotate_rr_graph.cpp +++ b/openfpga/src/annotation/annotate_rr_graph.cpp @@ -100,30 +100,6 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, const vtr::Point& gsb_coord, const bool& perimeter_cb, const bool& include_clock) { - /* Bounding box for GSB ranges on routing tracks. - * Note that when perimeter connection blocks are not allowed, - * - top side routing tracks for any GSB exist on y = [0, H-2) - * - right side routing tracks for any GSB exist on x = [0, W-2) - * - bottom side routing tracks for any GSB exist on y = [1, H-1) - * - left side routing tracks for any GSB exist on x = [1, W-1) - * Note that when perimeter connection blocks are allowed, - * - top side routing tracks for any GSB exist on y = [0, H-1) - * - right side routing tracks for any GSB exist on x = [0, W-1) - * - bottom side routing tracks for any GSB exist on y = [0, H) - * - left side routing tracks for any GSB exist on x = [0, W) - */ - std::map> track_range; - track_range[TOP] = vtr::Point(0, gsb_range.y()); - track_range[RIGHT] = vtr::Point(0, gsb_range.x()); - track_range[BOTTOM] = vtr::Point(0, gsb_range.y()); - track_range[LEFT] = vtr::Point(0, gsb_range.x()); - if (perimeter_cb) { - track_range[TOP] = vtr::Point(0, gsb_range.y() + 1); - track_range[RIGHT] = vtr::Point(0, gsb_range.x() + 1); - track_range[BOTTOM] = vtr::Point(0, gsb_range.y() + 1); - track_range[LEFT] = vtr::Point(0, gsb_range.x() + 1); - } - /* Create an object to return */ RRGSB rr_gsb; @@ -151,7 +127,7 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, switch (side) { case TOP: /* TOP = 0 */ - if (track_range[side_manager.get_side()].x() > gsb_coord.y() || gsb_coord.y() > track_range[side_manager.get_side()].y()) { + if (gsb_coord.y() == gsb_range.y()) { rr_gsb.clear_one_side(side_manager.get_side()); break; } @@ -181,13 +157,7 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, break; case RIGHT: /* RIGHT = 1 */ - /* For the border, we should take special care - * For the fabric where no cbs are on perimeter tiles (x = W - 1), - * the the border should be on the x = W - 2 - * For the fabric where cbs are on perimeter tiles, - * the border should be on the x = W - 1 - */ - if (track_range[side_manager.get_side()].x() > gsb_coord.x() || gsb_coord.x() > track_range[side_manager.get_side()].y()) { + if (gsb_coord.x() == gsb_range.x()) { rr_gsb.clear_one_side(side_manager.get_side()); break; } @@ -218,7 +188,7 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, gsb_coord.x() + 1, gsb_coord.y(), OPIN, opin_grid_side[1]); break; case BOTTOM: /* BOTTOM = 2*/ - if (track_range[side_manager.get_side()].x() > gsb_coord.y() || gsb_coord.y() > track_range[side_manager.get_side()].y()) { + if (!perimeter_cb && gsb_coord.y() == 0) { rr_gsb.clear_one_side(side_manager.get_side()); break; } @@ -248,7 +218,7 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, gsb_coord.y(), OPIN, opin_grid_side[1]); break; case LEFT: /* LEFT = 3 */ - if (track_range[side_manager.get_side()].x() > gsb_coord.y() || gsb_coord.y() > track_range[side_manager.get_side()].y()) { + if (!perimeter_cb && gsb_coord.x() == 0) { rr_gsb.clear_one_side(side_manager.get_side()); break; } @@ -464,8 +434,8 @@ void annotate_device_rr_gsb(const DeviceContext& vpr_device_ctx, * the GSBs at the borderside correctly sort drive_rr_nodes should be * called if required by users */ - vtr::Point sub_gsb_range(vpr_device_ctx.grid.width() - 2, - vpr_device_ctx.grid.height() - 2); + vtr::Point sub_gsb_range(vpr_device_ctx.grid.width() - 1, + vpr_device_ctx.grid.height() - 1); const RRGSB& rr_gsb = build_rr_gsb(vpr_device_ctx, sub_gsb_range, From 36c0cfe645007479436591cfab0455dead961cb8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 5 Jul 2024 12:14:14 -0700 Subject: [PATCH 39/91] [lib] update vtr --- vtr-verilog-to-routing | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index 0a1bc20b0..4da28ffbc 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit 0a1bc20b08da6ad0d0fbf5fe9e931b1bbdac09a1 +Subproject commit 4da28ffbccf4eb2b31a57ec36a3c135225ef40f9 From f2506598a98feadbec3c8d676d4482ea44280fe7 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 5 Jul 2024 12:20:49 -0700 Subject: [PATCH 40/91] [lib] update vtr --- vtr-verilog-to-routing | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index 4da28ffbc..c71c3b9d3 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit 4da28ffbccf4eb2b31a57ec36a3c135225ef40f9 +Subproject commit c71c3b9d3a1a17b6865511b29e5d2e14f5e9fe15 From 283aa3a1c9fea01cf1952a82da59612ed6e45c0c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 5 Jul 2024 12:21:17 -0700 Subject: [PATCH 41/91] [core] debug --- openfpga/src/annotation/annotate_rr_graph.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openfpga/src/annotation/annotate_rr_graph.cpp b/openfpga/src/annotation/annotate_rr_graph.cpp index 915dae2fd..a1ad9c24c 100644 --- a/openfpga/src/annotation/annotate_rr_graph.cpp +++ b/openfpga/src/annotation/annotate_rr_graph.cpp @@ -330,7 +330,7 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, case RIGHT: /* RIGHT = 1 */ /* For the bording, we should take special care */ /* Check if TOP side chan width is 0 or not */ - chan_side = TOP; + chan_side = BOTTOM; /* Build the connection block: ipin and ipin_grid_side */ /* LEFT side INPUT Pins of Grid[x+1][y] */ ix = rr_gsb.get_sb_x() + 1; @@ -350,7 +350,7 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, case LEFT: /* LEFT = 3 */ /* For the bording, we should take special care */ /* Check if left side chan width is 0 or not */ - chan_side = TOP; + chan_side = BOTTOM; /* Build the connection block: ipin and ipin_grid_side */ /* RIGHT side INPUT Pins of Grid[x][y] */ ix = rr_gsb.get_sb_x(); From a41f4371096633cca8782c34121b293dc4ae77af Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 5 Jul 2024 12:36:47 -0700 Subject: [PATCH 42/91] [core] now netlist look ok --- openfpga/src/fabric/build_top_module_connection.cpp | 6 +++--- openfpga/src/fabric/build_top_module_utils.cpp | 8 ++++---- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/openfpga/src/fabric/build_top_module_connection.cpp b/openfpga/src/fabric/build_top_module_connection.cpp index 2493c20c9..d5d4e7aea 100644 --- a/openfpga/src/fabric/build_top_module_connection.cpp +++ b/openfpga/src/fabric/build_top_module_connection.cpp @@ -753,17 +753,17 @@ static void add_top_module_nets_connect_sb_and_cb( * is_cb_exist() FOr RIGHT and BOTTOM side, find the adjacent RRGSB and then * use is_cb_exist() */ - if (TOP == side_manager.get_side() || LEFT == side_manager.get_side()) { + if (BOTTOM == side_manager.get_side() || LEFT == side_manager.get_side()) { if (false == rr_gsb.is_cb_exist(cb_type)) { continue; } } - if (RIGHT == side_manager.get_side() || BOTTOM == side_manager.get_side()) { + if (RIGHT == side_manager.get_side() || TOP == side_manager.get_side()) { /* Only for the condition where cbs are on perimeter, the neighbour cb will be invalid * Bypass in such case on finding neighbour cbs */ - if (BOTTOM == side_manager.get_side() && instance_sb_coordinate.y() == 0) { + if (TOP == side_manager.get_side() && instance_sb_coordinate.y() == device_rr_gsb.get_gsb_range().y()) { continue; } if (RIGHT == side_manager.get_side() && instance_sb_coordinate.x() == device_rr_gsb.get_gsb_range().x()) { diff --git a/openfpga/src/fabric/build_top_module_utils.cpp b/openfpga/src/fabric/build_top_module_utils.cpp index ebf52eb77..8b7c8f2e6 100644 --- a/openfpga/src/fabric/build_top_module_utils.cpp +++ b/openfpga/src/fabric/build_top_module_utils.cpp @@ -100,13 +100,13 @@ vtr::Point find_top_module_gsb_coordinate_by_sb_side( vtr::Point gsb_coordinate; - if ((TOP == sb_side) || (LEFT == sb_side)) { + if ((BOTTOM == sb_side) || (LEFT == sb_side)) { gsb_coordinate.set_x(rr_gsb.get_x()); gsb_coordinate.set_y(rr_gsb.get_y()); return gsb_coordinate; } - VTR_ASSERT((RIGHT == sb_side) || (BOTTOM == sb_side)); + VTR_ASSERT((RIGHT == sb_side) || (TOP == sb_side)); /* RIGHT side: x + 1 */ if (RIGHT == sb_side) { @@ -115,9 +115,9 @@ vtr::Point find_top_module_gsb_coordinate_by_sb_side( } /* BOTTOM side: y - 1 */ - if (BOTTOM == sb_side) { + if (TOP == sb_side) { gsb_coordinate.set_x(rr_gsb.get_x()); - gsb_coordinate.set_y(rr_gsb.get_y() - 1); + gsb_coordinate.set_y(rr_gsb.get_y() + 1); } return gsb_coordinate; From 5e89b950edc561e5b5b3e72f373abd3d62201c7b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 5 Jul 2024 13:41:38 -0700 Subject: [PATCH 43/91] [lib] update vtr --- vtr-verilog-to-routing | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index c71c3b9d3..d2be1c8b2 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit c71c3b9d3a1a17b6865511b29e5d2e14f5e9fe15 +Subproject commit d2be1c8b2629069479863826695ed317bf88618a From 46d916f0a056c9bdbfca4bab90eedb1fa8ba07f7 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 5 Jul 2024 16:59:08 -0700 Subject: [PATCH 44/91] [core] fixed the bugs in fabric tile build-up --- openfpga/src/fabric/build_fabric_tile.cpp | 261 +++++++++++++++------ openfpga/src/fabric/build_tile_modules.cpp | 4 +- 2 files changed, 186 insertions(+), 79 deletions(-) diff --git a/openfpga/src/fabric/build_fabric_tile.cpp b/openfpga/src/fabric/build_fabric_tile.cpp index a1e5f9460..c20c37537 100644 --- a/openfpga/src/fabric/build_fabric_tile.cpp +++ b/openfpga/src/fabric/build_fabric_tile.cpp @@ -22,12 +22,110 @@ namespace openfpga { /******************************************************************** - * Build tiles by following the top-level style. - * - The programmble block, e.g., clb, is placed on the top-left corner - * - The connection blocks and switch block are placed on the right and bottom - *sides + * With a given coordinate of a grid, find an existing fabric tile + * or create a new fabric tile + * - A grid may never exist in any fabric tile (no coordinate matches) + * Create a new one + * - A grid already in another fabric tile (occur in heterogeneous blocks) + * Find the existing one *******************************************************************/ -static int build_fabric_tile_style_top_left(FabricTile& fabric_tile, +static int find_or_create_one_fabric_tile_from_grid( + FabricTile& fabric_tile, + FabricTileId& curr_tile_id, + const DeviceGrid& grids, + const t_physical_tile_loc& tile_loc, + const RRGraphView& rr_graph, + const DeviceRRGSB& device_rr_gsb, + const bool& verbose) { + t_physical_tile_type_ptr phy_tile_type = + grids.get_physical_type(tile_loc); + vtr::Point curr_tile_coord(tile_loc.x, tile_loc.y); + vtr::Point curr_gsb_coord(tile_loc.x, tile_loc.y); + + bool skip_add_pb = false; + /* For EMPTY grid, routing blocks may still be required if there is a gsb + */ + if (true == is_empty_type(phy_tile_type)) { + skip_add_pb = true; + if (!device_rr_gsb.is_gsb_exist(rr_graph, curr_gsb_coord)) { + VTR_LOGV(verbose, "Skip tile[%lu][%lu] as it is empty\n", + curr_tile_coord.x(), curr_tile_coord.y()); + return CMD_EXEC_SUCCESS; + } + /* Need to create a new tile here */ + VTR_LOGV(verbose, + "Create tile[%lu][%lu] which only has routing but not a " + "programmable block\n", + curr_tile_coord.x(), curr_tile_coord.y()); + curr_tile_id = fabric_tile.create_tile(curr_tile_coord); + } else if ((0 < grids.get_width_offset(tile_loc)) || + (0 < grids.get_height_offset(tile_loc))) { + /* Skip width, height > 1 tiles (mostly heterogeneous blocks) */ + /* Find the root of this grid, the instance id should be valid. + * We just copy it here + */ + vtr::Point root_tile_coord( + curr_tile_coord.x() - grids.get_width_offset(tile_loc), + curr_tile_coord.y() - grids.get_height_offset(tile_loc)); + skip_add_pb = true; + VTR_LOGV(verbose, + "Tile[%lu][%lu] contains a heterogeneous block which is " + "rooted from tile[%lu][%lu]\n", + curr_tile_coord.x(), curr_tile_coord.y(), root_tile_coord.x(), + root_tile_coord.y()); + curr_tile_id = fabric_tile.find_tile(root_tile_coord); + /* Update the coordinates of the pb in tiles */ + size_t root_pb_idx_in_curr_tile = + fabric_tile.find_pb_index_in_tile(curr_tile_id, root_tile_coord); + int status_code = fabric_tile.set_pb_max_coordinate( + curr_tile_id, root_pb_idx_in_curr_tile, curr_tile_coord); + if (status_code != CMD_EXEC_SUCCESS) { + return CMD_EXEC_FATAL_ERROR; + } + } else { + /* Need to create a new tile here */ + VTR_LOGV(verbose, "Create a regular tile[%lu][%lu]\n", + curr_tile_coord.x(), curr_tile_coord.y()); + curr_tile_id = fabric_tile.create_tile(curr_tile_coord); + } + + /* Ensure that we have a valid id */ + if (!fabric_tile.valid_tile_id(curr_tile_id)) { + VTR_LOG_ERROR("Failed to get a valid id for tile[%lu][%lu]!\n", + curr_tile_coord.x(), curr_tile_coord.y()); + return CMD_EXEC_FATAL_ERROR; + } + + /* Add components: pb, cbx, cby, and sb if exists */ + if (!skip_add_pb) { + fabric_tile.add_pb_coordinate(curr_tile_id, curr_tile_coord, + curr_gsb_coord); + } + return CMD_EXEC_SUCCESS; +} + +/******************************************************************** + * Build tiles by following the bottom style. + * - The programmble block, e.g., clb, is placed on the bottom-left corner + * - The connection blocks and switch block are placed on the top and bottom + *sides + * This is exactly how GSB is organized. Just need to transfer data from one GSB + * The gsb coordinate is the same as the grid coordinate when the + * bottom-left style is considered + * + * ------------------------------ + * +----------+ +----------+ ^ + * | CBx | | SB | | + * | [x][y] | | [x][y] | GSB[x][y] + * +----------+ +----------+ | + * +----------+ +----------+ | + * | Grid | | CBy | | + * | [x][y] | | [x][y] | | + * +----------+ +----------+ v + * ------------------------------ + * + *******************************************************************/ +static int build_fabric_tile_style_bottom_left(FabricTile& fabric_tile, const DeviceGrid& grids, const size_t& layer, const RRGraphView& rr_graph, @@ -39,82 +137,16 @@ static int build_fabric_tile_style_top_left(FabricTile& fabric_tile, for (size_t ix = 0; ix < grids.width(); ++ix) { for (size_t iy = 0; iy < grids.height(); ++iy) { t_physical_tile_loc tile_loc(ix, iy, layer); - t_physical_tile_type_ptr phy_tile_type = - grids.get_physical_type(tile_loc); - bool skip_add_pb = false; - vtr::Point curr_tile_coord(ix, iy); - vtr::Point curr_gsb_coord(ix, iy - 1); FabricTileId curr_tile_id = FabricTileId::INVALID(); - /* For EMPTY grid, routing blocks may still be required if there is a gsb - */ - if (true == is_empty_type(phy_tile_type)) { - skip_add_pb = true; - if (!device_rr_gsb.is_gsb_exist(rr_graph, curr_gsb_coord)) { - VTR_LOGV(verbose, "Skip tile[%lu][%lu] as it is empty\n", - curr_tile_coord.x(), curr_tile_coord.y()); - continue; - } - /* Need to create a new tile here */ - VTR_LOGV(verbose, - "Create tile[%lu][%lu] which only has routing but not a " - "programmable block\n", - curr_tile_coord.x(), curr_tile_coord.y()); - curr_tile_id = fabric_tile.create_tile(curr_tile_coord); - } else if ((0 < grids.get_width_offset(tile_loc)) || - (0 < grids.get_height_offset(tile_loc))) { - /* Skip width, height > 1 tiles (mostly heterogeneous blocks) */ - /* Find the root of this grid, the instance id should be valid. - * We just copy it here - */ - vtr::Point root_tile_coord( - ix - grids.get_width_offset(tile_loc), - iy - grids.get_height_offset(tile_loc)); - skip_add_pb = true; - VTR_LOGV(verbose, - "Tile[%lu][%lu] contains a heterogeneous block which is " - "rooted from tile[%lu][%lu]\n", - curr_tile_coord.x(), curr_tile_coord.y(), root_tile_coord.x(), - root_tile_coord.y()); - curr_tile_id = fabric_tile.find_tile(root_tile_coord); - /* Update the coordinates of the pb in tiles */ - size_t root_pb_idx_in_curr_tile = - fabric_tile.find_pb_index_in_tile(curr_tile_id, root_tile_coord); - status_code = fabric_tile.set_pb_max_coordinate( - curr_tile_id, root_pb_idx_in_curr_tile, vtr::Point(ix, iy)); - if (status_code != CMD_EXEC_SUCCESS) { - return CMD_EXEC_FATAL_ERROR; - } - } else { - /* Need to create a new tile here */ - VTR_LOGV(verbose, "Create a regular tile[%lu][%lu]\n", - curr_tile_coord.x(), curr_tile_coord.y()); - curr_tile_id = fabric_tile.create_tile(curr_tile_coord); - } - - /* Ensure that we have a valid id */ - if (!fabric_tile.valid_tile_id(curr_tile_id)) { - VTR_LOG_ERROR("Failed to get a valid id for tile[%lu][%lu]!\n", ix, iy); + status_code = find_or_create_one_fabric_tile_from_grid(fabric_tile, curr_tile_id, grids, tile_loc, rr_graph, device_rr_gsb, verbose); + if (status_code != CMD_EXEC_SUCCESS) { return CMD_EXEC_FATAL_ERROR; } - - /* Add components: pb, cbx, cby, and sb if exists */ - if (!skip_add_pb) { - fabric_tile.add_pb_coordinate(curr_tile_id, curr_tile_coord, - curr_gsb_coord); + /* If no valid tile is created or spotted, the tile does not exist physically, skip */ + if (fabric_tile.valid_tile_id(curr_tile_id)) { + continue; } - /* The gsb coordinate is different than the grid coordinate when the - * top-left style is considered - * - * +----------+ +----------+ - * | Grid | | CBx | - * | [x][y] | | [x][y] | - * +----------+ +----------+ - * +----------+ +----------+ - * | CBy | | SB | - * | [x][y-1] | | [x][y-1] | - * +----------+ +----------+ - * - */ + vtr::Point curr_gsb_coord(ix, iy); if (!device_rr_gsb.is_gsb_exist(rr_graph, curr_gsb_coord)) { continue; } @@ -135,6 +167,77 @@ static int build_fabric_tile_style_top_left(FabricTile& fabric_tile, return status_code; } + +/******************************************************************** + * Build tiles by following the top-left style. + * - The programmble block, e.g., clb, is placed on the top-left corner + * - The connection blocks and switch block are placed on the right and bottom + *sides + * Tile[x][y] + * ------------------------------ + * +----------+ +----------+ ^ + * | Grid | | CBy | GSB[x][y] + * | [x][y] | | [x][y] | | + * +----------+ +----------+ v + * ------------------------------ + * +----------+ +----------+ ^ + * | CBx | | SB | | + * | [x][y-1] | | [x][y-1] | GSB[x][y-1] + * +----------+ +----------+ | + * ------------------------------ + + *******************************************************************/ +static int build_fabric_tile_style_top_left(FabricTile& fabric_tile, + const DeviceGrid& grids, + const size_t& layer, + const RRGraphView& rr_graph, + const DeviceRRGSB& device_rr_gsb, + const bool& verbose) { + int status_code = CMD_EXEC_SUCCESS; + + /* Walk through all the device rr_gsb and create tile one by one */ + for (size_t ix = 0; ix < grids.width(); ++ix) { + for (size_t iy = 0; iy < grids.height(); ++iy) { + t_physical_tile_loc tile_loc(ix, iy, layer); + FabricTileId curr_tile_id = FabricTileId::INVALID(); + status_code = find_or_create_one_fabric_tile_from_grid(fabric_tile, curr_tile_id, grids, tile_loc, rr_graph, device_rr_gsb, verbose); + if (status_code != CMD_EXEC_SUCCESS) { + return CMD_EXEC_FATAL_ERROR; + } + /* If no valid tile is created or spotted, the tile does not exist physically, skip */ + if (fabric_tile.valid_tile_id(curr_tile_id)) { + continue; + } + /* For the cby in the same gsb */ + vtr::Point curr_gsb_coord(ix, iy); + if (!device_rr_gsb.is_gsb_exist(rr_graph, curr_gsb_coord)) { + continue; + } + const RRGSB& curr_rr_gsb = device_rr_gsb.get_gsb(curr_gsb_coord); + if (curr_rr_gsb.is_cb_exist(CHANY)) { + fabric_tile.add_cb_coordinate(curr_tile_id, CHANY, + curr_rr_gsb.get_sb_coordinate()); + } + /* For the cbx and sb in the neighbour gsb */ + vtr::Point neighbor_gsb_coord(ix, iy - 1); + if (!device_rr_gsb.is_gsb_exist(rr_graph, neighbor_gsb_coord)) { + continue; + } + const RRGSB& neighbor_rr_gsb = device_rr_gsb.get_gsb(neighbor_gsb_coord); + if (neighbor_rr_gsb.is_cb_exist(CHANX)) { + fabric_tile.add_cb_coordinate(curr_tile_id, CHANX, + neighbor_rr_gsb.get_sb_coordinate()); + } + if (neighbor_rr_gsb.is_sb_exist(rr_graph)) { + fabric_tile.add_sb_coordinate(curr_tile_id, + neighbor_rr_gsb.get_sb_coordinate()); + } + } + } + + return status_code; +} + /******************************************************************** * Build tile-level information for a given FPGA fabric, w.r.t. to configuration *******************************************************************/ @@ -152,6 +255,10 @@ int build_fabric_tile(FabricTile& fabric_tile, const TileConfig& tile_config, if (tile_config.style() == TileConfig::e_style::TOP_LEFT) { status_code = build_fabric_tile_style_top_left( fabric_tile, grids, 0, rr_graph, device_rr_gsb, verbose); + } else if (tile_config.style() == TileConfig::e_style::BOTTOM_LEFT) { + status_code = build_fabric_tile_style_bottom_left( + fabric_tile, grids, 0, rr_graph, device_rr_gsb, verbose); + } else { /* Error out for styles that are not supported yet! */ VTR_LOG_ERROR("Tile style '%s' is not supported yet!\n", diff --git a/openfpga/src/fabric/build_tile_modules.cpp b/openfpga/src/fabric/build_tile_modules.cpp index f93cd07bf..ab5b535fe 100644 --- a/openfpga/src/fabric/build_tile_modules.cpp +++ b/openfpga/src/fabric/build_tile_modules.cpp @@ -732,13 +732,13 @@ static int build_tile_module_port_and_nets_between_sb_and_cb( * is_cb_exist() FOr RIGHT and BOTTOM side, find the adjacent RRGSB and then * use is_cb_exist() */ - if (TOP == side_manager.get_side() || LEFT == side_manager.get_side()) { + if (BOTTOM == side_manager.get_side() || LEFT == side_manager.get_side()) { if (false == rr_gsb.is_cb_exist(cb_type)) { continue; } } - if (RIGHT == side_manager.get_side() || BOTTOM == side_manager.get_side()) { + if (RIGHT == side_manager.get_side() || TOP == side_manager.get_side()) { const RRGSB& adjacent_gsb = device_rr_gsb.get_gsb(module_gsb_cb_coordinate); if (false == adjacent_gsb.is_cb_exist(cb_type)) { From cca9fb475663e2cf01f000178b76a98413fda47f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 5 Jul 2024 17:55:19 -0700 Subject: [PATCH 45/91] [core] fixed a bug on bottom left tile organization --- openfpga/src/fabric/build_fabric_tile.cpp | 123 ++++++++++++++-------- 1 file changed, 78 insertions(+), 45 deletions(-) diff --git a/openfpga/src/fabric/build_fabric_tile.cpp b/openfpga/src/fabric/build_fabric_tile.cpp index c20c37537..9e4580600 100644 --- a/openfpga/src/fabric/build_fabric_tile.cpp +++ b/openfpga/src/fabric/build_fabric_tile.cpp @@ -34,8 +34,6 @@ static int find_or_create_one_fabric_tile_from_grid( FabricTileId& curr_tile_id, const DeviceGrid& grids, const t_physical_tile_loc& tile_loc, - const RRGraphView& rr_graph, - const DeviceRRGSB& device_rr_gsb, const bool& verbose) { t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(tile_loc); @@ -46,18 +44,7 @@ static int find_or_create_one_fabric_tile_from_grid( /* For EMPTY grid, routing blocks may still be required if there is a gsb */ if (true == is_empty_type(phy_tile_type)) { - skip_add_pb = true; - if (!device_rr_gsb.is_gsb_exist(rr_graph, curr_gsb_coord)) { - VTR_LOGV(verbose, "Skip tile[%lu][%lu] as it is empty\n", - curr_tile_coord.x(), curr_tile_coord.y()); - return CMD_EXEC_SUCCESS; - } - /* Need to create a new tile here */ - VTR_LOGV(verbose, - "Create tile[%lu][%lu] which only has routing but not a " - "programmable block\n", - curr_tile_coord.x(), curr_tile_coord.y()); - curr_tile_id = fabric_tile.create_tile(curr_tile_coord); + return CMD_EXEC_SUCCESS; } else if ((0 < grids.get_width_offset(tile_loc)) || (0 < grids.get_height_offset(tile_loc))) { /* Skip width, height > 1 tiles (mostly heterogeneous blocks) */ @@ -138,28 +125,42 @@ static int build_fabric_tile_style_bottom_left(FabricTile& fabric_tile, for (size_t iy = 0; iy < grids.height(); ++iy) { t_physical_tile_loc tile_loc(ix, iy, layer); FabricTileId curr_tile_id = FabricTileId::INVALID(); - status_code = find_or_create_one_fabric_tile_from_grid(fabric_tile, curr_tile_id, grids, tile_loc, rr_graph, device_rr_gsb, verbose); + status_code = find_or_create_one_fabric_tile_from_grid(fabric_tile, curr_tile_id, grids, tile_loc, verbose); if (status_code != CMD_EXEC_SUCCESS) { return CMD_EXEC_FATAL_ERROR; } - /* If no valid tile is created or spotted, the tile does not exist physically, skip */ - if (fabric_tile.valid_tile_id(curr_tile_id)) { - continue; - } + /* If no tile is created for the pb, check if routing exists */ + vtr::Point curr_tile_coord(tile_loc.x, tile_loc.y); vtr::Point curr_gsb_coord(ix, iy); - if (!device_rr_gsb.is_gsb_exist(rr_graph, curr_gsb_coord)) { - continue; + if (!fabric_tile.valid_tile_id(curr_tile_id)) { + if (!device_rr_gsb.is_gsb_exist(rr_graph, curr_gsb_coord)) { + VTR_LOGV(verbose, "Skip tile[%lu][%lu] as it is empty\n", + curr_tile_coord.x(), curr_tile_coord.y()); + continue; + } + /* Need to create a new tile here */ + VTR_LOGV(verbose, + "Create tile[%lu][%lu] which only has routing but not a " + "programmable block\n", + curr_tile_coord.x(), curr_tile_coord.y()); + curr_tile_id = fabric_tile.create_tile(curr_tile_coord); } const RRGSB& curr_rr_gsb = device_rr_gsb.get_gsb(curr_gsb_coord); for (t_rr_type cb_type : {CHANX, CHANY}) { if (curr_rr_gsb.is_cb_exist(cb_type)) { fabric_tile.add_cb_coordinate(curr_tile_id, cb_type, curr_rr_gsb.get_sb_coordinate()); + VTR_LOGV(verbose, "Added %s connection block [%lu][%lu] to tile[%lu][%lu]\n", + cb_type == CHANX ? "x-" : "y-", curr_rr_gsb.get_cb_x(cb_type), curr_rr_gsb.get_cb_y(cb_type), + ix, iy); } } if (curr_rr_gsb.is_sb_exist(rr_graph)) { fabric_tile.add_sb_coordinate(curr_tile_id, curr_rr_gsb.get_sb_coordinate()); + VTR_LOGV(verbose, "Added switch block [%lu][%lu] to tile[%lu][%lu]\n", + curr_rr_gsb.get_sb_x(), curr_rr_gsb.get_sb_y(), + ix, iy); } } } @@ -200,37 +201,69 @@ static int build_fabric_tile_style_top_left(FabricTile& fabric_tile, for (size_t iy = 0; iy < grids.height(); ++iy) { t_physical_tile_loc tile_loc(ix, iy, layer); FabricTileId curr_tile_id = FabricTileId::INVALID(); - status_code = find_or_create_one_fabric_tile_from_grid(fabric_tile, curr_tile_id, grids, tile_loc, rr_graph, device_rr_gsb, verbose); + status_code = find_or_create_one_fabric_tile_from_grid(fabric_tile, curr_tile_id, grids, tile_loc, verbose); if (status_code != CMD_EXEC_SUCCESS) { return CMD_EXEC_FATAL_ERROR; } - /* If no valid tile is created or spotted, the tile does not exist physically, skip */ - if (fabric_tile.valid_tile_id(curr_tile_id)) { - continue; + /* If no valid tile is created/found by the pb, check if there is any routing inside */ + vtr::Point curr_tile_coord(tile_loc.x, tile_loc.y); + vtr::Point curr_gsb_coord(ix, iy); + vtr::Point neighbor_gsb_coord(ix, iy - 1); + if (!fabric_tile.valid_tile_id(curr_tile_id)) { + bool routing_exist = false; + if (device_rr_gsb.is_gsb_exist(rr_graph, curr_gsb_coord)) { + const RRGSB& routing_rr_gsb = device_rr_gsb.get_gsb(curr_gsb_coord); + if (routing_rr_gsb.is_cb_exist(CHANY)) { + routing_exist = true; + } + } + if (device_rr_gsb.is_gsb_exist(rr_graph, neighbor_gsb_coord)) { + const RRGSB& routing_rr_gsb = device_rr_gsb.get_gsb(neighbor_gsb_coord); + if (routing_rr_gsb.is_cb_exist(CHANX) || routing_rr_gsb.is_sb_exist(rr_graph)) { + routing_exist = true; + } + } + if (!routing_exist) { + VTR_LOGV(verbose, "Skip tile[%lu][%lu] as it is empty\n", + curr_tile_coord.x(), curr_tile_coord.y()); + continue; + } + /* Need to create a new tile here */ + VTR_LOGV(verbose, + "Create tile[%lu][%lu] which only has routing but not a " + "programmable block\n", + curr_tile_coord.x(), curr_tile_coord.y()); + curr_tile_id = fabric_tile.create_tile(curr_tile_coord); } /* For the cby in the same gsb */ - vtr::Point curr_gsb_coord(ix, iy); - if (!device_rr_gsb.is_gsb_exist(rr_graph, curr_gsb_coord)) { - continue; - } - const RRGSB& curr_rr_gsb = device_rr_gsb.get_gsb(curr_gsb_coord); - if (curr_rr_gsb.is_cb_exist(CHANY)) { - fabric_tile.add_cb_coordinate(curr_tile_id, CHANY, - curr_rr_gsb.get_sb_coordinate()); + if (device_rr_gsb.is_gsb_exist(rr_graph, curr_gsb_coord)) { + const RRGSB& curr_rr_gsb = device_rr_gsb.get_gsb(curr_gsb_coord); + if (curr_rr_gsb.is_cb_exist(CHANY)) { + fabric_tile.add_cb_coordinate(curr_tile_id, CHANY, + curr_rr_gsb.get_sb_coordinate()); + VTR_LOGV(verbose, "Added y- connection block [%lu][%lu] to tile[%lu][%lu]\n", + curr_rr_gsb.get_cb_x(CHANY), curr_rr_gsb.get_cb_y(CHANY), + ix, iy); + } } /* For the cbx and sb in the neighbour gsb */ - vtr::Point neighbor_gsb_coord(ix, iy - 1); - if (!device_rr_gsb.is_gsb_exist(rr_graph, neighbor_gsb_coord)) { - continue; - } - const RRGSB& neighbor_rr_gsb = device_rr_gsb.get_gsb(neighbor_gsb_coord); - if (neighbor_rr_gsb.is_cb_exist(CHANX)) { - fabric_tile.add_cb_coordinate(curr_tile_id, CHANX, - neighbor_rr_gsb.get_sb_coordinate()); - } - if (neighbor_rr_gsb.is_sb_exist(rr_graph)) { - fabric_tile.add_sb_coordinate(curr_tile_id, - neighbor_rr_gsb.get_sb_coordinate()); + if (device_rr_gsb.is_gsb_exist(rr_graph, neighbor_gsb_coord)) { + const RRGSB& neighbor_rr_gsb = device_rr_gsb.get_gsb(neighbor_gsb_coord); + if (neighbor_rr_gsb.is_cb_exist(CHANX)) { + fabric_tile.add_cb_coordinate(curr_tile_id, CHANX, + neighbor_rr_gsb.get_sb_coordinate()); + + VTR_LOGV(verbose, "Added x- connection block [%lu][%lu] to tile[%lu][%lu]\n", + neighbor_rr_gsb.get_cb_x(CHANX), neighbor_rr_gsb.get_cb_y(CHANX), + ix, iy); + } + if (neighbor_rr_gsb.is_sb_exist(rr_graph)) { + fabric_tile.add_sb_coordinate(curr_tile_id, + neighbor_rr_gsb.get_sb_coordinate()); + VTR_LOGV(verbose, "Added switch block [%lu][%lu] to tile[%lu][%lu]\n", + neighbor_rr_gsb.get_sb_x(), neighbor_rr_gsb.get_sb_y(), + ix, iy); + } } } } From a46820b7c1e820446a5e3557970ea46acb982535 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 5 Jul 2024 18:00:37 -0700 Subject: [PATCH 46/91] [core] add a new test for bottom-left tile grouping --- .../regression_test_scripts/basic_reg_test.sh | 1 + .../homo_fabric_tile_bl/config/task.conf | 35 +++++++++++++++++++ .../config/tile_config.xml | 1 + 3 files changed, 37 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_bl/config/task.conf create mode 100644 openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_bl/config/tile_config.xml diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index e8902632c..cdb93ee16 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -194,6 +194,7 @@ echo -e "Testing tiles with routing tracks around I/O"; run-task basic_tests/tile_organization/perimeter_cb $@ echo -e "Testing tile grouping on a homogeneous FPGA fabric (Full testbench)"; run-task basic_tests/tile_organization/homo_fabric_tile $@ +run-task basic_tests/tile_organization/homo_fabric_tile_bl $@ echo -e "Testing tile grouping on a homogeneous FPGA fabric (Preconfigured testbench)"; run-task basic_tests/tile_organization/fabric_tile_global_tile_clock_io_subtile $@ run-task basic_tests/tile_organization/homo_fabric_tile_preconfig $@ diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_bl/config/task.conf b/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_bl/config/task.conf new file mode 100644 index 000000000..c07a08d33 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_bl/config/task.conf @@ -0,0 +1,35 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/group_tile_full_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzTl_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = or2 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_bl/config/tile_config.xml b/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_bl/config/tile_config.xml new file mode 100644 index 000000000..026c140be --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_bl/config/tile_config.xml @@ -0,0 +1 @@ + From e95b264965eaf5063226a4ecb580d70af6d9767a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 5 Jul 2024 18:08:48 -0700 Subject: [PATCH 47/91] [core] debugging --- openfpga/src/fabric/build_fabric_tile.cpp | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/openfpga/src/fabric/build_fabric_tile.cpp b/openfpga/src/fabric/build_fabric_tile.cpp index 9e4580600..b8dd25938 100644 --- a/openfpga/src/fabric/build_fabric_tile.cpp +++ b/openfpga/src/fabric/build_fabric_tile.cpp @@ -145,6 +145,11 @@ static int build_fabric_tile_style_bottom_left(FabricTile& fabric_tile, curr_tile_coord.x(), curr_tile_coord.y()); curr_tile_id = fabric_tile.create_tile(curr_tile_coord); } + if (fabric_tile.valid_tile_id(curr_tile_id) && !device_rr_gsb.is_gsb_exist(rr_graph, curr_gsb_coord)) { + VTR_LOGV(verbose, "Skip to add routing to tile[%lu][%lu] as it is not required\n", + curr_tile_coord.x(), curr_tile_coord.y()); + continue; + } const RRGSB& curr_rr_gsb = device_rr_gsb.get_gsb(curr_gsb_coord); for (t_rr_type cb_type : {CHANX, CHANY}) { if (curr_rr_gsb.is_cb_exist(cb_type)) { From 1f7fbfef64cd2b2657600341b0655725731606a7 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 5 Jul 2024 18:19:22 -0700 Subject: [PATCH 48/91] [core] fixed a bug on inter-tile connections in top module --- openfpga/src/fabric/build_top_module_child_tile_instance.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openfpga/src/fabric/build_top_module_child_tile_instance.cpp b/openfpga/src/fabric/build_top_module_child_tile_instance.cpp index 3c1c86c1c..0ad953f68 100644 --- a/openfpga/src/fabric/build_top_module_child_tile_instance.cpp +++ b/openfpga/src/fabric/build_top_module_child_tile_instance.cpp @@ -802,13 +802,13 @@ static int build_top_module_tile_nets_between_sb_and_cb( * is_cb_exist() FOr RIGHT and BOTTOM side, find the adjacent RRGSB and then * use is_cb_exist() */ - if (TOP == side_manager.get_side() || LEFT == side_manager.get_side()) { + if (BOTTOM == side_manager.get_side() || LEFT == side_manager.get_side()) { if (false == rr_gsb.is_cb_exist(cb_type)) { continue; } } - if (RIGHT == side_manager.get_side() || BOTTOM == side_manager.get_side()) { + if (RIGHT == side_manager.get_side() || TOP == side_manager.get_side()) { const RRGSB& adjacent_gsb = device_rr_gsb.get_gsb(module_gsb_cb_coordinate); if (false == adjacent_gsb.is_cb_exist(cb_type)) { From 6024e35f89ce05eaa8431481008c00c945fa0ae6 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 5 Jul 2024 18:50:14 -0700 Subject: [PATCH 49/91] [core] fixed a bug --- openfpga/src/fabric/build_top_module_memory.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga/src/fabric/build_top_module_memory.cpp b/openfpga/src/fabric/build_top_module_memory.cpp index 47238685e..d9d65fbc2 100644 --- a/openfpga/src/fabric/build_top_module_memory.cpp +++ b/openfpga/src/fabric/build_top_module_memory.cpp @@ -141,7 +141,7 @@ static void organize_top_module_tile_memory_modules( const vtr::Point& tile_coord, const e_side& tile_border_side) { vtr::Point gsb_coord_range = device_rr_gsb.get_gsb_range(); - vtr::Point gsb_coord(tile_coord.x(), tile_coord.y() - 1); + vtr::Point gsb_coord(tile_coord.x(), tile_coord.y()); /* We do NOT consider SB and CBs if the gsb is not in the range! */ if ((gsb_coord.x() < gsb_coord_range.x()) && From 43ca3ec747e4232d54509d2c4c4d9add5518706e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 6 Jul 2024 12:11:31 -0700 Subject: [PATCH 50/91] [test] make arch pin loc for spread for perimeter cb validation --- ...k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml index 11b4d4d4e..2bab2cd89 100644 --- a/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml +++ b/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml @@ -93,9 +93,9 @@ - fpga_input[0:3].inpad + fpga_input[0:1].inpad - + fpga_input[2:3].inpad @@ -106,9 +106,9 @@ - fpga_output[0:1].outpad + fpga_output[0:0].outpad - + fpga_output[1:1].outpad @@ -122,8 +122,8 @@ - - fpga_input.inpad + fpga_input[0:1].inpad + fpga_input[2:3].inpad @@ -135,8 +135,8 @@ - - fpga_output.outpad + fpga_output[0:0].outpad + fpga_output[1:1].outpad From 703cbddc9ed3812b0ff651765997516236bcc9af Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 6 Jul 2024 12:14:57 -0700 Subject: [PATCH 51/91] [core] code format --- openfpga/src/annotation/annotate_rr_graph.cpp | 10 +-- .../base/openfpga_verilog_command_template.h | 6 +- openfpga/src/base/openfpga_verilog_template.h | 10 ++- openfpga/src/fabric/build_device_module.cpp | 3 +- openfpga/src/fabric/build_fabric_tile.cpp | 87 ++++++++++--------- .../build_grid_module_duplicated_pins.cpp | 11 ++- .../src/fabric/build_grid_module_utils.cpp | 10 ++- openfpga/src/fabric/build_grid_module_utils.h | 3 +- openfpga/src/fabric/build_grid_modules.cpp | 20 ++--- openfpga/src/fabric/build_tile_modules.cpp | 38 ++++---- openfpga/src/fabric/build_tile_modules.h | 23 +++-- ...top_module_child_fine_grained_instance.cpp | 23 +++-- ...d_top_module_child_fine_grained_instance.h | 3 +- .../fabric/build_top_module_connection.cpp | 10 ++- .../fpga_verilog/fabric_verilog_options.cpp | 4 +- openfpga/src/fpga_verilog/verilog_grid.cpp | 14 ++- openfpga/src/fpga_verilog/verilog_lut.cpp | 3 +- openfpga/src/fpga_verilog/verilog_memory.cpp | 13 ++- .../fpga_verilog/verilog_module_writer.cpp | 39 +++++---- openfpga/src/fpga_verilog/verilog_mux.cpp | 6 +- openfpga/src/fpga_verilog/verilog_routing.cpp | 14 ++- .../verilog_shift_register_banks.cpp | 14 ++- openfpga/src/fpga_verilog/verilog_tile.cpp | 7 +- .../src/fpga_verilog/verilog_top_module.cpp | 14 ++- 24 files changed, 192 insertions(+), 193 deletions(-) diff --git a/openfpga/src/annotation/annotate_rr_graph.cpp b/openfpga/src/annotation/annotate_rr_graph.cpp index a1ad9c24c..373607fb2 100644 --- a/openfpga/src/annotation/annotate_rr_graph.cpp +++ b/openfpga/src/annotation/annotate_rr_graph.cpp @@ -98,8 +98,7 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, const vtr::Point& gsb_range, const size_t& layer, const vtr::Point& gsb_coord, - const bool& perimeter_cb, - const bool& include_clock) { + const bool& perimeter_cb, const bool& include_clock) { /* Create an object to return */ RRGSB rr_gsb; @@ -436,10 +435,9 @@ void annotate_device_rr_gsb(const DeviceContext& vpr_device_ctx, */ vtr::Point sub_gsb_range(vpr_device_ctx.grid.width() - 1, vpr_device_ctx.grid.height() - 1); - const RRGSB& rr_gsb = - build_rr_gsb(vpr_device_ctx, - sub_gsb_range, - layer, vtr::Point(ix, iy), vpr_device_ctx.arch->perimeter_cb, include_clock); + const RRGSB& rr_gsb = build_rr_gsb( + vpr_device_ctx, sub_gsb_range, layer, vtr::Point(ix, iy), + vpr_device_ctx.arch->perimeter_cb, include_clock); /* Add to device_rr_gsb */ vtr::Point gsb_coordinate = rr_gsb.get_sb_coordinate(); device_rr_gsb.add_rr_gsb(gsb_coordinate, rr_gsb); diff --git a/openfpga/src/base/openfpga_verilog_command_template.h b/openfpga/src/base/openfpga_verilog_command_template.h index 2cd03278e..001f7ee40 100644 --- a/openfpga/src/base/openfpga_verilog_command_template.h +++ b/openfpga/src/base/openfpga_verilog_command_template.h @@ -31,8 +31,10 @@ ShellCommandId add_write_fabric_verilog_command_template( shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING); /* Add an option '--constant_undriven_inputs' */ - shell_cmd.add_option("constant_undriven_inputs", false, - "Use constant gnd for undriven wires in Verilog netlists. Recommand to enable when there are boundary routing tracks in FPGA fabric"); + shell_cmd.add_option( + "constant_undriven_inputs", false, + "Use constant gnd for undriven wires in Verilog netlists. Recommand to " + "enable when there are boundary routing tracks in FPGA fabric"); /* Add an option '--explicit_port_mapping' */ shell_cmd.add_option("explicit_port_mapping", false, diff --git a/openfpga/src/base/openfpga_verilog_template.h b/openfpga/src/base/openfpga_verilog_template.h index 19109ce21..93dc8035a 100644 --- a/openfpga/src/base/openfpga_verilog_template.h +++ b/openfpga/src/base/openfpga_verilog_template.h @@ -58,12 +58,16 @@ int write_fabric_verilog_template(T& openfpga_ctx, const Command& cmd, } options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose)); options.set_compress_routing(openfpga_ctx.flow_manager().compress_routing()); - /* For perimeter cb, enable the constant undriven inputs, unless it is off by user */ + /* For perimeter cb, enable the constant undriven inputs, unless it is off by + * user */ if (g_vpr_ctx.device().arch->perimeter_cb) { options.set_constant_undriven_inputs(true); - VTR_LOG("Automatically enable the constant_undriven_input option as perimeter connection blocks are seen in FPGA fabric\n"); + VTR_LOG( + "Automatically enable the constant_undriven_input option as perimeter " + "connection blocks are seen in FPGA fabric\n"); } else { - options.set_constant_undriven_inputs(cmd_context.option_enable(cmd, opt_constant_undriven_inputs)); + options.set_constant_undriven_inputs( + cmd_context.option_enable(cmd, opt_constant_undriven_inputs)); } return fpga_fabric_verilog( diff --git a/openfpga/src/fabric/build_device_module.cpp b/openfpga/src/fabric/build_device_module.cpp index e03ee2510..a04e9e015 100644 --- a/openfpga/src/fabric/build_device_module.cpp +++ b/openfpga/src/fabric/build_device_module.cpp @@ -128,7 +128,8 @@ int build_device_module_graph( openfpga_ctx.device_rr_gsb(), vpr_device_ctx.rr_graph, openfpga_ctx.arch().tile_annotations, openfpga_ctx.arch().circuit_lib, sram_model, openfpga_ctx.arch().config_protocol.type(), - name_module_using_index, vpr_device_ctx.arch->perimeter_cb, frame_view, verbose); + name_module_using_index, vpr_device_ctx.arch->perimeter_cb, frame_view, + verbose); } /* Build FPGA fabric top-level module */ diff --git a/openfpga/src/fabric/build_fabric_tile.cpp b/openfpga/src/fabric/build_fabric_tile.cpp index b8dd25938..e9747e920 100644 --- a/openfpga/src/fabric/build_fabric_tile.cpp +++ b/openfpga/src/fabric/build_fabric_tile.cpp @@ -22,7 +22,7 @@ namespace openfpga { /******************************************************************** - * With a given coordinate of a grid, find an existing fabric tile + * With a given coordinate of a grid, find an existing fabric tile * or create a new fabric tile * - A grid may never exist in any fabric tile (no coordinate matches) * Create a new one @@ -30,13 +30,9 @@ namespace openfpga { * Find the existing one *******************************************************************/ static int find_or_create_one_fabric_tile_from_grid( - FabricTile& fabric_tile, - FabricTileId& curr_tile_id, - const DeviceGrid& grids, - const t_physical_tile_loc& tile_loc, - const bool& verbose) { - t_physical_tile_type_ptr phy_tile_type = - grids.get_physical_type(tile_loc); + FabricTile& fabric_tile, FabricTileId& curr_tile_id, const DeviceGrid& grids, + const t_physical_tile_loc& tile_loc, const bool& verbose) { + t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(tile_loc); vtr::Point curr_tile_coord(tile_loc.x, tile_loc.y); vtr::Point curr_gsb_coord(tile_loc.x, tile_loc.y); @@ -71,8 +67,8 @@ static int find_or_create_one_fabric_tile_from_grid( } } else { /* Need to create a new tile here */ - VTR_LOGV(verbose, "Create a regular tile[%lu][%lu]\n", - curr_tile_coord.x(), curr_tile_coord.y()); + VTR_LOGV(verbose, "Create a regular tile[%lu][%lu]\n", curr_tile_coord.x(), + curr_tile_coord.y()); curr_tile_id = fabric_tile.create_tile(curr_tile_coord); } @@ -100,7 +96,7 @@ static int find_or_create_one_fabric_tile_from_grid( * The gsb coordinate is the same as the grid coordinate when the * bottom-left style is considered * - * ------------------------------ + * ------------------------------ * +----------+ +----------+ ^ * | CBx | | SB | | * | [x][y] | | [x][y] | GSB[x][y] @@ -113,11 +109,11 @@ static int find_or_create_one_fabric_tile_from_grid( * *******************************************************************/ static int build_fabric_tile_style_bottom_left(FabricTile& fabric_tile, - const DeviceGrid& grids, - const size_t& layer, - const RRGraphView& rr_graph, - const DeviceRRGSB& device_rr_gsb, - const bool& verbose) { + const DeviceGrid& grids, + const size_t& layer, + const RRGraphView& rr_graph, + const DeviceRRGSB& device_rr_gsb, + const bool& verbose) { int status_code = CMD_EXEC_SUCCESS; /* Walk through all the device rr_gsb and create tile one by one */ @@ -125,7 +121,8 @@ static int build_fabric_tile_style_bottom_left(FabricTile& fabric_tile, for (size_t iy = 0; iy < grids.height(); ++iy) { t_physical_tile_loc tile_loc(ix, iy, layer); FabricTileId curr_tile_id = FabricTileId::INVALID(); - status_code = find_or_create_one_fabric_tile_from_grid(fabric_tile, curr_tile_id, grids, tile_loc, verbose); + status_code = find_or_create_one_fabric_tile_from_grid( + fabric_tile, curr_tile_id, grids, tile_loc, verbose); if (status_code != CMD_EXEC_SUCCESS) { return CMD_EXEC_FATAL_ERROR; } @@ -145,9 +142,12 @@ static int build_fabric_tile_style_bottom_left(FabricTile& fabric_tile, curr_tile_coord.x(), curr_tile_coord.y()); curr_tile_id = fabric_tile.create_tile(curr_tile_coord); } - if (fabric_tile.valid_tile_id(curr_tile_id) && !device_rr_gsb.is_gsb_exist(rr_graph, curr_gsb_coord)) { - VTR_LOGV(verbose, "Skip to add routing to tile[%lu][%lu] as it is not required\n", - curr_tile_coord.x(), curr_tile_coord.y()); + if (fabric_tile.valid_tile_id(curr_tile_id) && + !device_rr_gsb.is_gsb_exist(rr_graph, curr_gsb_coord)) { + VTR_LOGV( + verbose, + "Skip to add routing to tile[%lu][%lu] as it is not required\n", + curr_tile_coord.x(), curr_tile_coord.y()); continue; } const RRGSB& curr_rr_gsb = device_rr_gsb.get_gsb(curr_gsb_coord); @@ -155,17 +155,17 @@ static int build_fabric_tile_style_bottom_left(FabricTile& fabric_tile, if (curr_rr_gsb.is_cb_exist(cb_type)) { fabric_tile.add_cb_coordinate(curr_tile_id, cb_type, curr_rr_gsb.get_sb_coordinate()); - VTR_LOGV(verbose, "Added %s connection block [%lu][%lu] to tile[%lu][%lu]\n", - cb_type == CHANX ? "x-" : "y-", curr_rr_gsb.get_cb_x(cb_type), curr_rr_gsb.get_cb_y(cb_type), - ix, iy); + VTR_LOGV( + verbose, "Added %s connection block [%lu][%lu] to tile[%lu][%lu]\n", + cb_type == CHANX ? "x-" : "y-", curr_rr_gsb.get_cb_x(cb_type), + curr_rr_gsb.get_cb_y(cb_type), ix, iy); } } if (curr_rr_gsb.is_sb_exist(rr_graph)) { fabric_tile.add_sb_coordinate(curr_tile_id, curr_rr_gsb.get_sb_coordinate()); VTR_LOGV(verbose, "Added switch block [%lu][%lu] to tile[%lu][%lu]\n", - curr_rr_gsb.get_sb_x(), curr_rr_gsb.get_sb_y(), - ix, iy); + curr_rr_gsb.get_sb_x(), curr_rr_gsb.get_sb_y(), ix, iy); } } } @@ -173,19 +173,18 @@ static int build_fabric_tile_style_bottom_left(FabricTile& fabric_tile, return status_code; } - /******************************************************************** * Build tiles by following the top-left style. * - The programmble block, e.g., clb, is placed on the top-left corner * - The connection blocks and switch block are placed on the right and bottom *sides * Tile[x][y] - * ------------------------------ + * ------------------------------ * +----------+ +----------+ ^ * | Grid | | CBy | GSB[x][y] * | [x][y] | | [x][y] | | * +----------+ +----------+ v - * ------------------------------ + * ------------------------------ * +----------+ +----------+ ^ * | CBx | | SB | | * | [x][y-1] | | [x][y-1] | GSB[x][y-1] @@ -206,11 +205,13 @@ static int build_fabric_tile_style_top_left(FabricTile& fabric_tile, for (size_t iy = 0; iy < grids.height(); ++iy) { t_physical_tile_loc tile_loc(ix, iy, layer); FabricTileId curr_tile_id = FabricTileId::INVALID(); - status_code = find_or_create_one_fabric_tile_from_grid(fabric_tile, curr_tile_id, grids, tile_loc, verbose); + status_code = find_or_create_one_fabric_tile_from_grid( + fabric_tile, curr_tile_id, grids, tile_loc, verbose); if (status_code != CMD_EXEC_SUCCESS) { return CMD_EXEC_FATAL_ERROR; } - /* If no valid tile is created/found by the pb, check if there is any routing inside */ + /* If no valid tile is created/found by the pb, check if there is any + * routing inside */ vtr::Point curr_tile_coord(tile_loc.x, tile_loc.y); vtr::Point curr_gsb_coord(ix, iy); vtr::Point neighbor_gsb_coord(ix, iy - 1); @@ -223,8 +224,10 @@ static int build_fabric_tile_style_top_left(FabricTile& fabric_tile, } } if (device_rr_gsb.is_gsb_exist(rr_graph, neighbor_gsb_coord)) { - const RRGSB& routing_rr_gsb = device_rr_gsb.get_gsb(neighbor_gsb_coord); - if (routing_rr_gsb.is_cb_exist(CHANX) || routing_rr_gsb.is_sb_exist(rr_graph)) { + const RRGSB& routing_rr_gsb = + device_rr_gsb.get_gsb(neighbor_gsb_coord); + if (routing_rr_gsb.is_cb_exist(CHANX) || + routing_rr_gsb.is_sb_exist(rr_graph)) { routing_exist = true; } } @@ -246,28 +249,30 @@ static int build_fabric_tile_style_top_left(FabricTile& fabric_tile, if (curr_rr_gsb.is_cb_exist(CHANY)) { fabric_tile.add_cb_coordinate(curr_tile_id, CHANY, curr_rr_gsb.get_sb_coordinate()); - VTR_LOGV(verbose, "Added y- connection block [%lu][%lu] to tile[%lu][%lu]\n", - curr_rr_gsb.get_cb_x(CHANY), curr_rr_gsb.get_cb_y(CHANY), - ix, iy); + VTR_LOGV( + verbose, "Added y- connection block [%lu][%lu] to tile[%lu][%lu]\n", + curr_rr_gsb.get_cb_x(CHANY), curr_rr_gsb.get_cb_y(CHANY), ix, iy); } } /* For the cbx and sb in the neighbour gsb */ if (device_rr_gsb.is_gsb_exist(rr_graph, neighbor_gsb_coord)) { - const RRGSB& neighbor_rr_gsb = device_rr_gsb.get_gsb(neighbor_gsb_coord); + const RRGSB& neighbor_rr_gsb = + device_rr_gsb.get_gsb(neighbor_gsb_coord); if (neighbor_rr_gsb.is_cb_exist(CHANX)) { fabric_tile.add_cb_coordinate(curr_tile_id, CHANX, neighbor_rr_gsb.get_sb_coordinate()); - VTR_LOGV(verbose, "Added x- connection block [%lu][%lu] to tile[%lu][%lu]\n", - neighbor_rr_gsb.get_cb_x(CHANX), neighbor_rr_gsb.get_cb_y(CHANX), - ix, iy); + VTR_LOGV(verbose, + "Added x- connection block [%lu][%lu] to tile[%lu][%lu]\n", + neighbor_rr_gsb.get_cb_x(CHANX), + neighbor_rr_gsb.get_cb_y(CHANX), ix, iy); } if (neighbor_rr_gsb.is_sb_exist(rr_graph)) { fabric_tile.add_sb_coordinate(curr_tile_id, neighbor_rr_gsb.get_sb_coordinate()); VTR_LOGV(verbose, "Added switch block [%lu][%lu] to tile[%lu][%lu]\n", - neighbor_rr_gsb.get_sb_x(), neighbor_rr_gsb.get_sb_y(), - ix, iy); + neighbor_rr_gsb.get_sb_x(), neighbor_rr_gsb.get_sb_y(), ix, + iy); } } } diff --git a/openfpga/src/fabric/build_grid_module_duplicated_pins.cpp b/openfpga/src/fabric/build_grid_module_duplicated_pins.cpp index 7e628e459..6118e673d 100644 --- a/openfpga/src/fabric/build_grid_module_duplicated_pins.cpp +++ b/openfpga/src/fabric/build_grid_module_duplicated_pins.cpp @@ -66,8 +66,8 @@ void add_grid_module_duplicated_pb_type_ports( * Otherwise, we will iterate all the 4 sides */ if (true == is_io_type(grid_type_descriptor)) { - grid_pin_sides = - find_grid_module_pin_sides(grid_type_descriptor, border_side, perimeter_cb); + grid_pin_sides = find_grid_module_pin_sides(grid_type_descriptor, + border_side, perimeter_cb); } else { grid_pin_sides = {TOP, RIGHT, BOTTOM, LEFT}; } @@ -173,8 +173,7 @@ static void add_grid_module_net_connect_duplicated_pb_graph_pin( const size_t& child_inst_subtile_index, const VprDeviceAnnotation& vpr_device_annotation, t_physical_tile_type_ptr grid_type_descriptor, t_pb_graph_pin* pb_graph_pin, - const e_side& border_side, - const bool& perimeter_cb, + const e_side& border_side, const bool& perimeter_cb, const e_pin2pin_interc_type& pin2pin_interc_type) { /* Make sure this is ONLY applied to output pins */ VTR_ASSERT(OUTPUT2OUTPUT_INTERC == pin2pin_interc_type); @@ -185,8 +184,8 @@ static void add_grid_module_net_connect_duplicated_pb_graph_pin( * Otherwise, we will iterate all the 4 sides */ if (true == is_io_type(grid_type_descriptor)) { - grid_pin_sides = - find_grid_module_pin_sides(grid_type_descriptor, border_side, perimeter_cb); + grid_pin_sides = find_grid_module_pin_sides(grid_type_descriptor, + border_side, perimeter_cb); } else { grid_pin_sides = {TOP, RIGHT, BOTTOM, LEFT}; } diff --git a/openfpga/src/fabric/build_grid_module_utils.cpp b/openfpga/src/fabric/build_grid_module_utils.cpp index 951e2429d..812038b10 100644 --- a/openfpga/src/fabric/build_grid_module_utils.cpp +++ b/openfpga/src/fabric/build_grid_module_utils.cpp @@ -24,7 +24,8 @@ namespace openfpga { * 5. I/O grids in the center part of FPGA can have ports on any side *******************************************************************/ std::vector find_grid_module_pin_sides( - t_physical_tile_type_ptr grid_type_descriptor, const e_side& border_side, const bool& perimeter_cb) { + t_physical_tile_type_ptr grid_type_descriptor, const e_side& border_side, + const bool& perimeter_cb) { /* We must have an regular (non-I/O) type here */ VTR_ASSERT(true == is_io_type(grid_type_descriptor)); SideManager side_manager(border_side); @@ -36,7 +37,8 @@ std::vector find_grid_module_pin_sides( if (!perimeter_cb) { return std::vector(1, side_manager.get_opposite()); } - /* For cbs on perimeter, exclude the border side. All the other 3 sides are ok */ + /* For cbs on perimeter, exclude the border side. All the other 3 sides are ok + */ std::vector pin_sides; pin_sides.reserve(3); for (e_side pin_side : {TOP, RIGHT, BOTTOM, LEFT}) { @@ -66,8 +68,8 @@ void add_grid_module_net_connect_pb_graph_pin( * Otherwise, we will iterate all the 4 sides */ if (true == is_io_type(grid_type_descriptor)) { - grid_pin_sides = - find_grid_module_pin_sides(grid_type_descriptor, border_side, perimeter_cb); + grid_pin_sides = find_grid_module_pin_sides(grid_type_descriptor, + border_side, perimeter_cb); } else { grid_pin_sides = {TOP, RIGHT, BOTTOM, LEFT}; } diff --git a/openfpga/src/fabric/build_grid_module_utils.h b/openfpga/src/fabric/build_grid_module_utils.h index 1051ae601..d83d9ab9f 100644 --- a/openfpga/src/fabric/build_grid_module_utils.h +++ b/openfpga/src/fabric/build_grid_module_utils.h @@ -19,7 +19,8 @@ namespace openfpga { std::vector find_grid_module_pin_sides( - t_physical_tile_type_ptr grid_type_descriptor, const e_side& border_side, const bool& perimeter_cb); + t_physical_tile_type_ptr grid_type_descriptor, const e_side& border_side, + const bool& perimeter_cb); void add_grid_module_net_connect_pb_graph_pin( ModuleManager& module_manager, const ModuleId& grid_module, diff --git a/openfpga/src/fabric/build_grid_modules.cpp b/openfpga/src/fabric/build_grid_modules.cpp index 8ffe94fda..051a53f4f 100644 --- a/openfpga/src/fabric/build_grid_modules.cpp +++ b/openfpga/src/fabric/build_grid_modules.cpp @@ -42,8 +42,7 @@ static void add_grid_module_pb_type_ports( ModuleManager& module_manager, const ModuleId& grid_module, const VprDeviceAnnotation& vpr_device_annotation, t_physical_tile_type_ptr grid_type_descriptor, - const TileAnnotation& tile_annotation, - const e_side& border_side, + const TileAnnotation& tile_annotation, const e_side& border_side, const bool& perimeter_cb) { /* Ensure that we have a valid grid_type_descriptor */ VTR_ASSERT(nullptr != grid_type_descriptor); @@ -54,8 +53,8 @@ static void add_grid_module_pb_type_ports( * Otherwise, we will iterate all the 4 sides */ if (true == is_io_type(grid_type_descriptor)) { - grid_pin_sides = - find_grid_module_pin_sides(grid_type_descriptor, border_side, perimeter_cb); + grid_pin_sides = find_grid_module_pin_sides(grid_type_descriptor, + border_side, perimeter_cb); } else { grid_pin_sides = {TOP, RIGHT, BOTTOM, LEFT}; } @@ -1171,8 +1170,7 @@ static int build_physical_tile_module( const TileAnnotation& tile_annotation, const e_side& border_side, const QLMemoryBankConfigSetting* ql_memory_bank_config_setting, const bool& duplicate_grid_pin, const bool& group_config_block, - const bool& perimeter_cb, - const bool& verbose) { + const bool& perimeter_cb, const bool& verbose) { int status = CMD_EXEC_SUCCESS; /* Create a Module for the top-level physical block, and add to module manager */ @@ -1268,7 +1266,8 @@ static int build_physical_tile_module( module_manager.child_module_instances(grid_module, pb_module)) { add_grid_module_nets_connect_pb_type_ports( module_manager, grid_module, pb_module, child_instance, sub_tile, - vpr_device_annotation, phy_block_type, tile_annotation, border_side, perimeter_cb); + vpr_device_annotation, phy_block_type, tile_annotation, border_side, + perimeter_cb); } } } else { @@ -1294,7 +1293,8 @@ static int build_physical_tile_module( module_manager.child_module_instances(grid_module, pb_module)) { add_grid_module_nets_connect_duplicated_pb_type_ports( module_manager, grid_module, pb_module, child_instance, sub_tile, - vpr_device_annotation, phy_block_type, tile_annotation, border_side, perimeter_cb); + vpr_device_annotation, phy_block_type, tile_annotation, border_side, + perimeter_cb); } } } @@ -1450,8 +1450,8 @@ int build_grid_modules( status = build_physical_tile_module( module_manager, decoder_lib, device_annotation, circuit_lib, sram_orgz_type, sram_model, &physical_tile, tile_annotation, NUM_SIDES, - ql_memory_bank_config_setting, duplicate_grid_pin, group_config_block, device_ctx.arch->perimeter_cb, - verbose); + ql_memory_bank_config_setting, duplicate_grid_pin, group_config_block, + device_ctx.arch->perimeter_cb, verbose); if (status != CMD_EXEC_SUCCESS) { return CMD_EXEC_FATAL_ERROR; } diff --git a/openfpga/src/fabric/build_tile_modules.cpp b/openfpga/src/fabric/build_tile_modules.cpp index ab5b535fe..f10d913bb 100644 --- a/openfpga/src/fabric/build_tile_modules.cpp +++ b/openfpga/src/fabric/build_tile_modules.cpp @@ -1175,8 +1175,7 @@ static int build_tile_port_and_nets_from_pb( const TileAnnotation& tile_annotation, const vtr::Point& pb_coord, const std::vector& pb_instances, const FabricTile& fabric_tile, const FabricTileId& curr_fabric_tile_id, const size_t& ipb, - const bool& perimeter_cb, - const bool& frame_view, const bool& verbose) { + const bool& perimeter_cb, const bool& frame_view, const bool& verbose) { size_t pb_instance = pb_instances[ipb]; t_physical_tile_type_ptr phy_tile = grids.get_physical_type( t_physical_tile_loc(pb_coord.x(), pb_coord.y(), layer)); @@ -1202,7 +1201,8 @@ static int build_tile_port_and_nets_from_pb( * Otherwise, we will iterate all the 4 sides */ if (true == is_io_type(phy_tile)) { - grid_pin_sides = find_grid_module_pin_sides(phy_tile, grid_side, perimeter_cb); + grid_pin_sides = + find_grid_module_pin_sides(phy_tile, grid_side, perimeter_cb); } else { grid_pin_sides = {TOP, RIGHT, BOTTOM, LEFT}; } @@ -1379,8 +1379,7 @@ static int build_tile_module_ports_and_nets( const FabricTileId& fabric_tile_id, const std::vector& pb_instances, const std::map>& cb_instances, const std::vector& sb_instances, const bool& name_module_using_index, - const bool& perimeter_cb, - const bool& frame_view, const bool& verbose) { + const bool& perimeter_cb, const bool& frame_view, const bool& verbose) { int status_code = CMD_EXEC_SUCCESS; /* Get the submodule of Switch blocks one by one, build connections between sb @@ -1489,10 +1488,8 @@ static int build_tile_module( const TileAnnotation& tile_annotation, const CircuitLibrary& circuit_lib, const CircuitModelId& sram_model, const e_config_protocol_type& sram_orgz_type, - const bool& name_module_using_index, - const bool& perimeter_cb, - const bool& frame_view, - const bool& verbose) { + const bool& name_module_using_index, const bool& perimeter_cb, + const bool& frame_view, const bool& verbose) { int status_code = CMD_EXEC_SUCCESS; /* Create the module */ @@ -1702,19 +1699,16 @@ static int build_tile_module( /******************************************************************** * Build all the tile modules *******************************************************************/ -int build_tile_modules(ModuleManager& module_manager, - DecoderLibrary& decoder_lib, - const FabricTile& fabric_tile, const DeviceGrid& grids, - const VprDeviceAnnotation& vpr_device_annotation, - const DeviceRRGSB& device_rr_gsb, - const RRGraphView& rr_graph_view, - const TileAnnotation& tile_annotation, - const CircuitLibrary& circuit_lib, - const CircuitModelId& sram_model, - const e_config_protocol_type& sram_orgz_type, - const bool& name_module_using_index, - const bool& perimeter_cb, - const bool& frame_view, const bool& verbose) { +int build_tile_modules( + ModuleManager& module_manager, DecoderLibrary& decoder_lib, + const FabricTile& fabric_tile, const DeviceGrid& grids, + const VprDeviceAnnotation& vpr_device_annotation, + const DeviceRRGSB& device_rr_gsb, const RRGraphView& rr_graph_view, + const TileAnnotation& tile_annotation, const CircuitLibrary& circuit_lib, + const CircuitModelId& sram_model, + const e_config_protocol_type& sram_orgz_type, + const bool& name_module_using_index, const bool& perimeter_cb, + const bool& frame_view, const bool& verbose) { vtr::ScopedStartFinishTimer timer("Build tile modules for the FPGA fabric"); int status_code = CMD_EXEC_SUCCESS; diff --git a/openfpga/src/fabric/build_tile_modules.h b/openfpga/src/fabric/build_tile_modules.h index e3a629808..b1507e62c 100644 --- a/openfpga/src/fabric/build_tile_modules.h +++ b/openfpga/src/fabric/build_tile_modules.h @@ -25,19 +25,16 @@ /* begin namespace openfpga */ namespace openfpga { -int build_tile_modules(ModuleManager& module_manager, - DecoderLibrary& decoder_lib, - const FabricTile& fabric_tile, const DeviceGrid& grids, - const VprDeviceAnnotation& vpr_device_annotation, - const DeviceRRGSB& device_rr_gsb, - const RRGraphView& rr_graph_view, - const TileAnnotation& tile_annotation, - const CircuitLibrary& circuit_lib, - const CircuitModelId& sram_model, - const e_config_protocol_type& sram_orgz_type, - const bool& name_module_using_index, - const bool& perimeter_cb, - const bool& frame_view, const bool& verbose); +int build_tile_modules( + ModuleManager& module_manager, DecoderLibrary& decoder_lib, + const FabricTile& fabric_tile, const DeviceGrid& grids, + const VprDeviceAnnotation& vpr_device_annotation, + const DeviceRRGSB& device_rr_gsb, const RRGraphView& rr_graph_view, + const TileAnnotation& tile_annotation, const CircuitLibrary& circuit_lib, + const CircuitModelId& sram_model, + const e_config_protocol_type& sram_orgz_type, + const bool& name_module_using_index, const bool& perimeter_cb, + const bool& frame_view, const bool& verbose); } /* end namespace openfpga */ diff --git a/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp b/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp index 2e7a33182..d25a9af72 100644 --- a/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp +++ b/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp @@ -261,11 +261,15 @@ static vtr::Matrix add_top_module_connection_block_instances( * We will skip those modules */ const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy); - VTR_LOGV(verbose, "Try to add %s connnection block at (%lu, %lu)\n", cb_type == CHANX ? "X-" : "Y-", ix, iy); + VTR_LOGV(verbose, "Try to add %s connnection block at (%lu, %lu)\n", + cb_type == CHANX ? "X-" : "Y-", ix, iy); vtr::Point cb_coordinate(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); if (false == rr_gsb.is_cb_exist(cb_type)) { - VTR_LOGV(verbose, "Skip %s connnection block at (%lu, %lu) as it does not exist\n", cb_type == CHANX ? "X-" : "Y-", cb_coordinate.x(), cb_coordinate.y()); + VTR_LOGV( + verbose, + "Skip %s connnection block at (%lu, %lu) as it does not exist\n", + cb_type == CHANX ? "X-" : "Y-", cb_coordinate.x(), cb_coordinate.y()); continue; } /* If we use compact routing hierarchy, we should instanciate the unique @@ -297,7 +301,9 @@ static vtr::Matrix add_top_module_connection_block_instances( top_module, cb_module, cb_instance_ids[rr_gsb.get_cb_x(cb_type)][rr_gsb.get_cb_y(cb_type)], cb_instance_name); - VTR_LOGV(verbose, "Added %s connnection block '%s' (module '%s')\n", cb_type == CHANX ? "X-" : "Y-", cb_instance_name.c_str(), cb_module_name.c_str()); + VTR_LOGV(verbose, "Added %s connnection block '%s' (module '%s')\n", + cb_type == CHANX ? "X-" : "Y-", cb_instance_name.c_str(), + cb_module_name.c_str()); } } @@ -448,8 +454,7 @@ int build_top_module_fine_grained_child_instances( const ConfigProtocol& config_protocol, const CircuitModelId& sram_model, const bool& frame_view, const bool& compact_routing_hierarchy, const bool& duplicate_grid_pin, const FabricKey& fabric_key, - const bool& group_config_block, - const bool& verbose) { + const bool& group_config_block, const bool& verbose) { int status = CMD_EXEC_SUCCESS; std::map> cb_instance_ids; @@ -463,11 +468,11 @@ int build_top_module_fine_grained_child_instances( compact_routing_hierarchy); /* Add all the CBX and CBYs across the fabric */ cb_instance_ids[CHANX] = add_top_module_connection_block_instances( - module_manager, top_module, device_rr_gsb, CHANX, - compact_routing_hierarchy, verbose); + module_manager, top_module, device_rr_gsb, CHANX, compact_routing_hierarchy, + verbose); cb_instance_ids[CHANY] = add_top_module_connection_block_instances( - module_manager, top_module, device_rr_gsb, CHANY, - compact_routing_hierarchy, verbose); + module_manager, top_module, device_rr_gsb, CHANY, compact_routing_hierarchy, + verbose); /* Update I/O children list */ add_top_module_io_children(module_manager, top_module, grids, layer, diff --git a/openfpga/src/fabric/build_top_module_child_fine_grained_instance.h b/openfpga/src/fabric/build_top_module_child_fine_grained_instance.h index dd4f8e24d..604cce99b 100644 --- a/openfpga/src/fabric/build_top_module_child_fine_grained_instance.h +++ b/openfpga/src/fabric/build_top_module_child_fine_grained_instance.h @@ -44,8 +44,7 @@ int build_top_module_fine_grained_child_instances( const ConfigProtocol& config_protocol, const CircuitModelId& sram_model, const bool& frame_view, const bool& compact_routing_hierarchy, const bool& duplicate_grid_pin, const FabricKey& fabric_key, - const bool& group_config_block, - const bool& verbose); + const bool& group_config_block, const bool& verbose); } /* end namespace openfpga */ diff --git a/openfpga/src/fabric/build_top_module_connection.cpp b/openfpga/src/fabric/build_top_module_connection.cpp index d5d4e7aea..959532257 100644 --- a/openfpga/src/fabric/build_top_module_connection.cpp +++ b/openfpga/src/fabric/build_top_module_connection.cpp @@ -760,13 +760,15 @@ static void add_top_module_nets_connect_sb_and_cb( } if (RIGHT == side_manager.get_side() || TOP == side_manager.get_side()) { - /* Only for the condition where cbs are on perimeter, the neighbour cb will be invalid - * Bypass in such case on finding neighbour cbs + /* Only for the condition where cbs are on perimeter, the neighbour cb + * will be invalid Bypass in such case on finding neighbour cbs */ - if (TOP == side_manager.get_side() && instance_sb_coordinate.y() == device_rr_gsb.get_gsb_range().y()) { + if (TOP == side_manager.get_side() && + instance_sb_coordinate.y() == device_rr_gsb.get_gsb_range().y()) { continue; } - if (RIGHT == side_manager.get_side() && instance_sb_coordinate.x() == device_rr_gsb.get_gsb_range().x()) { + if (RIGHT == side_manager.get_side() && + instance_sb_coordinate.x() == device_rr_gsb.get_gsb_range().x()) { continue; } const RRGSB& adjacent_gsb = diff --git a/openfpga/src/fpga_verilog/fabric_verilog_options.cpp b/openfpga/src/fpga_verilog/fabric_verilog_options.cpp index 44da5e47c..23f6aef12 100644 --- a/openfpga/src/fpga_verilog/fabric_verilog_options.cpp +++ b/openfpga/src/fpga_verilog/fabric_verilog_options.cpp @@ -54,7 +54,9 @@ e_verilog_default_net_type FabricVerilogOption::default_net_type() const { return default_net_type_; } -bool FabricVerilogOption::constant_undriven_inputs() const { return constant_undriven_inputs_; } +bool FabricVerilogOption::constant_undriven_inputs() const { + return constant_undriven_inputs_; +} bool FabricVerilogOption::verbose_output() const { return verbose_output_; } diff --git a/openfpga/src/fpga_verilog/verilog_grid.cpp b/openfpga/src/fpga_verilog/verilog_grid.cpp index 7ccdd35d4..4da841564 100644 --- a/openfpga/src/fpga_verilog/verilog_grid.cpp +++ b/openfpga/src/fpga_verilog/verilog_grid.cpp @@ -233,10 +233,9 @@ static void rec_print_verilog_logical_tile( std::string(physical_pb_type->name) + " -----")); /* Write the verilog module */ - write_verilog_module_to_file(fp, module_manager, pb_module, - options.explicit_port_mapping(), - options.constant_undriven_inputs(), - options.default_net_type()); + write_verilog_module_to_file( + fp, module_manager, pb_module, options.explicit_port_mapping(), + options.constant_undriven_inputs(), options.default_net_type()); print_verilog_comment( fp, @@ -348,10 +347,9 @@ static void print_verilog_physical_tile_netlist( print_verilog_comment( fp, std::string("----- BEGIN Grid Verilog module: " + module_manager.module_name(grid_module) + " -----")); - write_verilog_module_to_file(fp, module_manager, grid_module, - options.explicit_port_mapping(), - options.constant_undriven_inputs(), - options.default_net_type()); + write_verilog_module_to_file( + fp, module_manager, grid_module, options.explicit_port_mapping(), + options.constant_undriven_inputs(), options.default_net_type()); print_verilog_comment( fp, std::string("----- END Grid Verilog module: " + diff --git a/openfpga/src/fpga_verilog/verilog_lut.cpp b/openfpga/src/fpga_verilog/verilog_lut.cpp index b20b1d07a..45dc0b862 100644 --- a/openfpga/src/fpga_verilog/verilog_lut.cpp +++ b/openfpga/src/fpga_verilog/verilog_lut.cpp @@ -63,8 +63,7 @@ void print_verilog_submodule_luts(const ModuleManager& module_manager, fp, module_manager, lut_module, options.explicit_port_mapping() || circuit_lib.dump_explicit_port_map(lut_model), - options.constant_undriven_inputs(), - options.default_net_type()); + options.constant_undriven_inputs(), options.default_net_type()); } /* Close the file handler */ diff --git a/openfpga/src/fpga_verilog/verilog_memory.cpp b/openfpga/src/fpga_verilog/verilog_memory.cpp index 0e0972269..99557e6b9 100644 --- a/openfpga/src/fpga_verilog/verilog_memory.cpp +++ b/openfpga/src/fpga_verilog/verilog_memory.cpp @@ -61,8 +61,7 @@ static void print_verilog_mux_memory_module( fp, module_manager, mem_module, options.explicit_port_mapping() || circuit_lib.dump_explicit_port_map(mux_model), - options.constant_undriven_inputs(), - options.default_net_type()); + options.constant_undriven_inputs(), options.default_net_type()); /* Add an empty line as a splitter */ fp << std::endl; @@ -85,8 +84,7 @@ static void print_verilog_mux_memory_module( fp, module_manager, feedthru_mem_module, options.explicit_port_mapping() || circuit_lib.dump_explicit_port_map(mux_model), - options.constant_undriven_inputs(), - options.default_net_type()); + options.constant_undriven_inputs(), options.default_net_type()); /* Add an empty line as a splitter */ fp << std::endl; @@ -243,10 +241,9 @@ void print_verilog_submodule_memories( for (ModuleId mem_group_module : module_manager.modules_by_usage( ModuleManager::e_module_usage_type::MODULE_CONFIG_GROUP)) { /* Write the module content in Verilog format */ - write_verilog_module_to_file(fp, module_manager, mem_group_module, - options.explicit_port_mapping(), - options.constant_undriven_inputs(), - options.default_net_type()); + write_verilog_module_to_file( + fp, module_manager, mem_group_module, options.explicit_port_mapping(), + options.constant_undriven_inputs(), options.default_net_type()); /* Add an empty line as a splitter */ fp << std::endl; diff --git a/openfpga/src/fpga_verilog/verilog_module_writer.cpp b/openfpga/src/fpga_verilog/verilog_module_writer.cpp index 3b52c2d87..c99a088c0 100644 --- a/openfpga/src/fpga_verilog/verilog_module_writer.cpp +++ b/openfpga/src/fpga_verilog/verilog_module_writer.cpp @@ -145,13 +145,10 @@ static BasicPort generate_verilog_port_for_module_net( * Verilog wire writter function will use the output of this function * to write up local wire declaration in Verilog format *******************************************************************/ -static void -find_verilog_module_local_undriven_wires( +static void find_verilog_module_local_undriven_wires( std::map>& local_wires, - const ModuleManager& module_manager, - const ModuleId& module_id, + const ModuleManager& module_manager, const ModuleId& module_id, const std::vector& port_type_blacklist) { - /* Local wires could also happen for undriven ports of child module */ for (const ModuleId& child : module_manager.child_modules(module_id)) { for (size_t instance : @@ -159,9 +156,11 @@ find_verilog_module_local_undriven_wires( for (const ModulePortId& child_port_id : module_manager.module_ports(child)) { BasicPort child_port = module_manager.module_port(child, child_port_id); - ModuleManager::e_module_port_type child_port_type = module_manager.port_type(child, child_port_id); + ModuleManager::e_module_port_type child_port_type = + module_manager.port_type(child, child_port_id); bool filter_out = false; - for (ModuleManager::e_module_port_type curr_port_type : port_type_blacklist) { + for (ModuleManager::e_module_port_type curr_port_type : + port_type_blacklist) { if (child_port_type == curr_port_type) { filter_out = true; break; @@ -267,7 +266,9 @@ find_verilog_module_local_wires(const ModuleManager& module_manager, } } - find_verilog_module_local_undriven_wires(local_wires, module_manager, module_id, std::vector()); + find_verilog_module_local_undriven_wires( + local_wires, module_manager, module_id, + std::vector()); return local_wires; } @@ -606,20 +607,22 @@ void write_verilog_module_to_file( /* Use constant to drive undriven local wires */ if (constant_local_undriven_wires) { std::vector blacklist = { - ModuleManager::e_module_port_type::MODULE_GLOBAL_PORT, - ModuleManager::e_module_port_type::MODULE_GPIN_PORT, - ModuleManager::e_module_port_type::MODULE_GPOUT_PORT, - ModuleManager::e_module_port_type::MODULE_GPIO_PORT, - ModuleManager::e_module_port_type::MODULE_INOUT_PORT, - ModuleManager::e_module_port_type::MODULE_OUTPUT_PORT, - ModuleManager::e_module_port_type::MODULE_CLOCK_PORT - }; + ModuleManager::e_module_port_type::MODULE_GLOBAL_PORT, + ModuleManager::e_module_port_type::MODULE_GPIN_PORT, + ModuleManager::e_module_port_type::MODULE_GPOUT_PORT, + ModuleManager::e_module_port_type::MODULE_GPIO_PORT, + ModuleManager::e_module_port_type::MODULE_INOUT_PORT, + ModuleManager::e_module_port_type::MODULE_OUTPUT_PORT, + ModuleManager::e_module_port_type::MODULE_CLOCK_PORT}; std::map> local_undriven_wires; - find_verilog_module_local_undriven_wires(local_undriven_wires, module_manager, module_id, blacklist); + find_verilog_module_local_undriven_wires( + local_undriven_wires, module_manager, module_id, blacklist); for (std::pair> port_group : local_undriven_wires) { for (const BasicPort& local_undriven_wire : port_group.second) { - print_verilog_wire_constant_values(fp, local_undriven_wire, std::vector(local_undriven_wire.get_width(), 0)); + print_verilog_wire_constant_values( + fp, local_undriven_wire, + std::vector(local_undriven_wire.get_width(), 0)); } } } diff --git a/openfpga/src/fpga_verilog/verilog_mux.cpp b/openfpga/src/fpga_verilog/verilog_mux.cpp index 38fcc0224..6f7a2a282 100644 --- a/openfpga/src/fpga_verilog/verilog_mux.cpp +++ b/openfpga/src/fpga_verilog/verilog_mux.cpp @@ -679,8 +679,7 @@ static void generate_verilog_mux_branch_module( fp, module_manager, mux_module, use_explicit_port_map || circuit_lib.dump_explicit_port_map(mux_model), - false, - default_net_type); + false, default_net_type); /* Add an empty line as a splitter */ fp << std::endl; } else { @@ -1424,8 +1423,7 @@ static void generate_verilog_mux_module( circuit_lib.dump_explicit_port_map(mux_model) || circuit_lib.dump_explicit_port_map( circuit_lib.pass_gate_logic_model(mux_model))), - false, - default_net_type); + false, default_net_type); /* Add an empty line as a splitter */ fp << std::endl; break; diff --git a/openfpga/src/fpga_verilog/verilog_routing.cpp b/openfpga/src/fpga_verilog/verilog_routing.cpp index 3826a2552..00bcaeda5 100644 --- a/openfpga/src/fpga_verilog/verilog_routing.cpp +++ b/openfpga/src/fpga_verilog/verilog_routing.cpp @@ -115,10 +115,9 @@ static void print_verilog_routing_connection_box_unique_module( VTR_ASSERT(true == module_manager.valid_module_id(cb_module)); /* Write the verilog module */ - write_verilog_module_to_file(fp, module_manager, cb_module, - options.explicit_port_mapping(), - options.constant_undriven_inputs(), - options.default_net_type()); + write_verilog_module_to_file( + fp, module_manager, cb_module, options.explicit_port_mapping(), + options.constant_undriven_inputs(), options.default_net_type()); /* Add an empty line as a splitter */ fp << std::endl; @@ -237,10 +236,9 @@ static void print_verilog_routing_switch_box_unique_module( VTR_ASSERT(true == module_manager.valid_module_id(sb_module)); /* Write the verilog module */ - write_verilog_module_to_file(fp, module_manager, sb_module, - options.explicit_port_mapping(), - options.constant_undriven_inputs(), - options.default_net_type()); + write_verilog_module_to_file( + fp, module_manager, sb_module, options.explicit_port_mapping(), + options.constant_undriven_inputs(), options.default_net_type()); /* Close file handler */ fp.close(); diff --git a/openfpga/src/fpga_verilog/verilog_shift_register_banks.cpp b/openfpga/src/fpga_verilog/verilog_shift_register_banks.cpp index 6d4707b1e..6f548d8ec 100644 --- a/openfpga/src/fpga_verilog/verilog_shift_register_banks.cpp +++ b/openfpga/src/fpga_verilog/verilog_shift_register_banks.cpp @@ -56,10 +56,9 @@ void print_verilog_submodule_shift_register_banks( for (const ModuleId& sr_module : blwl_sr_banks.bl_bank_unique_modules()) { VTR_ASSERT(true == module_manager.valid_module_id(sr_module)); /* Write the module content in Verilog format */ - write_verilog_module_to_file(fp, module_manager, sr_module, - options.explicit_port_mapping(), - options.constant_undriven_inputs(), - options.default_net_type()); + write_verilog_module_to_file( + fp, module_manager, sr_module, options.explicit_port_mapping(), + options.constant_undriven_inputs(), options.default_net_type()); /* Add an empty line as a splitter */ fp << std::endl; @@ -68,10 +67,9 @@ void print_verilog_submodule_shift_register_banks( for (const ModuleId& sr_module : blwl_sr_banks.wl_bank_unique_modules()) { VTR_ASSERT(true == module_manager.valid_module_id(sr_module)); /* Write the module content in Verilog format */ - write_verilog_module_to_file(fp, module_manager, sr_module, - options.explicit_port_mapping(), - options.constant_undriven_inputs(), - options.default_net_type()); + write_verilog_module_to_file( + fp, module_manager, sr_module, options.explicit_port_mapping(), + options.constant_undriven_inputs(), options.default_net_type()); /* Add an empty line as a splitter */ fp << std::endl; diff --git a/openfpga/src/fpga_verilog/verilog_tile.cpp b/openfpga/src/fpga_verilog/verilog_tile.cpp index f6b10beaf..a3bb1e992 100644 --- a/openfpga/src/fpga_verilog/verilog_tile.cpp +++ b/openfpga/src/fpga_verilog/verilog_tile.cpp @@ -58,10 +58,9 @@ static int print_verilog_tile_module_netlist( options.time_stamp()); /* Write the module content in Verilog format */ - write_verilog_module_to_file(fp, module_manager, tile_module, - options.explicit_port_mapping(), - options.constant_undriven_inputs(), - options.default_net_type()); + write_verilog_module_to_file( + fp, module_manager, tile_module, options.explicit_port_mapping(), + options.constant_undriven_inputs(), options.default_net_type()); /* Add an empty line as a splitter */ fp << std::endl; diff --git a/openfpga/src/fpga_verilog/verilog_top_module.cpp b/openfpga/src/fpga_verilog/verilog_top_module.cpp index 60ed91956..26268e4c1 100644 --- a/openfpga/src/fpga_verilog/verilog_top_module.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_module.cpp @@ -61,10 +61,9 @@ void print_verilog_core_module(NetlistManager& netlist_manager, options.time_stamp()); /* Write the module content in Verilog format */ - write_verilog_module_to_file(fp, module_manager, core_module, - options.explicit_port_mapping(), - options.constant_undriven_inputs(), - options.default_net_type()); + write_verilog_module_to_file( + fp, module_manager, core_module, options.explicit_port_mapping(), + options.constant_undriven_inputs(), options.default_net_type()); /* Add an empty line as a splitter */ fp << std::endl; @@ -128,10 +127,9 @@ void print_verilog_top_module(NetlistManager& netlist_manager, fp, std::string("Top-level Verilog module for FPGA"), options.time_stamp()); /* Write the module content in Verilog format */ - write_verilog_module_to_file(fp, module_manager, top_module, - options.explicit_port_mapping(), - options.constant_undriven_inputs(), - options.default_net_type()); + write_verilog_module_to_file( + fp, module_manager, top_module, options.explicit_port_mapping(), + options.constant_undriven_inputs(), options.default_net_type()); /* Add an empty line as a splitter */ fp << std::endl; From 201b2555e5cd10cb536b3db55abb6895bedef5d4 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 6 Jul 2024 12:15:08 -0700 Subject: [PATCH 52/91] [test] code format --- ...N4_tileable_IoSubtile_PerimeterCb_40nm.xml | 32 +++++++++---------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml index 2bab2cd89..e25a5a686 100644 --- a/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml +++ b/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml @@ -65,8 +65,8 @@ - - + + fpga_input[0:1].inpad fpga_input[2:3].inpad @@ -78,8 +78,8 @@ - - + + fpga_output[0:0].outpad fpga_output[1:1].outpad @@ -94,9 +94,9 @@ fpga_input[0:1].inpad - + fpga_input[2:3].inpad - + @@ -107,9 +107,9 @@ fpga_output[0:0].outpad - + fpga_output[1:1].outpad - + @@ -121,10 +121,10 @@ - + fpga_input[0:1].inpad fpga_input[2:3].inpad - + @@ -134,10 +134,10 @@ - + fpga_output[0:0].outpad fpga_output[1:1].outpad - + @@ -149,9 +149,9 @@ - + fpga_input[0:1].inpad - + fpga_input[2:3].inpad @@ -162,9 +162,9 @@ - + fpga_output[0:0].outpad - + fpga_output[1:1].outpad From 91f8bb584137d87a2a93365388cf7af989cc1a99 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 7 Jul 2024 13:40:01 -0700 Subject: [PATCH 53/91] [doc] update figures for ecb --- .../figures/ecb_allowed_direct_connection.png | Bin 112293 -> 99353 bytes ...d_direct_connection_inner_tile_example.png | Bin 107355 -> 111180 bytes ...d_direct_connection_inter_tile_example.png | Bin 112800 -> 100259 bytes .../ecb_forbid_direct_connection_example.png | Bin 116620 -> 122110 bytes 4 files changed, 0 insertions(+), 0 deletions(-) diff --git a/docs/source/manual/arch_lang/figures/ecb_allowed_direct_connection.png b/docs/source/manual/arch_lang/figures/ecb_allowed_direct_connection.png index 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[PATCH 54/91] [test] fixed a bug on ecb support --- .../tasks/basic_tests/k4_series/k4n4_ecb/config/task.conf | 2 +- ...gzBr_40nm.xml => k4_N4_ecb_tileable_TileOrgzBl_40nm.xml} | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) rename openfpga_flow/vpr_arch/{k4_N4_ecb_tileable_TileOrgzBr_40nm.xml => k4_N4_ecb_tileable_TileOrgzBl_40nm.xml} (99%) diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_ecb/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_ecb/config/task.conf index 87f77596d..035b92ed7 100644 --- a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_ecb/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_ecb/config/task.conf @@ -22,7 +22,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio openfpga_vpr_device_layout=2x2 [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_ecb_tileable_TileOrgzBr_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_ecb_tileable_TileOrgzBl_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif diff --git a/openfpga_flow/vpr_arch/k4_N4_ecb_tileable_TileOrgzBr_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_ecb_tileable_TileOrgzBl_40nm.xml similarity index 99% rename from openfpga_flow/vpr_arch/k4_N4_ecb_tileable_TileOrgzBr_40nm.xml rename to openfpga_flow/vpr_arch/k4_N4_ecb_tileable_TileOrgzBl_40nm.xml index 4597207bb..c9899d852 100644 --- a/openfpga_flow/vpr_arch/k4_N4_ecb_tileable_TileOrgzBr_40nm.xml +++ b/openfpga_flow/vpr_arch/k4_N4_ecb_tileable_TileOrgzBl_40nm.xml @@ -65,10 +65,10 @@ - clb.clk - clb.I2[0:3] clb.I3[0:3] clb.O[2:3] + clb.clk + clb.I2[0:3] clb.I3[0:3] clb.O[2:3] - clb.I0[0:3] clb.I1[0:3] clb.O[0:1] + clb.I0[0:3] clb.I1[0:3] clb.O[0:1] From 4da5150a2631ab6b9ad89d98804233fb8342d9bd Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 7 Jul 2024 14:20:26 -0700 Subject: [PATCH 55/91] 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z3onz=nI*9;=chfBzPJJ-;DPq}E8nzZ@l7+#wZqmX{q*^X3sZUr`a_@kZ{H@thwEs3Uhf=2Ys@ Date: Sun, 7 Jul 2024 14:57:05 -0700 Subject: [PATCH 56/91] [core] now support perimeter cb in programmable clock network arch --- .../src/annotation/append_clock_rr_graph.cpp | 48 +++++++++++++++---- 1 file changed, 39 insertions(+), 9 deletions(-) diff --git a/openfpga/src/annotation/append_clock_rr_graph.cpp b/openfpga/src/annotation/append_clock_rr_graph.cpp index ffe49e146..e9e690d11 100644 --- a/openfpga/src/annotation/append_clock_rr_graph.cpp +++ b/openfpga/src/annotation/append_clock_rr_graph.cpp @@ -49,9 +49,16 @@ static size_t estimate_clock_rr_graph_num_nodes(const DeviceGrid& grids, const bool& through_channel, const ClockNetwork& clk_ntwk) { size_t num_nodes = 0; + vtr::Rect chanx_bb(1, 0, grids.width() - 1, grids.height() - 1); + if (perimeter_cb) { + chanx_bb.set_xmin(0); + chanx_bb.set_xmax(grids.width()); + chanx_bb.set_ymin(0); + chanx_bb.set_ymax(grids.height()); + } /* Check the number of CHANX nodes required */ - for (size_t iy = 0; iy < grids.height() - 1; ++iy) { - for (size_t ix = 1; ix < grids.width() - 1; ++ix) { + for (size_t iy = chanx_bb.ymin(); iy < chanx_bb.ymax(); ++iy) { + for (size_t ix = chanx_bb.xmin(); ix < chanx_bb.xmax(); ++ix) { vtr::Point chanx_coord(ix, iy); /* Bypass if the routing channel does not exist when through channels are * not allowed */ @@ -64,8 +71,16 @@ static size_t estimate_clock_rr_graph_num_nodes(const DeviceGrid& grids, } } - for (size_t ix = 0; ix < grids.width() - 1; ++ix) { - for (size_t iy = 1; iy < grids.height() - 1; ++iy) { + vtr::Rect chany_bb(0, 1, grids.width() - 1, grids.height() - 1); + if (perimeter_cb) { + chany_bb.set_xmin(0); + chany_bb.set_xmax(grids.width()); + chany_bb.set_ymin(0); + chany_bb.set_ymax(grids.height()); + } + + for (size_t ix = chany_bb.xmin(); ix < chany_bb.xmax(); ++ix) { + for (size_t iy = chany_bb.xmin(); iy < chany_bb.ymax(); ++iy) { vtr::Point chany_coord(ix, iy); /* Bypass if the routing channel does not exist when through channel are * not allowed */ @@ -159,9 +174,16 @@ static void add_rr_graph_clock_nodes( clk_ntwk.num_trees(), clk_ntwk.max_tree_depth(), clk_ntwk.max_tree_width()); + vtr::Rect chanx_bb(1, 0, grids.width() - 1, grids.height() - 1); + if (perimeter_cb) { + chanx_bb.set_xmin(0); + chanx_bb.set_xmax(grids.width()); + chanx_bb.set_ymin(0); + chanx_bb.set_ymax(grids.height()); + } /* Add X-direction clock nodes */ - for (size_t iy = 0; iy < grids.height() - 1; ++iy) { - for (size_t ix = 1; ix < grids.width() - 1; ++ix) { + for (size_t iy = chanx_bb.ymin(); iy < chanx_bb.ymax(); ++iy) { + for (size_t ix = chanx_bb.xmin(); ix < chanx_bb.xmax(); ++ix) { vtr::Point chanx_coord(ix, iy); /* Bypass if the routing channel does not exist when through channels are * not allowed */ @@ -182,8 +204,15 @@ static void add_rr_graph_clock_nodes( 1, 0, ClockTreeId(0), ClockLevelId(0), ClockTreePinId(0), Direction::INC))); /* Add Y-direction clock nodes */ - for (size_t ix = 0; ix < grids.width() - 1; ++ix) { - for (size_t iy = 1; iy < grids.height() - 1; ++iy) { + vtr::Rect chany_bb(0, 1, grids.width() - 1, grids.height() - 1); + if (perimeter_cb) { + chany_bb.set_xmin(0); + chany_bb.set_xmax(grids.width()); + chany_bb.set_ymin(0); + chany_bb.set_ymax(grids.height()); + } + for (size_t ix = chany_bb.xmin(); ix < chany_bb.xmax(); ++ix) { + for (size_t iy = chany_bb.xmin(); iy < chany_bb.ymax(); ++iy) { vtr::Point chany_coord(ix, iy); /* Bypass if the routing channel does not exist when through channel are * not allowed */ @@ -780,7 +809,8 @@ static void add_rr_graph_clock_edges( *******************************************************************/ int append_clock_rr_graph(DeviceContext& vpr_device_ctx, RRClockSpatialLookup& clk_rr_lookup, - const ClockNetwork& clk_ntwk, const bool& verbose) { + const ClockNetwork& clk_ntwk, + const bool& verbose) { vtr::ScopedStartFinishTimer timer( "Appending programmable clock network to routing resource graph"); From db12532eb8644f29e450f3fb8a8ed992e70cd3d9 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 7 Jul 2024 21:41:39 -0700 Subject: [PATCH 57/91] [test] typo --- .../homo_fabric_tile_ecb_2x2_preconfig/config/task.conf | 2 +- .../homo_fabric_tile_ecb_2x2_preconfig/config/tile_config.xml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_ecb_2x2_preconfig/config/task.conf b/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_ecb_2x2_preconfig/config/task.conf index 8f1b5aa53..08aca9064 100644 --- a/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_ecb_2x2_preconfig/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_ecb_2x2_preconfig/config/task.conf @@ -27,7 +27,7 @@ openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml openfpga_verilog_testbench_options=--explicit_port_mapping [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_ecb_tileable_TileOrgzBr_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_ecb_tileable_TileOrgzBl_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_ecb_2x2_preconfig/config/tile_config.xml b/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_ecb_2x2_preconfig/config/tile_config.xml index 1a1f3f6e8..026c140be 100644 --- a/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_ecb_2x2_preconfig/config/tile_config.xml +++ b/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_ecb_2x2_preconfig/config/tile_config.xml @@ -1 +1 @@ - + From 1a5e2392fcc92aab0050cbb52ee8a13e12a9d861 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 7 Jul 2024 22:32:13 -0700 Subject: [PATCH 58/91] [test] add a new testcase to validate clock network when perimeter cb is on --- ...nm_ClkNtwk_registerable_io_cc_openfpga.xml | 201 +++++++++ .../regression_test_scripts/basic_reg_test.sh | 1 + .../config/clk_arch_1clk_2layer.xml | 22 + .../config/task.conf | 42 ++ .../config/tile_config.xml | 1 + ...rimeterCb_ClkNtwk_registerable_io_40nm.xml | 411 ++++++++++++++++++ 6 files changed, 678 insertions(+) create mode 100644 openfpga_flow/openfpga_arch/k4_N4_40nm_ClkNtwk_registerable_io_cc_openfpga.xml create mode 100644 openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/clk_arch_1clk_2layer.xml create mode 100644 openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/task.conf create mode 100644 openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/tile_config.xml create mode 100644 openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_ClkNtwk_registerable_io_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_ClkNtwk_registerable_io_cc_openfpga.xml new file mode 100644 index 000000000..cdb96e29b --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_ClkNtwk_registerable_io_cc_openfpga.xml @@ -0,0 +1,201 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index cdb93ee16..f4b872def 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -197,6 +197,7 @@ run-task basic_tests/tile_organization/homo_fabric_tile $@ run-task basic_tests/tile_organization/homo_fabric_tile_bl $@ echo -e "Testing tile grouping on a homogeneous FPGA fabric (Preconfigured testbench)"; run-task basic_tests/tile_organization/fabric_tile_global_tile_clock_io_subtile $@ +run-task basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile $@ run-task basic_tests/tile_organization/homo_fabric_tile_preconfig $@ run-task basic_tests/tile_organization/homo_fabric_tile_2x2_preconfig $@ run-task basic_tests/tile_organization/homo_fabric_tile_4x4_preconfig $@ diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/clk_arch_1clk_2layer.xml b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/clk_arch_1clk_2layer.xml new file mode 100644 index 000000000..c45687e52 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/clk_arch_1clk_2layer.xml @@ -0,0 +1,22 @@ + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/task.conf b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/task.conf new file mode 100644 index 000000000..f7c94606f --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/task.conf @@ -0,0 +1,42 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/group_tile_clkntwk_preconfig_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_ClkNtwk_registerable_io_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_vpr_extra_options= +openfpga_pb_pin_fixup_command= +openfpga_vpr_device=2x2 +openfpga_vpr_route_chan_width=20 +openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml +openfpga_verilog_testbench_options=--explicit_port_mapping +openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_2layer.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_pipelined/and2_pipelined.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = and2_pipelined + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/tile_config.xml b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/tile_config.xml new file mode 100644 index 000000000..1a1f3f6e8 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/tile_config.xml @@ -0,0 +1 @@ + diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml new file mode 100644 index 000000000..de6fe0ac8 --- /dev/null +++ b/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml @@ -0,0 +1,411 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad[0:1] io.inpad[0:1] + + io.outpad[2:3] io.inpad[2:3] io.clk + io.outpad[4:5] io.inpad[4:5] + + + + + + + + + + + + + + + + io.outpad[0:0] io.inpad[0:0] io.clk + + io.outpad[1:1] io.inpad[1:1] + io.outpad[2:2] io.inpad[2:2] + + + + + + + + + + + + + + + + io.outpad[0:1] io.inpad[0:1] io.clk + + io.outpad[2:2] io.inpad[2:2] + io.outpad[3:4] io.inpad[3:4] + + + + + + + + + + + + + + + + io.outpad[0:1] io.inpad[0:1] io.clk + + io.outpad[2:3] io.inpad[2:3] + io.outpad[4:5] io.inpad[4:5] + + + + + + + + + + + + + + + + clb.I[0:4] clb.O[0:1] + clb.clk + clb.I[5:9] clb.O[2:3] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 + 1 + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From f784e583831f2114c682e903a31cc51f35abe680 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 7 Jul 2024 22:33:45 -0700 Subject: [PATCH 59/91] [test] typo --- ..._tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml index de6fe0ac8..b028e180a 100644 --- a/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml +++ b/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml @@ -143,8 +143,8 @@ - - + + @@ -153,8 +153,8 @@ - - + + From 57a378ae59ccf4c9dffa5088181de30ae7c375e7 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 7 Jul 2024 22:35:14 -0700 Subject: [PATCH 60/91] [test] typo --- .../k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml index b028e180a..0f086c0bc 100644 --- a/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml +++ b/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml @@ -94,7 +94,7 @@ io.outpad[0:1] io.inpad[0:1] io.clk io.outpad[2:2] io.inpad[2:2] - io.outpad[3:4] io.inpad[3:4] + io.outpad[3:3] io.inpad[3:3] From 686cd761b72ca015280827559d056835844d4e2b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 7 Jul 2024 22:48:21 -0700 Subject: [PATCH 61/91] [test] debugging --- ...rimeterCb_ClkNtwk_registerable_io_40nm.xml | 37 ++++++++----------- 1 file changed, 16 insertions(+), 21 deletions(-) diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml index 0f086c0bc..c026c93b3 100644 --- a/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml +++ b/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml @@ -34,15 +34,10 @@ - - - - - - + @@ -53,15 +48,15 @@ - io.outpad[0:1] io.inpad[0:1] + io_top[0:1].outpad[0:0] io_top[0:1].inpad[0:0] - io.outpad[2:3] io.inpad[2:3] io.clk - io.outpad[4:5] io.inpad[4:5] + io_top[2:3].outpad[0:0] io_top[2:3].inpad[0:0] io_top[0:5].clk[0:0] + io_top[4:5].outpad[0:0] io_top[4:5].inpad[0:0] - + @@ -72,15 +67,15 @@ - io.outpad[0:0] io.inpad[0:0] io.clk + io_right[0:0].outpad[0:0] io_right[0:0].inpad[0:0] io_right[0:2].clk[0:0] - io.outpad[1:1] io.inpad[1:1] - io.outpad[2:2] io.inpad[2:2] + io_right[1:1].outpad[0:0] io_right[1:1].inpad[0:0] + io_right[2:2].outpad[0:0] io_right[2:2].inpad[0:0] - + @@ -91,15 +86,15 @@ - io.outpad[0:1] io.inpad[0:1] io.clk + io_bottom[0:1].outpad[0:0] io_bottom[0:1].inpad[0:0] io_bottom[0:3].clk[0:0] - io.outpad[2:2] io.inpad[2:2] - io.outpad[3:3] io.inpad[3:3] + io_bottom[2:2].outpad[0:0] io_bottom[2:2].inpad[0:0] + io_bottom[3:3].outpad[0:0] io_bottom[3:3].inpad[0:0] - + @@ -110,10 +105,10 @@ - io.outpad[0:1] io.inpad[0:1] io.clk + io_left[0:1].outpad[0:0] io_left[0:1].inpad[0:0] io_left[0:5].clk[0:0] - io.outpad[2:3] io.inpad[2:3] - io.outpad[4:5] io.inpad[4:5] + io_left[2:3].outpad[0:0] io_left[2:3].inpad[0:0] + io_left[4:5].outpad[0:0] io_left[4:5].inpad[0:0] From b0851a62998b4756970ec33a8c57f6c1f7248b83 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 7 Jul 2024 23:05:37 -0700 Subject: [PATCH 62/91] [test] debugging --- ...rimeterCb_ClkNtwk_registerable_io_40nm.xml | 37 ++++++++++--------- 1 file changed, 19 insertions(+), 18 deletions(-) diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml index c026c93b3..6c1cb8d63 100644 --- a/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml +++ b/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml @@ -44,14 +44,14 @@ - + io_top[0:1].outpad[0:0] io_top[0:1].inpad[0:0] - io_top[2:3].outpad[0:0] io_top[2:3].inpad[0:0] io_top[0:5].clk[0:0] - io_top[4:5].outpad[0:0] io_top[4:5].inpad[0:0] + io_top[0:5].clk[0:0] + io_top[2:5].outpad[0:0] io_top[2:5].inpad[0:0] @@ -63,7 +63,7 @@ - + @@ -82,33 +82,33 @@ - + io_bottom[0:1].outpad[0:0] io_bottom[0:1].inpad[0:0] io_bottom[0:3].clk[0:0] - io_bottom[2:2].outpad[0:0] io_bottom[2:2].inpad[0:0] - io_bottom[3:3].outpad[0:0] io_bottom[3:3].inpad[0:0] + io_bottom[2:3].outpad[0:0] io_bottom[2:3].inpad[0:0] + - + - + - io_left[0:1].outpad[0:0] io_left[0:1].inpad[0:0] io_left[0:5].clk[0:0] + io_left[0:1].outpad[0:0] io_left[0:1].inpad[0:0] io_left[0:3].clk[0:0] - io_left[2:3].outpad[0:0] io_left[2:3].inpad[0:0] - io_left[4:5].outpad[0:0] io_left[4:5].inpad[0:0] + + io_left[2:3].outpad[0:0] io_left[2:3].inpad[0:0] @@ -120,14 +120,15 @@ - + - - clb.I[0:4] clb.O[0:1] - clb.clk - clb.I[5:9] clb.O[2:3] - + + clb.I[0:1] clb.O[0:0] + clb.I[2:3] clb.O[1:1] clb.clk + clb.I[4:6] clb.O[2:2] + clb.I[7:9] clb.O[3:3] + From ff56139a53e7f26811632cc2387b14f313611a10 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 7 Jul 2024 23:07:51 -0700 Subject: [PATCH 63/91] [test] debugging --- .../k4_N4_40nm_ClkNtwk_registerable_io_cc_openfpga.xml | 5 ++++- .../config/clk_arch_1clk_2layer.xml | 7 +++++-- .../fabric_tile_clkntwk_io_subtile/config/task.conf | 2 +- ...4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml | 4 ++-- 4 files changed, 12 insertions(+), 6 deletions(-) diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_ClkNtwk_registerable_io_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_ClkNtwk_registerable_io_cc_openfpga.xml index cdb96e29b..e0c4966c5 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_ClkNtwk_registerable_io_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_ClkNtwk_registerable_io_cc_openfpga.xml @@ -175,7 +175,10 @@ - + + + + diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/clk_arch_1clk_2layer.xml b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/clk_arch_1clk_2layer.xml index c45687e52..4c4c38bb8 100644 --- a/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/clk_arch_1clk_2layer.xml +++ b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/clk_arch_1clk_2layer.xml @@ -4,7 +4,7 @@ - + @@ -16,7 +16,10 @@ - + + + + diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/task.conf b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/task.conf index f7c94606f..f9c6517ab 100644 --- a/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/task.conf @@ -22,7 +22,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio openfpga_vpr_extra_options= openfpga_pb_pin_fixup_command= openfpga_vpr_device=2x2 -openfpga_vpr_route_chan_width=20 +openfpga_vpr_route_chan_width=40 openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml openfpga_verilog_testbench_options=--explicit_port_mapping openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_2layer.xml diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml index 6c1cb8d63..09a0af616 100644 --- a/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml +++ b/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml @@ -206,12 +206,12 @@ - + 1 1 1 - + 1 1 1 1 1 1 1 1 1 From 8449da0143813cb01ffb47afa962fd1cbd67a6d2 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 7 Jul 2024 23:36:13 -0700 Subject: [PATCH 64/91] [core] typo --- openfpga/src/annotation/append_clock_rr_graph.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openfpga/src/annotation/append_clock_rr_graph.cpp b/openfpga/src/annotation/append_clock_rr_graph.cpp index e9e690d11..e60aaa50d 100644 --- a/openfpga/src/annotation/append_clock_rr_graph.cpp +++ b/openfpga/src/annotation/append_clock_rr_graph.cpp @@ -80,7 +80,7 @@ static size_t estimate_clock_rr_graph_num_nodes(const DeviceGrid& grids, } for (size_t ix = chany_bb.xmin(); ix < chany_bb.xmax(); ++ix) { - for (size_t iy = chany_bb.xmin(); iy < chany_bb.ymax(); ++iy) { + for (size_t iy = chany_bb.ymin(); iy < chany_bb.ymax(); ++iy) { vtr::Point chany_coord(ix, iy); /* Bypass if the routing channel does not exist when through channel are * not allowed */ @@ -212,7 +212,7 @@ static void add_rr_graph_clock_nodes( chany_bb.set_ymax(grids.height()); } for (size_t ix = chany_bb.xmin(); ix < chany_bb.xmax(); ++ix) { - for (size_t iy = chany_bb.xmin(); iy < chany_bb.ymax(); ++iy) { + for (size_t iy = chany_bb.ymin(); iy < chany_bb.ymax(); ++iy) { vtr::Point chany_coord(ix, iy); /* Bypass if the routing channel does not exist when through channel are * not allowed */ From cdd477ad80fbff3e749d378a7b5e8bbf5a14ea96 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 8 Jul 2024 10:14:39 -0700 Subject: [PATCH 65/91] [core] remove restrictions on cb clock nodes --- openfpga/src/annotation/append_clock_rr_graph.cpp | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/openfpga/src/annotation/append_clock_rr_graph.cpp b/openfpga/src/annotation/append_clock_rr_graph.cpp index e60aaa50d..b7b82c269 100644 --- a/openfpga/src/annotation/append_clock_rr_graph.cpp +++ b/openfpga/src/annotation/append_clock_rr_graph.cpp @@ -194,15 +194,9 @@ static void add_rr_graph_clock_nodes( add_rr_graph_block_clock_nodes( rr_graph_builder, clk_rr_lookup, rr_graph_view, clk_ntwk, layer, chanx_coord, CHANX, CHANX_COST_INDEX_START, verbose); - VTR_ASSERT(rr_graph_view.valid_node( - clk_rr_lookup.find_node(1, 0, ClockTreeId(0), ClockLevelId(0), - ClockTreePinId(0), Direction::INC))); } } - VTR_ASSERT(rr_graph_view.valid_node(clk_rr_lookup.find_node( - 1, 0, ClockTreeId(0), ClockLevelId(0), ClockTreePinId(0), Direction::INC))); - /* Add Y-direction clock nodes */ vtr::Rect chany_bb(0, 1, grids.width() - 1, grids.height() - 1); if (perimeter_cb) { @@ -224,13 +218,8 @@ static void add_rr_graph_clock_nodes( rr_graph_builder, clk_rr_lookup, rr_graph_view, clk_ntwk, layer, chany_coord, CHANY, CHANX_COST_INDEX_START + rr_graph_view.num_rr_segments(), verbose); - VTR_ASSERT(rr_graph_view.valid_node( - clk_rr_lookup.find_node(1, 0, ClockTreeId(0), ClockLevelId(0), - ClockTreePinId(0), Direction::INC))); } } - VTR_ASSERT(rr_graph_view.valid_node(clk_rr_lookup.find_node( - 1, 0, ClockTreeId(0), ClockLevelId(0), ClockTreePinId(0), Direction::INC))); } /******************************************************************** From 5c9c4d93c5636d854dc01945919018eeabb1c48e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 8 Jul 2024 10:46:47 -0700 Subject: [PATCH 66/91] [core] typo --- openfpga/src/annotation/route_clock_rr_graph.cpp | 4 ++-- .../config/clk_arch_1clk_2layer.xml | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/openfpga/src/annotation/route_clock_rr_graph.cpp b/openfpga/src/annotation/route_clock_rr_graph.cpp index 0be7cdf84..207b83d0e 100644 --- a/openfpga/src/annotation/route_clock_rr_graph.cpp +++ b/openfpga/src/annotation/route_clock_rr_graph.cpp @@ -186,8 +186,6 @@ static int route_spine_taps( const std::map& tree2clk_pin_map, const ClockNetwork& clk_ntwk, const ClockTreeId& clk_tree, const ClockSpineId& ispine, const ClockTreePinId& ipin, const bool& verbose) { - std::vector> spine_coords = - clk_ntwk.spine_coordinates(ispine); size_t spine_tap_cnt = 0; /* Route the spine-to-IPIN connections (only for the last level) */ if (clk_ntwk.is_last_level(ispine)) { @@ -195,6 +193,8 @@ static int route_spine_taps( "Routing clock taps of spine '%s' for pin '%d' of tree '%s'...\n", clk_ntwk.spine_name(ispine).c_str(), size_t(ipin), clk_ntwk.tree_name(clk_tree).c_str()); + std::vector> spine_coords = + clk_ntwk.spine_coordinates(ispine); /* Connect to any fan-out node which is IPIN */ for (size_t icoord = 0; icoord < spine_coords.size(); ++icoord) { vtr::Point src_coord = spine_coords[icoord]; diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/clk_arch_1clk_2layer.xml b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/clk_arch_1clk_2layer.xml index 4c4c38bb8..453d0b5d0 100644 --- a/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/clk_arch_1clk_2layer.xml +++ b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/clk_arch_1clk_2layer.xml @@ -8,8 +8,8 @@ - - + + From 48ae3691c429b58590ffb1ec89ae5d6901293f29 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 8 Jul 2024 10:57:54 -0700 Subject: [PATCH 67/91] [test] typo --- .../k4_N4_40nm_ClkNtwk_registerable_io_cc_openfpga.xml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_ClkNtwk_registerable_io_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_ClkNtwk_registerable_io_cc_openfpga.xml index e0c4966c5..f9d09c73e 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_ClkNtwk_registerable_io_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_ClkNtwk_registerable_io_cc_openfpga.xml @@ -173,7 +173,7 @@ - + From 6492d43a01148a6ef987c8283cd98f10419d5d60 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 8 Jul 2024 11:29:20 -0700 Subject: [PATCH 68/91] [test] add a new test to validate perimeter cb using global tile clock --- ...erimeterCb_registerable_io_cc_openfpga.xml | 204 ++++++++++++++++++ .../regression_test_scripts/basic_reg_test.sh | 1 + .../config/task.conf | 41 ++++ .../config/tile_config.xml | 1 + 4 files changed, 247 insertions(+) create mode 100644 openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_PerimeterCb_registerable_io_cc_openfpga.xml create mode 100644 openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_perimeter_cb_global_tile_clock/config/task.conf create mode 100644 openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_perimeter_cb_global_tile_clock/config/tile_config.xml diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_PerimeterCb_registerable_io_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_PerimeterCb_registerable_io_cc_openfpga.xml new file mode 100644 index 000000000..341bf52e2 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_PerimeterCb_registerable_io_cc_openfpga.xml @@ -0,0 +1,204 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index f4b872def..4e1f55602 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -197,6 +197,7 @@ run-task basic_tests/tile_organization/homo_fabric_tile $@ run-task basic_tests/tile_organization/homo_fabric_tile_bl $@ echo -e "Testing tile grouping on a homogeneous FPGA fabric (Preconfigured testbench)"; run-task basic_tests/tile_organization/fabric_tile_global_tile_clock_io_subtile $@ +run-task basic_tests/tile_organization/fabric_tile_perimeter_cb_global_tile_clock_io_subtile $@ run-task basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile $@ run-task basic_tests/tile_organization/homo_fabric_tile_preconfig $@ run-task basic_tests/tile_organization/homo_fabric_tile_2x2_preconfig $@ diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_perimeter_cb_global_tile_clock/config/task.conf b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_perimeter_cb_global_tile_clock/config/task.conf new file mode 100644 index 000000000..20efcfa2d --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_perimeter_cb_global_tile_clock/config/task.conf @@ -0,0 +1,41 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/group_tile_preconfig_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_PerimeterCb_registerable_io_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_vpr_extra_options= +openfpga_pb_pin_fixup_command= +openfpga_vpr_device=2x2 +openfpga_vpr_route_chan_width=40 +openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml +openfpga_verilog_testbench_options=--explicit_port_mapping + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_pipelined/and2_pipelined.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = and2_pipelined + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_perimeter_cb_global_tile_clock/config/tile_config.xml b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_perimeter_cb_global_tile_clock/config/tile_config.xml new file mode 100644 index 000000000..1a1f3f6e8 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_perimeter_cb_global_tile_clock/config/tile_config.xml @@ -0,0 +1 @@ + From 7bd60f5f7d6d42ee546f61937d0b4432f0854596 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 8 Jul 2024 12:39:54 -0700 Subject: [PATCH 69/91] [core] support perimeter cb when identify pins of I/Os tiles --- openfpga/src/base/openfpga_pb_pin_fixup.cpp | 2 +- openfpga/src/fabric/build_device_module.cpp | 4 +++- openfpga/src/fabric/build_top_module.cpp | 8 +++++--- openfpga/src/fabric/build_top_module.h | 4 +++- ...d_top_module_child_fine_grained_instance.cpp | 6 ++++-- ...ild_top_module_child_fine_grained_instance.h | 4 +++- .../build_top_module_child_tile_instance.cpp | 17 +++++++++-------- .../build_top_module_child_tile_instance.h | 1 + .../src/fabric/build_top_module_connection.cpp | 17 ++++++++++------- .../src/fabric/build_top_module_connection.h | 3 ++- .../src/utils/openfpga_physical_tile_utils.cpp | 9 ++++++--- .../src/utils/openfpga_physical_tile_utils.h | 2 +- 12 files changed, 48 insertions(+), 29 deletions(-) diff --git a/openfpga/src/base/openfpga_pb_pin_fixup.cpp b/openfpga/src/base/openfpga_pb_pin_fixup.cpp index 22bff36c4..e96e4d218 100644 --- a/openfpga/src/base/openfpga_pb_pin_fixup.cpp +++ b/openfpga/src/base/openfpga_pb_pin_fixup.cpp @@ -60,7 +60,7 @@ static void update_cluster_pin_with_post_routing_results( rr_node_type = IPIN; } std::vector pin_sides = - find_physical_tile_pin_side(physical_tile, physical_pin, border_side); + find_physical_tile_pin_side(physical_tile, physical_pin, border_side, device_ctx.arch->perimeter_cb); /* As some grid has height/width offset, we may not have the pin on any side */ if (0 == pin_sides.size()) { diff --git a/openfpga/src/fabric/build_device_module.cpp b/openfpga/src/fabric/build_device_module.cpp index a04e9e015..3ffa869e8 100644 --- a/openfpga/src/fabric/build_device_module.cpp +++ b/openfpga/src/fabric/build_device_module.cpp @@ -142,7 +142,9 @@ int build_device_module_graph( openfpga_ctx.arch().arch_direct, openfpga_ctx.arch().config_protocol, sram_model, fabric_tile, name_module_using_index, frame_view, compress_routing, duplicate_grid_pin, fabric_key, - generate_random_fabric_key, group_config_block, verbose); + generate_random_fabric_key, group_config_block, + vpr_device_ctx.arch->perimeter_cb, + verbose); if (CMD_EXEC_FATAL_ERROR == status) { return status; diff --git a/openfpga/src/fabric/build_top_module.cpp b/openfpga/src/fabric/build_top_module.cpp index bce676019..54fd54702 100644 --- a/openfpga/src/fabric/build_top_module.cpp +++ b/openfpga/src/fabric/build_top_module.cpp @@ -58,7 +58,9 @@ int build_top_module( const bool& name_module_using_index, const bool& frame_view, const bool& compact_routing_hierarchy, const bool& duplicate_grid_pin, const FabricKey& fabric_key, const bool& generate_random_fabric_key, - const bool& group_config_block, const bool& verbose) { + const bool& group_config_block, + const bool& perimeter_cb, + const bool& verbose) { vtr::ScopedStartFinishTimer timer("Build FPGA fabric module"); int status = CMD_EXEC_SUCCESS; @@ -79,7 +81,7 @@ int build_top_module( rr_clock_lookup, vpr_device_annotation, grids, layer, tile_annotation, rr_graph, device_rr_gsb, tile_direct, arch_direct, config_protocol, sram_model, frame_view, compact_routing_hierarchy, duplicate_grid_pin, - fabric_key, group_config_block, verbose); + fabric_key, group_config_block, perimeter_cb, verbose); } else { /* Build the tile instances under the top module */ status = build_top_module_tile_child_instances( @@ -87,7 +89,7 @@ int build_top_module( rr_clock_lookup, vpr_device_annotation, grids, layer, tile_annotation, rr_graph, device_rr_gsb, tile_direct, arch_direct, fabric_tile, config_protocol, sram_model, fabric_key, group_config_block, - name_module_using_index, frame_view, verbose); + name_module_using_index, perimeter_cb, frame_view, verbose); } if (status != CMD_EXEC_SUCCESS) { diff --git a/openfpga/src/fabric/build_top_module.h b/openfpga/src/fabric/build_top_module.h index ee9d346d2..75c3649eb 100644 --- a/openfpga/src/fabric/build_top_module.h +++ b/openfpga/src/fabric/build_top_module.h @@ -45,7 +45,9 @@ int build_top_module( const bool& name_module_using_index, const bool& frame_view, const bool& compact_routing_hierarchy, const bool& duplicate_grid_pin, const FabricKey& fabric_key, const bool& generate_random_fabric_key, - const bool& group_config_block, const bool& verbose); + const bool& group_config_block, + const bool& perimeter_cb, + const bool& verbose); } /* end namespace openfpga */ diff --git a/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp b/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp index d25a9af72..7e3fcfa2f 100644 --- a/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp +++ b/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp @@ -454,7 +454,9 @@ int build_top_module_fine_grained_child_instances( const ConfigProtocol& config_protocol, const CircuitModelId& sram_model, const bool& frame_view, const bool& compact_routing_hierarchy, const bool& duplicate_grid_pin, const FabricKey& fabric_key, - const bool& group_config_block, const bool& verbose) { + const bool& group_config_block, + const bool& perimeter_cb, + const bool& verbose) { int status = CMD_EXEC_SUCCESS; std::map> cb_instance_ids; @@ -501,7 +503,7 @@ int build_top_module_fine_grained_child_instances( status = add_top_module_global_ports_from_grid_modules( module_manager, top_module, tile_annotation, vpr_device_annotation, grids, layer, rr_graph, device_rr_gsb, cb_instance_ids, grid_instance_ids, - clk_ntwk, rr_clock_lookup); + clk_ntwk, rr_clock_lookup, perimeter_cb); if (CMD_EXEC_FATAL_ERROR == status) { return status; } diff --git a/openfpga/src/fabric/build_top_module_child_fine_grained_instance.h b/openfpga/src/fabric/build_top_module_child_fine_grained_instance.h index 604cce99b..394f7a2df 100644 --- a/openfpga/src/fabric/build_top_module_child_fine_grained_instance.h +++ b/openfpga/src/fabric/build_top_module_child_fine_grained_instance.h @@ -44,7 +44,9 @@ int build_top_module_fine_grained_child_instances( const ConfigProtocol& config_protocol, const CircuitModelId& sram_model, const bool& frame_view, const bool& compact_routing_hierarchy, const bool& duplicate_grid_pin, const FabricKey& fabric_key, - const bool& group_config_block, const bool& verbose); + const bool& group_config_block, + const bool& perimeter_cb, + const bool& verbose); } /* end namespace openfpga */ diff --git a/openfpga/src/fabric/build_top_module_child_tile_instance.cpp b/openfpga/src/fabric/build_top_module_child_tile_instance.cpp index 0ad953f68..bf12dabc6 100644 --- a/openfpga/src/fabric/build_top_module_child_tile_instance.cpp +++ b/openfpga/src/fabric/build_top_module_child_tile_instance.cpp @@ -1295,7 +1295,7 @@ static int build_top_module_global_net_for_given_tile_module( const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, const size_t& layer, const vtr::Point& grid_coordinate, const e_side& border_side, const vtr::Matrix& tile_instance_ids, - const FabricTile& fabric_tile) { + const FabricTile& fabric_tile, const bool& perimeter_cb) { /* Get the tile module and instance */ FabricTileId curr_fabric_tile_id = fabric_tile.find_tile_by_pb_coordinate(grid_coordinate); @@ -1392,7 +1392,7 @@ static int build_top_module_global_net_for_given_tile_module( size_t grid_pin_height = physical_tile->pin_height_offset[grid_pin_index]; std::vector pin_sides = find_physical_tile_pin_side( - physical_tile, grid_pin_index, border_side); + physical_tile, grid_pin_index, border_side, perimeter_cb); BasicPort grid_pin_info = vpr_device_annotation.physical_tile_pin_port_info(physical_tile, @@ -1452,7 +1452,7 @@ static int build_top_module_global_net_from_tile_modules( const TileGlobalPortId& tile_global_port, const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, const size_t& layer, const vtr::Matrix& tile_instance_ids, - const FabricTile& fabric_tile) { + const FabricTile& fabric_tile, const bool& perimeter_cb) { int status = CMD_EXEC_SUCCESS; std::map>> io_coordinates = @@ -1531,7 +1531,7 @@ static int build_top_module_global_net_from_tile_modules( module_manager, top_module, top_module_port, tile_annotation, tile_global_port, tile_port, vpr_device_annotation, grids, layer, vtr::Point(ix, iy), NUM_SIDES, tile_instance_ids, - fabric_tile); + fabric_tile, perimeter_cb); if (CMD_EXEC_FATAL_ERROR == status) { return status; } @@ -1578,7 +1578,7 @@ static int build_top_module_global_net_from_tile_modules( status = build_top_module_global_net_for_given_tile_module( module_manager, top_module, top_module_port, tile_annotation, tile_global_port, tile_port, vpr_device_annotation, grids, layer, - io_coordinate, io_side, tile_instance_ids, fabric_tile); + io_coordinate, io_side, tile_instance_ids, fabric_tile, perimeter_cb); if (CMD_EXEC_FATAL_ERROR == status) { return status; } @@ -1600,7 +1600,7 @@ static int add_top_module_global_ports_from_tile_modules( const size_t& layer, const RRGraphView& rr_graph, const DeviceRRGSB& device_rr_gsb, const vtr::Matrix& tile_instance_ids, const FabricTile& fabric_tile, - const ClockNetwork& clk_ntwk, const RRClockSpatialLookup& rr_clock_lookup) { + const ClockNetwork& clk_ntwk, const RRClockSpatialLookup& rr_clock_lookup, const bool& perimeter_cb) { int status = CMD_EXEC_SUCCESS; /* Add the global ports which are NOT yet added to the top-level module @@ -1657,7 +1657,7 @@ static int add_top_module_global_ports_from_tile_modules( status = build_top_module_global_net_from_tile_modules( module_manager, top_module, top_module_port, tile_annotation, tile_global_port, vpr_device_annotation, grids, layer, - tile_instance_ids, fabric_tile); + tile_instance_ids, fabric_tile, perimeter_cb); } if (status == CMD_EXEC_FATAL_ERROR) { return status; @@ -1905,6 +1905,7 @@ int build_top_module_tile_child_instances( const FabricTile& fabric_tile, const ConfigProtocol& config_protocol, const CircuitModelId& sram_model, const FabricKey& fabric_key, const bool& group_config_block, const bool& name_module_using_index, + const bool& perimeter_cb, const bool& frame_view, const bool& verbose) { int status = CMD_EXEC_SUCCESS; vtr::Matrix tile_instance_ids; @@ -1942,7 +1943,7 @@ int build_top_module_tile_child_instances( status = add_top_module_global_ports_from_tile_modules( module_manager, top_module, tile_annotation, vpr_device_annotation, grids, layer, rr_graph, device_rr_gsb, tile_instance_ids, fabric_tile, clk_ntwk, - rr_clock_lookup); + rr_clock_lookup, perimeter_cb); if (CMD_EXEC_FATAL_ERROR == status) { return status; } diff --git a/openfpga/src/fabric/build_top_module_child_tile_instance.h b/openfpga/src/fabric/build_top_module_child_tile_instance.h index bec2a9fa1..74a8aea63 100644 --- a/openfpga/src/fabric/build_top_module_child_tile_instance.h +++ b/openfpga/src/fabric/build_top_module_child_tile_instance.h @@ -44,6 +44,7 @@ int build_top_module_tile_child_instances( const FabricTile& fabric_tile, const ConfigProtocol& config_protocol, const CircuitModelId& sram_model, const FabricKey& fabric_key, const bool& group_config_block, const bool& name_module_using_index, + const bool& perimeter_cb, const bool& frame_view, const bool& verbose); } /* end namespace openfpga */ diff --git a/openfpga/src/fabric/build_top_module_connection.cpp b/openfpga/src/fabric/build_top_module_connection.cpp index 959532257..46907a1bb 100644 --- a/openfpga/src/fabric/build_top_module_connection.cpp +++ b/openfpga/src/fabric/build_top_module_connection.cpp @@ -956,7 +956,8 @@ static int build_top_module_global_net_for_given_grid_module( const BasicPort& tile_port_to_connect, const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, const size_t& layer, const vtr::Point& grid_coordinate, - const e_side& border_side, const vtr::Matrix& grid_instance_ids) { + const e_side& border_side, const vtr::Matrix& grid_instance_ids, + const bool& perimeter_cb) { t_physical_tile_type_ptr physical_tile = grids.get_physical_type( t_physical_tile_loc(grid_coordinate.x(), grid_coordinate.y(), layer)); /* Find the module name for this type of grid */ @@ -1033,7 +1034,7 @@ static int build_top_module_global_net_for_given_grid_module( size_t grid_pin_height = physical_tile->pin_height_offset[grid_pin_index]; std::vector pin_sides = find_physical_tile_pin_side( - physical_tile, grid_pin_index, border_side); + physical_tile, grid_pin_index, border_side, perimeter_cb); BasicPort grid_pin_info = vpr_device_annotation.physical_tile_pin_port_info(physical_tile, @@ -1091,7 +1092,8 @@ static int build_top_module_global_net_from_grid_modules( const ModulePortId& top_module_port, const TileAnnotation& tile_annotation, const TileGlobalPortId& tile_global_port, const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, - const size_t& layer, const vtr::Matrix& grid_instance_ids) { + const size_t& layer, const vtr::Matrix& grid_instance_ids, + const bool& perimeter_cb) { int status = CMD_EXEC_SUCCESS; std::map>> io_coordinates = @@ -1169,7 +1171,7 @@ static int build_top_module_global_net_from_grid_modules( status = build_top_module_global_net_for_given_grid_module( module_manager, top_module, top_module_port, tile_annotation, tile_global_port, tile_port, vpr_device_annotation, grids, layer, - vtr::Point(ix, iy), NUM_SIDES, grid_instance_ids); + vtr::Point(ix, iy), NUM_SIDES, grid_instance_ids, perimeter_cb); if (CMD_EXEC_FATAL_ERROR == status) { return status; } @@ -1216,7 +1218,7 @@ static int build_top_module_global_net_from_grid_modules( status = build_top_module_global_net_for_given_grid_module( module_manager, top_module, top_module_port, tile_annotation, tile_global_port, tile_port, vpr_device_annotation, grids, layer, - io_coordinate, io_side, grid_instance_ids); + io_coordinate, io_side, grid_instance_ids, perimeter_cb); if (CMD_EXEC_FATAL_ERROR == status) { return status; } @@ -1317,7 +1319,8 @@ int add_top_module_global_ports_from_grid_modules( const DeviceRRGSB& device_rr_gsb, const std::map>& cb_instance_ids, const vtr::Matrix& grid_instance_ids, const ClockNetwork& clk_ntwk, - const RRClockSpatialLookup& rr_clock_lookup) { + const RRClockSpatialLookup& rr_clock_lookup, + const bool& perimeter_cb) { int status = CMD_EXEC_SUCCESS; /* Add the global ports which are NOT yet added to the top-level module @@ -1382,7 +1385,7 @@ int add_top_module_global_ports_from_grid_modules( status = build_top_module_global_net_from_grid_modules( module_manager, top_module, top_module_port, tile_annotation, tile_global_port, vpr_device_annotation, grids, layer, - grid_instance_ids); + grid_instance_ids, perimeter_cb); } if (status == CMD_EXEC_FATAL_ERROR) { return status; diff --git a/openfpga/src/fabric/build_top_module_connection.h b/openfpga/src/fabric/build_top_module_connection.h index d4c18e7a7..08a642e07 100644 --- a/openfpga/src/fabric/build_top_module_connection.h +++ b/openfpga/src/fabric/build_top_module_connection.h @@ -42,7 +42,8 @@ int add_top_module_global_ports_from_grid_modules( const DeviceRRGSB& device_rr_gsb, const std::map>& cb_instance_ids, const vtr::Matrix& grid_instance_ids, const ClockNetwork& clk_ntwk, - const RRClockSpatialLookup& rr_clock_lookup); + const RRClockSpatialLookup& rr_clock_lookup, + const bool& perimeter_cb); void add_top_module_nets_prog_clock(ModuleManager& module_manager, const ModuleId& top_module, diff --git a/openfpga/src/utils/openfpga_physical_tile_utils.cpp b/openfpga/src/utils/openfpga_physical_tile_utils.cpp index 1f539ffcf..85768ff92 100644 --- a/openfpga/src/utils/openfpga_physical_tile_utils.cpp +++ b/openfpga/src/utils/openfpga_physical_tile_utils.cpp @@ -27,7 +27,7 @@ namespace openfpga { *******************************************************************/ std::vector find_physical_tile_pin_side( t_physical_tile_type_ptr physical_tile, const int& physical_pin, - const e_side& border_side) { + const e_side& border_side, const bool& perimeter_cb) { std::vector pin_sides; for (const e_side& side_cand : {TOP, RIGHT, BOTTOM, LEFT}) { int pin_width_offset = physical_tile->pin_width_offset[physical_pin]; @@ -40,17 +40,20 @@ std::vector find_physical_tile_pin_side( /* For regular grid, we should have pin only one side! * I/O grids: VPR creates the grid with duplicated pins on every side - * but the expected side (only used side) will be opposite side of the border + * - In regular cases: the expected side (only used side) will be on the opposite to the border * side! + * - When perimeter cb is on, the expected sides can be on any sides except the border side. But we only expect 1 side */ if (NUM_SIDES == border_side) { VTR_ASSERT(1 == pin_sides.size()); - } else { + } else if (!perimeter_cb) { SideManager side_manager(border_side); VTR_ASSERT(pin_sides.end() != std::find(pin_sides.begin(), pin_sides.end(), side_manager.get_opposite())); pin_sides.clear(); pin_sides.push_back(side_manager.get_opposite()); + } else { + VTR_ASSERT(1 == pin_sides.size() && pin_sides[0] != border_side); } return pin_sides; diff --git a/openfpga/src/utils/openfpga_physical_tile_utils.h b/openfpga/src/utils/openfpga_physical_tile_utils.h index 1ac98f321..68cb3972e 100644 --- a/openfpga/src/utils/openfpga_physical_tile_utils.h +++ b/openfpga/src/utils/openfpga_physical_tile_utils.h @@ -20,7 +20,7 @@ namespace openfpga { std::vector find_physical_tile_pin_side( t_physical_tile_type_ptr physical_tile, const int& physical_pin, - const e_side& border_side); + const e_side& border_side, const bool& perimeter_cb); float find_physical_tile_pin_Fc(t_physical_tile_type_ptr type, const int& pin); From ab454be831c8f3143acb8883e4131c803ea73ee5 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 8 Jul 2024 13:32:54 -0700 Subject: [PATCH 70/91] [lib] update vtr --- vtr-verilog-to-routing | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index d2be1c8b2..5ca82e54c 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit d2be1c8b2629069479863826695ed317bf88618a +Subproject commit 5ca82e54c4a2fa007fa7c43e9e91e582b7cf03fe From 549dc6e7e60e5523618eda2fc0f9ada3a6ec6450 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 8 Jul 2024 13:39:55 -0700 Subject: [PATCH 71/91] [lib] update vtr --- vtr-verilog-to-routing | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index 5ca82e54c..ddc3ac408 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit 5ca82e54c4a2fa007fa7c43e9e91e582b7cf03fe +Subproject commit ddc3ac408aa123dc8d4da1685c6dec7e65038646 From b50acacfbaaba260473dd3e30dc54d106bb33088 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 8 Jul 2024 15:09:31 -0700 Subject: [PATCH 72/91] [test] fixed some bug in pin loc; Outputs are not recommend on the fringe I/O tiles --- .../config/task.conf | 2 +- ...rimeterCb_ClkNtwk_registerable_io_40nm.xml | 28 +++++++++---------- 2 files changed, 15 insertions(+), 15 deletions(-) diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_perimeter_cb_global_tile_clock/config/task.conf b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_perimeter_cb_global_tile_clock/config/task.conf index 20efcfa2d..99a16d52e 100644 --- a/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_perimeter_cb_global_tile_clock/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_perimeter_cb_global_tile_clock/config/task.conf @@ -22,7 +22,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio openfpga_vpr_extra_options= openfpga_pb_pin_fixup_command= openfpga_vpr_device=2x2 -openfpga_vpr_route_chan_width=40 +openfpga_vpr_route_chan_width=20 openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml openfpga_verilog_testbench_options=--explicit_port_mapping diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml index 09a0af616..83d977423 100644 --- a/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml +++ b/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml @@ -48,10 +48,10 @@ - io_top[0:1].outpad[0:0] io_top[0:1].inpad[0:0] + io_top[0:1].outpad[0:0] - io_top[0:5].clk[0:0] - io_top[2:5].outpad[0:0] io_top[2:5].inpad[0:0] + io_top[2:3].outpad io_top[0:5].clk[0:0] + io_top[4:5].outpad[0:0] io_top[0:5].inpad[0:0] @@ -67,10 +67,10 @@ - io_right[0:0].outpad[0:0] io_right[0:0].inpad[0:0] io_right[0:2].clk[0:0] + io_right[0:0].outpad[0:0] io_right[0:2].inpad[0:0] io_right[0:2].clk[0:0] - io_right[1:1].outpad[0:0] io_right[1:1].inpad[0:0] - io_right[2:2].outpad[0:0] io_right[2:2].inpad[0:0] + io_right[1:1].outpad[0:0] + io_right[2:2].outpad[0:0] @@ -86,10 +86,10 @@ - io_bottom[0:1].outpad[0:0] io_bottom[0:1].inpad[0:0] io_bottom[0:3].clk[0:0] + io_bottom[0:1].outpad[0:0] io_bottom[0:3].clk[0:0] - io_bottom[2:3].outpad[0:0] io_bottom[2:3].inpad[0:0] - + io_bottom[2:2].outpad[0:0] io_bottom[0:3].inpad[0:0] + io_bottom[3:3].outpad[0:0] @@ -105,10 +105,10 @@ - io_left[0:1].outpad[0:0] io_left[0:1].inpad[0:0] io_left[0:3].clk[0:0] + io_left[0:1].outpad[0:0] io_left[0:3].inpad[0:0] io_left[0:3].clk[0:0] - - io_left[2:3].outpad[0:0] io_left[2:3].inpad[0:0] + io_left[2:2].outpad[0:0] + io_left[3:3].outpad[0:0] @@ -206,12 +206,12 @@ - + 1 1 1 - + 1 1 1 1 1 1 1 1 1 From 8bca3d79be5fdc284cb25bd8bce565982a385fe2 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 8 Jul 2024 15:17:24 -0700 Subject: [PATCH 73/91] [core] fixed a bug where tap points of clock network cannot reach perimeter cb --- .../src/annotation/append_clock_rr_graph.cpp | 22 +++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/openfpga/src/annotation/append_clock_rr_graph.cpp b/openfpga/src/annotation/append_clock_rr_graph.cpp index b7b82c269..0837e1fcd 100644 --- a/openfpga/src/annotation/append_clock_rr_graph.cpp +++ b/openfpga/src/annotation/append_clock_rr_graph.cpp @@ -751,9 +751,16 @@ static void add_rr_graph_clock_edges( const DeviceGrid& grids, const size_t& layer, const bool& perimeter_cb, const bool& through_channel, const ClockNetwork& clk_ntwk, const bool& verbose) { + vtr::Rect chanx_bb(1, 0, grids.width() - 1, grids.height() - 1); + if (perimeter_cb) { + chanx_bb.set_xmin(0); + chanx_bb.set_xmax(grids.width()); + chanx_bb.set_ymin(0); + chanx_bb.set_ymax(grids.height()); + } /* Add edges which is driven by X-direction clock routing tracks */ - for (size_t iy = 0; iy < grids.height() - 1; ++iy) { - for (size_t ix = 1; ix < grids.width() - 1; ++ix) { + for (size_t iy = chanx_bb.ymin(); iy < chanx_bb.ymax(); ++iy) { + for (size_t ix = chanx_bb.xmin(); ix < chanx_bb.xmax(); ++ix) { vtr::Point chanx_coord(ix, iy); /* Bypass if the routing channel does not exist when through channels are * not allowed */ @@ -768,8 +775,15 @@ static void add_rr_graph_clock_edges( } /* Add edges which is driven by Y-direction clock routing tracks */ - for (size_t ix = 0; ix < grids.width() - 1; ++ix) { - for (size_t iy = 1; iy < grids.height() - 1; ++iy) { + vtr::Rect chany_bb(0, 1, grids.width() - 1, grids.height() - 1); + if (perimeter_cb) { + chany_bb.set_xmin(0); + chany_bb.set_xmax(grids.width()); + chany_bb.set_ymin(0); + chany_bb.set_ymax(grids.height()); + } + for (size_t ix = chany_bb.xmin(); ix < chany_bb.xmax(); ++ix) { + for (size_t iy = chany_bb.ymin(); iy < chany_bb.ymax(); ++iy) { vtr::Point chany_coord(ix, iy); /* Bypass if the routing channel does not exist when through channel are * not allowed */ From c30eafac9f7c511c95452a1435edd9d7b9ddd6a0 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 8 Jul 2024 15:26:16 -0700 Subject: [PATCH 74/91] [test] fixed a bug on clk ntwk arch where some io clocks are not tapped --- .../config/clk_arch_1clk_2layer.xml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/clk_arch_1clk_2layer.xml b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/clk_arch_1clk_2layer.xml index 453d0b5d0..2b85f88cd 100644 --- a/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/clk_arch_1clk_2layer.xml +++ b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/clk_arch_1clk_2layer.xml @@ -16,10 +16,10 @@ - - - - + + + + From 6dde383a7fbc0f4b049ee214553885d968598501 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 8 Jul 2024 16:00:18 -0700 Subject: [PATCH 75/91] [core] debugging --- .../src/annotation/append_clock_rr_graph.cpp | 3 +++ .../utils/openfpga_physical_tile_utils.cpp | 20 +++++++++---------- 2 files changed, 12 insertions(+), 11 deletions(-) diff --git a/openfpga/src/annotation/append_clock_rr_graph.cpp b/openfpga/src/annotation/append_clock_rr_graph.cpp index 0837e1fcd..f9aadfc74 100644 --- a/openfpga/src/annotation/append_clock_rr_graph.cpp +++ b/openfpga/src/annotation/append_clock_rr_graph.cpp @@ -420,14 +420,17 @@ static void try_find_and_add_clock_track2ipin_node( t_physical_tile_loc(grid_coord.x(), grid_coord.y(), layer)); for (std::string tap_pin_name : clk_ntwk.tree_flatten_tap_to_ports(clk_tree, clk_pin, grid_coord)) { + VTR_LOG("Checking tap pin name: %s\n", tap_pin_name.c_str()); /* tap pin name could be 'io[5:5].a2f[0]' */ int grid_pin_idx = find_physical_tile_pin_index(grid_type, tap_pin_name); if (grid_pin_idx == grid_type->num_pins) { continue; } + VTR_LOG("Found a valid pin in physical tile\n"); RRNodeId des_node = rr_graph_view.node_lookup().find_node( layer, grid_coord.x(), grid_coord.y(), IPIN, grid_pin_idx, pin_side); if (rr_graph_view.valid_node(des_node)) { + VTR_LOG("Found a valid pin in rr graph\n"); des_nodes.push_back(des_node); } } diff --git a/openfpga/src/utils/openfpga_physical_tile_utils.cpp b/openfpga/src/utils/openfpga_physical_tile_utils.cpp index 85768ff92..1cce2eeee 100644 --- a/openfpga/src/utils/openfpga_physical_tile_utils.cpp +++ b/openfpga/src/utils/openfpga_physical_tile_utils.cpp @@ -144,9 +144,6 @@ int find_physical_tile_pin_index(t_physical_tile_type_ptr physical_tile, } PortParser tile_parser(pin_tokens[0]); BasicPort tile_info = tile_parser.port(); - if (tile_info.get_name() != std::string(physical_tile->name)) { - return pin_idx; - } if (!tile_info.is_valid()) { VTR_LOG_ERROR( "Invalid pin name '%s' whose subtile index is not valid, expect [0, " @@ -162,13 +159,6 @@ int find_physical_tile_pin_index(t_physical_tile_type_ptr physical_tile, pin_name.c_str()); exit(1); } - if (tile_info.get_msb() > size_t(physical_tile->capacity) - 1) { - VTR_LOG_ERROR( - "Invalid pin name '%s' whose subtile index is out of range, expect [0, " - "%lu]\n", - pin_name.c_str(), physical_tile->capacity - 1); - exit(1); - } /* precheck: return unfound pin if the pin index does not match */ PortParser pin_parser(pin_tokens[1]); BasicPort pin_info = pin_parser.port(); @@ -183,9 +173,17 @@ int find_physical_tile_pin_index(t_physical_tile_type_ptr physical_tile, /* Spot the subtile by using the index */ for (const t_sub_tile& sub_tile : physical_tile->sub_tiles) { - if (!sub_tile.capacity.is_in_range(tile_info.get_lsb())) { + /* Bypass unmatched subtiles*/ + if (tile_info.get_name() != std::string(sub_tile.name)) { continue; } + if (!sub_tile.capacity.is_in_range(tile_info.get_lsb())) { + VTR_LOG_ERROR( + "Invalid pin name '%s' whose subtile index is out of range, expect [%lu, " + "%lu]\n", + pin_name.c_str(), sub_tile.capacity.low, sub_tile.capacity.high); + exit(1); + } for (const t_physical_tile_port& sub_tile_port : sub_tile.ports) { if (std::string(sub_tile_port.name) != pin_info.get_name()) { continue; From e8f9deeeaf0730ffb964940e76acff3161ec9697 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 8 Jul 2024 16:12:20 -0700 Subject: [PATCH 76/91] [core] fixed a critical bug on computing pin index for subtile in clock taps --- openfpga/src/utils/openfpga_physical_tile_utils.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/openfpga/src/utils/openfpga_physical_tile_utils.cpp b/openfpga/src/utils/openfpga_physical_tile_utils.cpp index 1cce2eeee..ee3b3b5db 100644 --- a/openfpga/src/utils/openfpga_physical_tile_utils.cpp +++ b/openfpga/src/utils/openfpga_physical_tile_utils.cpp @@ -205,8 +205,9 @@ int find_physical_tile_pin_index(t_physical_tile_type_ptr physical_tile, /* Reach here, we get the port we want, return the accumulated index */ size_t accumulated_pin_idx = sub_tile_port.absolute_first_pin_index + - sub_tile.num_phy_pins * (tile_info.get_lsb() - sub_tile.capacity.low) + + (sub_tile.num_phy_pins / sub_tile.capacity.total()) * (tile_info.get_lsb() - sub_tile.capacity.low) + pin_info.get_lsb(); + VTR_LOG("Pin index: %lu\n", accumulated_pin_idx); return accumulated_pin_idx; } } From db459b0e87df04f824c90420b6b8a983c4933d62 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 8 Jul 2024 16:18:32 -0700 Subject: [PATCH 77/91] [core] add verbose outputs --- .../src/annotation/append_clock_rr_graph.cpp | 21 ++++++++++--------- .../utils/openfpga_physical_tile_utils.cpp | 1 - 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/openfpga/src/annotation/append_clock_rr_graph.cpp b/openfpga/src/annotation/append_clock_rr_graph.cpp index f9aadfc74..d54c018a6 100644 --- a/openfpga/src/annotation/append_clock_rr_graph.cpp +++ b/openfpga/src/annotation/append_clock_rr_graph.cpp @@ -415,22 +415,22 @@ static void try_find_and_add_clock_track2ipin_node( const RRGraphView& rr_graph_view, const size_t& layer, const vtr::Point& grid_coord, const e_side& pin_side, const ClockNetwork& clk_ntwk, const ClockTreeId& clk_tree, - const ClockTreePinId& clk_pin) { + const ClockTreePinId& clk_pin, const bool& verbose) { t_physical_tile_type_ptr grid_type = grids.get_physical_type( t_physical_tile_loc(grid_coord.x(), grid_coord.y(), layer)); for (std::string tap_pin_name : clk_ntwk.tree_flatten_tap_to_ports(clk_tree, clk_pin, grid_coord)) { - VTR_LOG("Checking tap pin name: %s\n", tap_pin_name.c_str()); + VTR_LOGV(verbose, "Checking tap pin name: %s\n", tap_pin_name.c_str()); /* tap pin name could be 'io[5:5].a2f[0]' */ int grid_pin_idx = find_physical_tile_pin_index(grid_type, tap_pin_name); if (grid_pin_idx == grid_type->num_pins) { continue; } - VTR_LOG("Found a valid pin in physical tile\n"); + VTR_LOGV(verbose, "Found a valid pin (index=%d) in physical tile\n", grid_pin_idx); RRNodeId des_node = rr_graph_view.node_lookup().find_node( layer, grid_coord.x(), grid_coord.y(), IPIN, grid_pin_idx, pin_side); if (rr_graph_view.valid_node(des_node)) { - VTR_LOG("Found a valid pin in rr graph\n"); + VTR_LOGV(verbose, "Found a valid pin in rr graph\n"); des_nodes.push_back(des_node); } } @@ -466,7 +466,8 @@ static std::vector find_clock_track2ipin_node( const DeviceGrid& grids, const RRGraphView& rr_graph_view, const t_rr_type& chan_type, const size_t& layer, const vtr::Point& chan_coord, const ClockNetwork& clk_ntwk, - const ClockTreeId& clk_tree, const ClockTreePinId& clk_pin) { + const ClockTreeId& clk_tree, const ClockTreePinId& clk_pin, + const bool& verbose) { std::vector des_nodes; if (chan_type == CHANX) { @@ -474,26 +475,26 @@ static std::vector find_clock_track2ipin_node( vtr::Point bot_grid_coord(chan_coord.x(), chan_coord.y() + 1); try_find_and_add_clock_track2ipin_node(des_nodes, grids, rr_graph_view, layer, bot_grid_coord, BOTTOM, - clk_ntwk, clk_tree, clk_pin); + clk_ntwk, clk_tree, clk_pin, verbose); /* Get the clock IPINs at the TOP side of adjacent grids [x][y] */ vtr::Point top_grid_coord(chan_coord.x(), chan_coord.y()); try_find_and_add_clock_track2ipin_node(des_nodes, grids, rr_graph_view, layer, top_grid_coord, TOP, clk_ntwk, - clk_tree, clk_pin); + clk_tree, clk_pin, verbose); } else { VTR_ASSERT(chan_type == CHANY); /* Get the clock IPINs at the LEFT side of adjacent grids [x][y+1] */ vtr::Point left_grid_coord(chan_coord.x() + 1, chan_coord.y()); try_find_and_add_clock_track2ipin_node(des_nodes, grids, rr_graph_view, layer, left_grid_coord, LEFT, - clk_ntwk, clk_tree, clk_pin); + clk_ntwk, clk_tree, clk_pin, verbose); /* Get the clock IPINs at the RIGHT side of adjacent grids [x][y] */ vtr::Point right_grid_coord(chan_coord.x(), chan_coord.y()); try_find_and_add_clock_track2ipin_node(des_nodes, grids, rr_graph_view, layer, right_grid_coord, RIGHT, - clk_ntwk, clk_tree, clk_pin); + clk_ntwk, clk_tree, clk_pin, verbose); } return des_nodes; @@ -560,7 +561,7 @@ static void add_rr_graph_block_clock_edges( size_t curr_edge_count = edge_count; for (RRNodeId des_node : find_clock_track2ipin_node( grids, rr_graph_view, chan_type, layer, chan_coord, clk_ntwk, - itree, ClockTreePinId(ipin))) { + itree, ClockTreePinId(ipin), verbose)) { /* Create edges */ VTR_ASSERT(rr_graph_view.valid_node(des_node)); rr_graph_builder.create_edge( diff --git a/openfpga/src/utils/openfpga_physical_tile_utils.cpp b/openfpga/src/utils/openfpga_physical_tile_utils.cpp index ee3b3b5db..652e7ecc7 100644 --- a/openfpga/src/utils/openfpga_physical_tile_utils.cpp +++ b/openfpga/src/utils/openfpga_physical_tile_utils.cpp @@ -207,7 +207,6 @@ int find_physical_tile_pin_index(t_physical_tile_type_ptr physical_tile, sub_tile_port.absolute_first_pin_index + (sub_tile.num_phy_pins / sub_tile.capacity.total()) * (tile_info.get_lsb() - sub_tile.capacity.low) + pin_info.get_lsb(); - VTR_LOG("Pin index: %lu\n", accumulated_pin_idx); return accumulated_pin_idx; } } From fe06c2f2b17641208b9923883e7215427a784a78 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 8 Jul 2024 16:18:58 -0700 Subject: [PATCH 78/91] [core] code format --- .../src/annotation/append_clock_rr_graph.cpp | 24 +++++++++---------- openfpga/src/base/openfpga_pb_pin_fixup.cpp | 4 ++-- openfpga/src/fabric/build_device_module.cpp | 3 +-- openfpga/src/fabric/build_top_module.cpp | 3 +-- openfpga/src/fabric/build_top_module.h | 3 +-- ...top_module_child_fine_grained_instance.cpp | 3 +-- ...d_top_module_child_fine_grained_instance.h | 3 +-- .../build_top_module_child_tile_instance.cpp | 10 ++++---- .../build_top_module_child_tile_instance.h | 3 +-- .../fabric/build_top_module_connection.cpp | 6 ++--- .../src/fabric/build_top_module_connection.h | 3 +-- .../utils/openfpga_physical_tile_utils.cpp | 13 ++++++---- 12 files changed, 37 insertions(+), 41 deletions(-) diff --git a/openfpga/src/annotation/append_clock_rr_graph.cpp b/openfpga/src/annotation/append_clock_rr_graph.cpp index d54c018a6..d051634db 100644 --- a/openfpga/src/annotation/append_clock_rr_graph.cpp +++ b/openfpga/src/annotation/append_clock_rr_graph.cpp @@ -426,7 +426,8 @@ static void try_find_and_add_clock_track2ipin_node( if (grid_pin_idx == grid_type->num_pins) { continue; } - VTR_LOGV(verbose, "Found a valid pin (index=%d) in physical tile\n", grid_pin_idx); + VTR_LOGV(verbose, "Found a valid pin (index=%d) in physical tile\n", + grid_pin_idx); RRNodeId des_node = rr_graph_view.node_lookup().find_node( layer, grid_coord.x(), grid_coord.y(), IPIN, grid_pin_idx, pin_side); if (rr_graph_view.valid_node(des_node)) { @@ -473,9 +474,9 @@ static std::vector find_clock_track2ipin_node( if (chan_type == CHANX) { /* Get the clock IPINs at the BOTTOM side of adjacent grids [x][y+1] */ vtr::Point bot_grid_coord(chan_coord.x(), chan_coord.y() + 1); - try_find_and_add_clock_track2ipin_node(des_nodes, grids, rr_graph_view, - layer, bot_grid_coord, BOTTOM, - clk_ntwk, clk_tree, clk_pin, verbose); + try_find_and_add_clock_track2ipin_node( + des_nodes, grids, rr_graph_view, layer, bot_grid_coord, BOTTOM, clk_ntwk, + clk_tree, clk_pin, verbose); /* Get the clock IPINs at the TOP side of adjacent grids [x][y] */ vtr::Point top_grid_coord(chan_coord.x(), chan_coord.y()); @@ -486,15 +487,15 @@ static std::vector find_clock_track2ipin_node( VTR_ASSERT(chan_type == CHANY); /* Get the clock IPINs at the LEFT side of adjacent grids [x][y+1] */ vtr::Point left_grid_coord(chan_coord.x() + 1, chan_coord.y()); - try_find_and_add_clock_track2ipin_node(des_nodes, grids, rr_graph_view, - layer, left_grid_coord, LEFT, - clk_ntwk, clk_tree, clk_pin, verbose); + try_find_and_add_clock_track2ipin_node( + des_nodes, grids, rr_graph_view, layer, left_grid_coord, LEFT, clk_ntwk, + clk_tree, clk_pin, verbose); /* Get the clock IPINs at the RIGHT side of adjacent grids [x][y] */ vtr::Point right_grid_coord(chan_coord.x(), chan_coord.y()); - try_find_and_add_clock_track2ipin_node(des_nodes, grids, rr_graph_view, - layer, right_grid_coord, RIGHT, - clk_ntwk, clk_tree, clk_pin, verbose); + try_find_and_add_clock_track2ipin_node( + des_nodes, grids, rr_graph_view, layer, right_grid_coord, RIGHT, clk_ntwk, + clk_tree, clk_pin, verbose); } return des_nodes; @@ -816,8 +817,7 @@ static void add_rr_graph_clock_edges( *******************************************************************/ int append_clock_rr_graph(DeviceContext& vpr_device_ctx, RRClockSpatialLookup& clk_rr_lookup, - const ClockNetwork& clk_ntwk, - const bool& verbose) { + const ClockNetwork& clk_ntwk, const bool& verbose) { vtr::ScopedStartFinishTimer timer( "Appending programmable clock network to routing resource graph"); diff --git a/openfpga/src/base/openfpga_pb_pin_fixup.cpp b/openfpga/src/base/openfpga_pb_pin_fixup.cpp index e96e4d218..4d7e1cfd4 100644 --- a/openfpga/src/base/openfpga_pb_pin_fixup.cpp +++ b/openfpga/src/base/openfpga_pb_pin_fixup.cpp @@ -59,8 +59,8 @@ static void update_cluster_pin_with_post_routing_results( VTR_ASSERT(class_inf.type == RECEIVER); rr_node_type = IPIN; } - std::vector pin_sides = - find_physical_tile_pin_side(physical_tile, physical_pin, border_side, device_ctx.arch->perimeter_cb); + std::vector pin_sides = find_physical_tile_pin_side( + physical_tile, physical_pin, border_side, device_ctx.arch->perimeter_cb); /* As some grid has height/width offset, we may not have the pin on any side */ if (0 == pin_sides.size()) { diff --git a/openfpga/src/fabric/build_device_module.cpp b/openfpga/src/fabric/build_device_module.cpp index 3ffa869e8..d517002a7 100644 --- a/openfpga/src/fabric/build_device_module.cpp +++ b/openfpga/src/fabric/build_device_module.cpp @@ -143,8 +143,7 @@ int build_device_module_graph( sram_model, fabric_tile, name_module_using_index, frame_view, compress_routing, duplicate_grid_pin, fabric_key, generate_random_fabric_key, group_config_block, - vpr_device_ctx.arch->perimeter_cb, - verbose); + vpr_device_ctx.arch->perimeter_cb, verbose); if (CMD_EXEC_FATAL_ERROR == status) { return status; diff --git a/openfpga/src/fabric/build_top_module.cpp b/openfpga/src/fabric/build_top_module.cpp index 54fd54702..fc2831d95 100644 --- a/openfpga/src/fabric/build_top_module.cpp +++ b/openfpga/src/fabric/build_top_module.cpp @@ -58,8 +58,7 @@ int build_top_module( const bool& name_module_using_index, const bool& frame_view, const bool& compact_routing_hierarchy, const bool& duplicate_grid_pin, const FabricKey& fabric_key, const bool& generate_random_fabric_key, - const bool& group_config_block, - const bool& perimeter_cb, + const bool& group_config_block, const bool& perimeter_cb, const bool& verbose) { vtr::ScopedStartFinishTimer timer("Build FPGA fabric module"); diff --git a/openfpga/src/fabric/build_top_module.h b/openfpga/src/fabric/build_top_module.h index 75c3649eb..4e560d4f3 100644 --- a/openfpga/src/fabric/build_top_module.h +++ b/openfpga/src/fabric/build_top_module.h @@ -45,8 +45,7 @@ int build_top_module( const bool& name_module_using_index, const bool& frame_view, const bool& compact_routing_hierarchy, const bool& duplicate_grid_pin, const FabricKey& fabric_key, const bool& generate_random_fabric_key, - const bool& group_config_block, - const bool& perimeter_cb, + const bool& group_config_block, const bool& perimeter_cb, const bool& verbose); } /* end namespace openfpga */ diff --git a/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp b/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp index 7e3fcfa2f..914e384e1 100644 --- a/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp +++ b/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp @@ -454,8 +454,7 @@ int build_top_module_fine_grained_child_instances( const ConfigProtocol& config_protocol, const CircuitModelId& sram_model, const bool& frame_view, const bool& compact_routing_hierarchy, const bool& duplicate_grid_pin, const FabricKey& fabric_key, - const bool& group_config_block, - const bool& perimeter_cb, + const bool& group_config_block, const bool& perimeter_cb, const bool& verbose) { int status = CMD_EXEC_SUCCESS; std::map> cb_instance_ids; diff --git a/openfpga/src/fabric/build_top_module_child_fine_grained_instance.h b/openfpga/src/fabric/build_top_module_child_fine_grained_instance.h index 394f7a2df..b4d1677d8 100644 --- a/openfpga/src/fabric/build_top_module_child_fine_grained_instance.h +++ b/openfpga/src/fabric/build_top_module_child_fine_grained_instance.h @@ -44,8 +44,7 @@ int build_top_module_fine_grained_child_instances( const ConfigProtocol& config_protocol, const CircuitModelId& sram_model, const bool& frame_view, const bool& compact_routing_hierarchy, const bool& duplicate_grid_pin, const FabricKey& fabric_key, - const bool& group_config_block, - const bool& perimeter_cb, + const bool& group_config_block, const bool& perimeter_cb, const bool& verbose); } /* end namespace openfpga */ diff --git a/openfpga/src/fabric/build_top_module_child_tile_instance.cpp b/openfpga/src/fabric/build_top_module_child_tile_instance.cpp index bf12dabc6..05f1f9b51 100644 --- a/openfpga/src/fabric/build_top_module_child_tile_instance.cpp +++ b/openfpga/src/fabric/build_top_module_child_tile_instance.cpp @@ -1530,8 +1530,8 @@ static int build_top_module_global_net_from_tile_modules( status = build_top_module_global_net_for_given_tile_module( module_manager, top_module, top_module_port, tile_annotation, tile_global_port, tile_port, vpr_device_annotation, grids, layer, - vtr::Point(ix, iy), NUM_SIDES, tile_instance_ids, - fabric_tile, perimeter_cb); + vtr::Point(ix, iy), NUM_SIDES, tile_instance_ids, fabric_tile, + perimeter_cb); if (CMD_EXEC_FATAL_ERROR == status) { return status; } @@ -1600,7 +1600,8 @@ static int add_top_module_global_ports_from_tile_modules( const size_t& layer, const RRGraphView& rr_graph, const DeviceRRGSB& device_rr_gsb, const vtr::Matrix& tile_instance_ids, const FabricTile& fabric_tile, - const ClockNetwork& clk_ntwk, const RRClockSpatialLookup& rr_clock_lookup, const bool& perimeter_cb) { + const ClockNetwork& clk_ntwk, const RRClockSpatialLookup& rr_clock_lookup, + const bool& perimeter_cb) { int status = CMD_EXEC_SUCCESS; /* Add the global ports which are NOT yet added to the top-level module @@ -1905,8 +1906,7 @@ int build_top_module_tile_child_instances( const FabricTile& fabric_tile, const ConfigProtocol& config_protocol, const CircuitModelId& sram_model, const FabricKey& fabric_key, const bool& group_config_block, const bool& name_module_using_index, - const bool& perimeter_cb, - const bool& frame_view, const bool& verbose) { + const bool& perimeter_cb, const bool& frame_view, const bool& verbose) { int status = CMD_EXEC_SUCCESS; vtr::Matrix tile_instance_ids; status = add_top_module_tile_instances(module_manager, top_module, diff --git a/openfpga/src/fabric/build_top_module_child_tile_instance.h b/openfpga/src/fabric/build_top_module_child_tile_instance.h index 74a8aea63..05b44d017 100644 --- a/openfpga/src/fabric/build_top_module_child_tile_instance.h +++ b/openfpga/src/fabric/build_top_module_child_tile_instance.h @@ -44,8 +44,7 @@ int build_top_module_tile_child_instances( const FabricTile& fabric_tile, const ConfigProtocol& config_protocol, const CircuitModelId& sram_model, const FabricKey& fabric_key, const bool& group_config_block, const bool& name_module_using_index, - const bool& perimeter_cb, - const bool& frame_view, const bool& verbose); + const bool& perimeter_cb, const bool& frame_view, const bool& verbose); } /* end namespace openfpga */ diff --git a/openfpga/src/fabric/build_top_module_connection.cpp b/openfpga/src/fabric/build_top_module_connection.cpp index 46907a1bb..0a754f352 100644 --- a/openfpga/src/fabric/build_top_module_connection.cpp +++ b/openfpga/src/fabric/build_top_module_connection.cpp @@ -1171,7 +1171,8 @@ static int build_top_module_global_net_from_grid_modules( status = build_top_module_global_net_for_given_grid_module( module_manager, top_module, top_module_port, tile_annotation, tile_global_port, tile_port, vpr_device_annotation, grids, layer, - vtr::Point(ix, iy), NUM_SIDES, grid_instance_ids, perimeter_cb); + vtr::Point(ix, iy), NUM_SIDES, grid_instance_ids, + perimeter_cb); if (CMD_EXEC_FATAL_ERROR == status) { return status; } @@ -1319,8 +1320,7 @@ int add_top_module_global_ports_from_grid_modules( const DeviceRRGSB& device_rr_gsb, const std::map>& cb_instance_ids, const vtr::Matrix& grid_instance_ids, const ClockNetwork& clk_ntwk, - const RRClockSpatialLookup& rr_clock_lookup, - const bool& perimeter_cb) { + const RRClockSpatialLookup& rr_clock_lookup, const bool& perimeter_cb) { int status = CMD_EXEC_SUCCESS; /* Add the global ports which are NOT yet added to the top-level module diff --git a/openfpga/src/fabric/build_top_module_connection.h b/openfpga/src/fabric/build_top_module_connection.h index 08a642e07..1c04d0e25 100644 --- a/openfpga/src/fabric/build_top_module_connection.h +++ b/openfpga/src/fabric/build_top_module_connection.h @@ -42,8 +42,7 @@ int add_top_module_global_ports_from_grid_modules( const DeviceRRGSB& device_rr_gsb, const std::map>& cb_instance_ids, const vtr::Matrix& grid_instance_ids, const ClockNetwork& clk_ntwk, - const RRClockSpatialLookup& rr_clock_lookup, - const bool& perimeter_cb); + const RRClockSpatialLookup& rr_clock_lookup, const bool& perimeter_cb); void add_top_module_nets_prog_clock(ModuleManager& module_manager, const ModuleId& top_module, diff --git a/openfpga/src/utils/openfpga_physical_tile_utils.cpp b/openfpga/src/utils/openfpga_physical_tile_utils.cpp index 652e7ecc7..fd77cc072 100644 --- a/openfpga/src/utils/openfpga_physical_tile_utils.cpp +++ b/openfpga/src/utils/openfpga_physical_tile_utils.cpp @@ -40,9 +40,10 @@ std::vector find_physical_tile_pin_side( /* For regular grid, we should have pin only one side! * I/O grids: VPR creates the grid with duplicated pins on every side - * - In regular cases: the expected side (only used side) will be on the opposite to the border - * side! - * - When perimeter cb is on, the expected sides can be on any sides except the border side. But we only expect 1 side + * - In regular cases: the expected side (only used side) will be on the + * opposite to the border side! + * - When perimeter cb is on, the expected sides can be on any sides except + * the border side. But we only expect 1 side */ if (NUM_SIDES == border_side) { VTR_ASSERT(1 == pin_sides.size()); @@ -179,7 +180,8 @@ int find_physical_tile_pin_index(t_physical_tile_type_ptr physical_tile, } if (!sub_tile.capacity.is_in_range(tile_info.get_lsb())) { VTR_LOG_ERROR( - "Invalid pin name '%s' whose subtile index is out of range, expect [%lu, " + "Invalid pin name '%s' whose subtile index is out of range, expect " + "[%lu, " "%lu]\n", pin_name.c_str(), sub_tile.capacity.low, sub_tile.capacity.high); exit(1); @@ -205,7 +207,8 @@ int find_physical_tile_pin_index(t_physical_tile_type_ptr physical_tile, /* Reach here, we get the port we want, return the accumulated index */ size_t accumulated_pin_idx = sub_tile_port.absolute_first_pin_index + - (sub_tile.num_phy_pins / sub_tile.capacity.total()) * (tile_info.get_lsb() - sub_tile.capacity.low) + + (sub_tile.num_phy_pins / sub_tile.capacity.total()) * + (tile_info.get_lsb() - sub_tile.capacity.low) + pin_info.get_lsb(); return accumulated_pin_idx; } From ad053cddca71ad7c4dc03c47b259f82a277b8a1d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 8 Jul 2024 18:02:30 -0700 Subject: [PATCH 79/91] [test] code format --- ..._tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml index 83d977423..fe403bd62 100644 --- a/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml +++ b/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml @@ -49,7 +49,7 @@ io_top[0:1].outpad[0:0] - + io_top[2:3].outpad io_top[0:5].clk[0:0] io_top[4:5].outpad[0:0] io_top[0:5].inpad[0:0] @@ -68,7 +68,7 @@ io_right[0:0].outpad[0:0] io_right[0:2].inpad[0:0] io_right[0:2].clk[0:0] - + io_right[1:1].outpad[0:0] io_right[2:2].outpad[0:0] @@ -87,7 +87,7 @@ io_bottom[0:1].outpad[0:0] io_bottom[0:3].clk[0:0] - + io_bottom[2:2].outpad[0:0] io_bottom[0:3].inpad[0:0] io_bottom[3:3].outpad[0:0] @@ -106,7 +106,7 @@ io_left[0:1].outpad[0:0] io_left[0:3].inpad[0:0] io_left[0:3].clk[0:0] - + io_left[2:2].outpad[0:0] io_left[3:3].outpad[0:0] From c7d6c3ab6169329701395574c3c3ac5208d0b159 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 8 Jul 2024 18:34:13 -0700 Subject: [PATCH 80/91] [arch] now all the outputs of I/O can only on 1 side --- ...k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml index e25a5a686..19caea0ac 100644 --- a/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml +++ b/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml @@ -67,8 +67,8 @@ - fpga_input[0:1].inpad - fpga_input[2:3].inpad + + fpga_input[0:3].inpad @@ -93,9 +93,9 @@ - fpga_input[0:1].inpad + fpga_input[0:3].inpad - fpga_input[2:3].inpad + @@ -122,8 +122,8 @@ - fpga_input[0:1].inpad - fpga_input[2:3].inpad + + fpga_input[0:3].inpad @@ -150,9 +150,9 @@ - fpga_input[0:1].inpad + fpga_input[0:3].inpad - fpga_input[2:3].inpad + From 03c1c6f9173e1bfd54be7b76582b8a991c505898 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 8 Jul 2024 18:35:23 -0700 Subject: [PATCH 81/91] [test] code format --- .../k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml index 19caea0ac..142784a73 100644 --- a/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml +++ b/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml @@ -67,7 +67,7 @@ - + fpga_input[0:3].inpad @@ -95,7 +95,7 @@ fpga_input[0:3].inpad - + @@ -122,7 +122,7 @@ - + fpga_input[0:3].inpad @@ -152,7 +152,7 @@ fpga_input[0:3].inpad - + From 8a5c33b1d642cd569c58084f9118e1637960bbf1 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 8 Jul 2024 19:01:16 -0700 Subject: [PATCH 82/91] [doc] new option for perimeter cb --- .../manual/arch_lang/addon_vpr_syntax.rst | 17 +++++++++++++++++ .../manual/arch_lang/figures/perimeter_cb.png | Bin 0 -> 5525581 bytes 2 files changed, 17 insertions(+) create mode 100644 docs/source/manual/arch_lang/figures/perimeter_cb.png diff --git a/docs/source/manual/arch_lang/addon_vpr_syntax.rst b/docs/source/manual/arch_lang/addon_vpr_syntax.rst index b2c88992c..95a8eec64 100644 --- a/docs/source/manual/arch_lang/addon_vpr_syntax.rst +++ b/docs/source/manual/arch_lang/addon_vpr_syntax.rst @@ -88,6 +88,23 @@ Layout .. warning:: Do NOT enable ``shrink_boundary`` if you are not using the tileable routing resource graph generator! +.. option:: perimeter_cb="" + + Allow connection blocks to appear around the perimeter programmable block (mainly I/Os). This is designed to enhance routability of I/Os on perimeter. Also strongly recommended when programmable clock network is required to touch clock pins on I/Os. As illustrated in :numref:`fig_perimeter_cb`, routing tracks can access three sides of each I/O when perimeter connection blocks are created. + By default, it is ``false``. + +.. warning:: When enabled, please only place outputs at one side of I/Os. For example, outputs of an I/O on the top side can only occur on the bottom side of the I/O tile. Otherwise, routability loss may be expected, leading to some pins cannot be reachable. Enable the ``opin2all_sides`` to recover routability loss. + + .. _fig_perimeter_cb: + + .. figure:: ./figures/perimeter_cb.png + :width: 100% + :alt: Impact of perimeter_cb + + Impact on routing architecture when perimeter connection blocks are : (a) disabled; (b) enabled. + + .. warning:: Do NOT enable ``perimeter_cb`` if you are not using the tileable routing resource graph generator! + .. option:: opin2all_sides="" Allow each output pin of a programmable block to drive the routing tracks on all the sides of its adjacent switch block (see an illustrative example in :numref:`fig_opin2all_sides`). This can improve the routability of an FPGA fabric with an increase in the sizes of routing multiplexers in each switch block. diff --git a/docs/source/manual/arch_lang/figures/perimeter_cb.png b/docs/source/manual/arch_lang/figures/perimeter_cb.png new file mode 100644 index 0000000000000000000000000000000000000000..e3a65833866e5c744504e5d357e786b8250578c1 GIT binary patch literal 5525581 zcmeEu=U-FXwl)G%M2esyh9X@A1x0D0sDOY7sO&8u(xe0>G(!hwGsaBhLt{P8Qx{J$ zFfec$=<7UYVBiA&*lx420G})t=)MG=PQV`P-DN1k3N8U}m?3wJ?l3Tv#&J;XP6F@Q zJ@hSL3=B6~j{i9 zj1;|py2$yDo9x+L&Nm~Su78{k=D3{AcIwJ{O%Mm;shUfdvo2?S=UQLwJKe58QJ^pq zZKlS&KS5o>UgXwCjWoM!N{38X{h7b+v#vqR{3~$znp7yyT{h8wd-$HJF#d!mv|8@p zKKuKW?{5^wr4nwNOaIUFdG1D>W@~pndFOTS|9L=+J=9z5|GL(H2KgWB{$K0(pXK_$ zR^>m|^}oIJKhF4{u<}2m>iphp37x45zSQ9Oe;rVYXKqtFb9~l`!SQjZtXWZofT9zwBa+XxEtFm9 z#ZL*8y5F|XO!I-D-$EJ$+WGF>6H7}_W-D}MxNvxKvdKzKO|8wn?;;4amf<_uy-0O$ z*b2LK^QO6rOF^M!HP#86UQ5GaL;|TAn8S@c$zzHMMx;T-?xAAfimRwpN)x2*Rm1Zxr3um@lH@ruMN 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openfpga_flow/regression_test_scripts/basic_reg_test.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index 4e1f55602..0f3abd81d 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -197,7 +197,7 @@ run-task basic_tests/tile_organization/homo_fabric_tile $@ run-task basic_tests/tile_organization/homo_fabric_tile_bl $@ echo -e "Testing tile grouping on a homogeneous FPGA fabric (Preconfigured testbench)"; run-task basic_tests/tile_organization/fabric_tile_global_tile_clock_io_subtile $@ -run-task basic_tests/tile_organization/fabric_tile_perimeter_cb_global_tile_clock_io_subtile $@ +run-task basic_tests/tile_organization/fabric_tile_perimeter_cb_global_tile_clock $@ run-task basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile $@ run-task basic_tests/tile_organization/homo_fabric_tile_preconfig $@ run-task basic_tests/tile_organization/homo_fabric_tile_2x2_preconfig $@ From 229adebe07e88b73c506c67bd44c31b24ffe33d5 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 8 Jul 2024 21:06:12 -0700 Subject: [PATCH 84/91] [doc] new option to write_fabric_verilog --- .../openfpga_commands/fpga_verilog_commands.rst | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst index 2ad413605..b29ce75d8 100644 --- a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst +++ b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst @@ -14,6 +14,14 @@ write_fabric_verilog Specify the output directory for the Verilog netlists. For example, ``--file /temp/fabric_netlist/`` + .. option:: --constant_undriven_inputs + + .. note:: This option is automatically enabled when the option ``perimeter_cb`` of tileable routing resource graph is enabled (see details in :ref`addon_vpr_syntax`). + + .. note:: Enable this option may shadow issues in your FPGA architecture, which causes them difficult to be found in design verification. + + Use constant gnd for undriven wires in Verilog netlists. Recommand to enable when there are boundary routing tracks in FPGA fabric. + .. option:: --default_net_type Specify the default net type for the Verilog netlists. Currently, supported types are ``none`` and ``wire``. Default value: ``none``. From bf484dbc7019a5d9db4a3a7543f4c6e8b1dbb21c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 8 Jul 2024 21:25:12 -0700 Subject: [PATCH 85/91] [doc] add perimeter cb examples on prog clk network --- .../manual/file_formats/clock_network.rst | 15 +++++++++++++++ ...rog_clk_network_example_2x2_perimeter_cb.png | Bin 0 -> 82100 bytes 2 files changed, 15 insertions(+) create mode 100644 docs/source/manual/file_formats/figures/prog_clk_network_example_2x2_perimeter_cb.png diff --git a/docs/source/manual/file_formats/clock_network.rst b/docs/source/manual/file_formats/clock_network.rst index f9c94b5a3..8bab91b43 100644 --- a/docs/source/manual/file_formats/clock_network.rst +++ b/docs/source/manual/file_formats/clock_network.rst @@ -14,6 +14,8 @@ Using the clock network description language, users can define multiple clock ne - A number of switch points which interconnects clock spines using programmable routing switches. See details in :ref:`file_formats_clock_network_switch_point`. - A number of tap points which connect the clock spines to programmable blocks, e.g., CLBs. See details in :ref:`file_formats_clock_network_tap_point`. +The entry point of a clock tree must be at a valid connection block. + .. note:: Please note that the levels of a clock network will be automatically inferred from the clock spines and switch points. Clock network will be **only** built based on the width and the number of levels, as well as the tap points. .. note:: The switch points and clock spines will be used to route a clock network. The switch points will not impact the physical clock network but only impact the configuration of the programmable routing switches in the physical clock network. @@ -45,6 +47,17 @@ Using the clock network description language, users can define multiple clock ne An example of programmable clock network considering a 2x2 FPGA fabric +Note that when the ``perimeter_cb`` is enabled for routing architecture (See details in :ref:`addon_vpr_syntax`), clock entry point can be indeed at the fringe of FPGA fabrics. See example in :numref:`prog_clock_network_example_2x2_perimeter_cb`. + +.. _fig_prog_clock_network_example_2x2_perimeter_cb: + +.. figure:: figures/prog_clk_network_example_2x2_perimeter_cb.png + :width: 100% + :alt: An example of programmable clock network considering a 2x2 FPGA fabric with perimeter cb + + An example of programmable clock network considering a 2x2 FPGA fabric with perimeter cb + + General Settings ^^^^^^^^^^^^^^^^ @@ -134,6 +147,8 @@ Clock Spine Settings The following syntax are applicable to the XML definition tagged by ``spine``. Note that a number of clock spines can be defined under the node ``clock_network``. +.. note:: Use coordinates of connection blocks to define the starting and ending points of clock spines. + .. option:: name="" The unique name of the clock spine. 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z6H|h=?qCKE{j?gBC74wF1ft-?_)IqyeLlkbu_D3HW<(GyUxFL#h}m=}*u}j4>^xz_ zu>_y{B*1M;V(mY}`_}(Ep_8`iup`Fvf5im<-?!_XcOW;_cwl*Mx3YE*NdXbz(9ty1 Js8e%@{2xe7fI9#H literal 0 HcmV?d00001 From 5cb104a5f69cea7f98b9f7f8149acb5d936d9055 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 8 Jul 2024 22:04:40 -0700 Subject: [PATCH 86/91] [test] fixed a bug --- ...k4_N4_40nm_GlobalTileClk_registerable_io_cc_openfpga.xml | 6 +++--- .../global_tile_clock_subtile/config/task.conf | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_registerable_io_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_registerable_io_cc_openfpga.xml index 56186f37f..32f84fff8 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_registerable_io_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_registerable_io_cc_openfpga.xml @@ -195,10 +195,10 @@ - + - - + + diff --git a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock_subtile/config/task.conf b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock_subtile/config/task.conf index d7f7a848c..d6172bb2f 100644 --- a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock_subtile/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock_subtile/config/task.conf @@ -20,7 +20,7 @@ openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scrip openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_registerable_io_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout=2x2_hybrid_io -openfpga_vpr_route_chan_width=60 +openfpga_vpr_route_chan_width=20 [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTileClk_registerable_io_40nm.xml From 1cdb1c59959ca3b2fd4f76ff9ce6751dfb2385a4 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 8 Jul 2024 22:22:08 -0700 Subject: [PATCH 87/91] [core] fixed a bug on calculating subtile pins --- .../fabric/build_top_module_connection.cpp | 20 +++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/openfpga/src/fabric/build_top_module_connection.cpp b/openfpga/src/fabric/build_top_module_connection.cpp index 0a754f352..494b4967f 100644 --- a/openfpga/src/fabric/build_top_module_connection.cpp +++ b/openfpga/src/fabric/build_top_module_connection.cpp @@ -975,6 +975,7 @@ static int build_top_module_global_net_for_given_grid_module( /* Walk through each instance considering the unique sub tile and capacity * range, each instance may have an independent pin to be driven by a global * net! */ + int curr_sub_tile_start_pin_index = 0; for (const t_sub_tile& sub_tile : physical_tile->sub_tiles) { VTR_ASSERT(1 == sub_tile.equivalent_sites.size()); int grid_pin_start_index = physical_tile->num_pins; @@ -995,18 +996,19 @@ static int build_top_module_global_net_for_given_grid_module( /* Port size must match!!! */ if (false == ref_tile_port.contained(tile_port_to_connect)) { VTR_LOG_ERROR( - "Tile annotation '%s' port '%s[%lu:%lu]' is out of the range of " - "physical tile port '%s[%lu:%lu]'!", + "Tile annotation '%s' port '%s' is out of the range of " + "physical tile port '%s'!\n", tile_annotation.global_port_name(tile_global_port).c_str(), - tile_port_to_connect.get_name().c_str(), - tile_port_to_connect.get_lsb(), tile_port_to_connect.get_msb(), - ref_tile_port.get_name().c_str(), ref_tile_port.get_lsb(), - ref_tile_port.get_msb()); + tile_port_to_connect.to_verilog_string().c_str(), + ref_tile_port.to_verilog_string().c_str()); return CMD_EXEC_FATAL_ERROR; } - grid_pin_start_index = + grid_pin_start_index = curr_sub_tile_start_pin_index + (subtile_index - sub_tile.capacity.low) * sub_tile_num_pins + tile_port.absolute_first_pin_index; + VTR_LOG( + "Index %lu for physical tile port '%s.%s.%s'\n!", grid_pin_start_index, + physical_tile->name, sub_tile.name, ref_tile_port.to_verilog_string().c_str()); physical_tile_port = tile_port; break; } @@ -1079,6 +1081,8 @@ static int build_top_module_global_net_for_given_grid_module( } } } + /* Note that the start pin index for a new type of tile should be calculated by the accumulated number of pins of previous sub tiles */ + curr_sub_tile_start_pin_index += sub_tile.num_phy_pins; } return CMD_EXEC_SUCCESS; @@ -1140,7 +1144,7 @@ static int build_top_module_global_net_from_grid_modules( if (true == out_of_range) { VTR_LOG_ERROR( "Coordinate (%lu, %lu) in tile annotation for tile '%s' is out of " - "range (%lu:%lu, %lu:%lu)!", + "range (%lu:%lu, %lu:%lu)!\n", range.x(), range.y(), tile_name.c_str(), start_coord.x(), end_coord.x(), start_coord.y(), end_coord.y()); return CMD_EXEC_FATAL_ERROR; From 04504e4d5db0e1d74b67e1e0e8fa230c6c28f469 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 8 Jul 2024 22:22:59 -0700 Subject: [PATCH 88/91] [core] code format --- openfpga/src/fabric/build_top_module_connection.cpp | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/openfpga/src/fabric/build_top_module_connection.cpp b/openfpga/src/fabric/build_top_module_connection.cpp index 494b4967f..f8f2526bb 100644 --- a/openfpga/src/fabric/build_top_module_connection.cpp +++ b/openfpga/src/fabric/build_top_module_connection.cpp @@ -1003,12 +1003,13 @@ static int build_top_module_global_net_for_given_grid_module( ref_tile_port.to_verilog_string().c_str()); return CMD_EXEC_FATAL_ERROR; } - grid_pin_start_index = curr_sub_tile_start_pin_index + + grid_pin_start_index = + curr_sub_tile_start_pin_index + (subtile_index - sub_tile.capacity.low) * sub_tile_num_pins + tile_port.absolute_first_pin_index; - VTR_LOG( - "Index %lu for physical tile port '%s.%s.%s'\n!", grid_pin_start_index, - physical_tile->name, sub_tile.name, ref_tile_port.to_verilog_string().c_str()); + VTR_LOG("Index %lu for physical tile port '%s.%s.%s'\n!", + grid_pin_start_index, physical_tile->name, sub_tile.name, + ref_tile_port.to_verilog_string().c_str()); physical_tile_port = tile_port; break; } @@ -1081,7 +1082,8 @@ static int build_top_module_global_net_for_given_grid_module( } } } - /* Note that the start pin index for a new type of tile should be calculated by the accumulated number of pins of previous sub tiles */ + /* Note that the start pin index for a new type of tile should be calculated + * by the accumulated number of pins of previous sub tiles */ curr_sub_tile_start_pin_index += sub_tile.num_phy_pins; } From 092b8b038f08a42f951d8af2f636a84f051e54d1 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 8 Jul 2024 22:23:37 -0700 Subject: [PATCH 89/91] [core] remove verbose out --- openfpga/src/fabric/build_top_module_connection.cpp | 3 --- 1 file changed, 3 deletions(-) diff --git a/openfpga/src/fabric/build_top_module_connection.cpp b/openfpga/src/fabric/build_top_module_connection.cpp index f8f2526bb..508516a8d 100644 --- a/openfpga/src/fabric/build_top_module_connection.cpp +++ b/openfpga/src/fabric/build_top_module_connection.cpp @@ -1007,9 +1007,6 @@ static int build_top_module_global_net_for_given_grid_module( curr_sub_tile_start_pin_index + (subtile_index - sub_tile.capacity.low) * sub_tile_num_pins + tile_port.absolute_first_pin_index; - VTR_LOG("Index %lu for physical tile port '%s.%s.%s'\n!", - grid_pin_start_index, physical_tile->name, sub_tile.name, - ref_tile_port.to_verilog_string().c_str()); physical_tile_port = tile_port; break; } From 5efc9d0e00b766c796d9acc7a216a939ae3fb31b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 8 Jul 2024 23:24:16 -0700 Subject: [PATCH 90/91] [test] update golden outputs --- .../and2_fpga_top_analysis.sdc | 56 +- .../ccff_timing.sdc | 840 +- .../disable_configurable_memory_outputs.sdc | 56 +- .../fabric_bitstream.bit | 256 +- .../fabric_bitstream.xml | 716 +- .../golden_outputs_no_time_stamp/fpga_top.v | 14 +- .../gsb_xml/cby_0__1_.xml | 120 +- .../gsb_xml/cby_1__1_.xml | 132 +- .../gsb_xml_no_rr_info/cby_0__1_.xml | 120 +- .../gsb_xml_no_rr_info/cby_1__1_.xml | 132 +- .../and2_fpga_top_analysis.sdc | 108 +- .../ccff_timing.sdc | 6708 +++++++------- .../disable_configurable_memory_outputs.sdc | 108 +- .../fabric_bitstream.bit | 284 +- .../fabric_bitstream.xml | 8124 ++++++++--------- .../golden_outputs_no_time_stamp/fpga_top.v | 104 +- .../gsb_xml/cby_0__1_.xml | 76 +- .../gsb_xml/cby_0__2_.xml | 76 +- .../gsb_xml/cby_0__3_.xml | 76 +- .../gsb_xml/cby_0__4_.xml | 76 +- .../gsb_xml/cby_1__1_.xml | 28 +- .../gsb_xml/cby_1__2_.xml | 28 +- .../gsb_xml/cby_1__3_.xml | 28 +- .../gsb_xml/cby_1__4_.xml | 28 +- .../gsb_xml/cby_2__1_.xml | 28 +- .../gsb_xml/cby_2__2_.xml | 28 +- .../gsb_xml/cby_2__3_.xml | 28 +- .../gsb_xml/cby_2__4_.xml | 28 +- .../gsb_xml/cby_3__1_.xml | 28 +- .../gsb_xml/cby_3__2_.xml | 28 +- .../gsb_xml/cby_3__3_.xml | 28 +- .../gsb_xml/cby_3__4_.xml | 28 +- .../gsb_xml/cby_4__1_.xml | 80 +- .../gsb_xml/cby_4__2_.xml | 80 +- .../gsb_xml/cby_4__3_.xml | 80 +- .../gsb_xml/cby_4__4_.xml | 80 +- .../gsb_xml_no_rr_info/cby_0__1_.xml | 76 +- .../gsb_xml_no_rr_info/cby_0__2_.xml | 76 +- .../gsb_xml_no_rr_info/cby_0__3_.xml | 76 +- .../gsb_xml_no_rr_info/cby_0__4_.xml | 76 +- .../gsb_xml_no_rr_info/cby_1__1_.xml | 28 +- .../gsb_xml_no_rr_info/cby_1__2_.xml | 28 +- .../gsb_xml_no_rr_info/cby_1__3_.xml | 28 +- .../gsb_xml_no_rr_info/cby_1__4_.xml | 28 +- .../gsb_xml_no_rr_info/cby_2__1_.xml | 28 +- .../gsb_xml_no_rr_info/cby_2__2_.xml | 28 +- .../gsb_xml_no_rr_info/cby_2__3_.xml | 28 +- .../gsb_xml_no_rr_info/cby_2__4_.xml | 28 +- .../gsb_xml_no_rr_info/cby_3__1_.xml | 28 +- .../gsb_xml_no_rr_info/cby_3__2_.xml | 28 +- .../gsb_xml_no_rr_info/cby_3__3_.xml | 28 +- .../gsb_xml_no_rr_info/cby_3__4_.xml | 28 +- .../gsb_xml_no_rr_info/cby_4__1_.xml | 80 +- .../gsb_xml_no_rr_info/cby_4__2_.xml | 80 +- .../gsb_xml_no_rr_info/cby_4__3_.xml | 80 +- .../gsb_xml_no_rr_info/cby_4__4_.xml | 80 +- .../and2_fpga_top_analysis.sdc | 56 +- .../ccff_timing.sdc | 840 +- .../disable_configurable_memory_outputs.sdc | 56 +- .../fabric_bitstream.bit | 256 +- .../fabric_bitstream.xml | 716 +- .../golden_outputs_no_time_stamp/fpga_top.v | 14 +- .../gsb_xml/cby_0__1_.xml | 120 +- .../gsb_xml/cby_1__1_.xml | 132 +- .../gsb_xml_no_rr_info/cby_0__1_.xml | 120 +- .../gsb_xml_no_rr_info/cby_1__1_.xml | 132 +- .../and2_fpga_top_analysis.sdc | 124 +- .../ccff_timing.sdc | 3092 +++---- .../disable_configurable_memory_outputs.sdc | 124 +- .../fabric_bitstream.bit | 266 +- .../fabric_bitstream.xml | 3308 +++---- .../golden_outputs_no_time_stamp/fpga_top.v | 36 +- .../gsb_xml/cby_0__1_.xml | 72 +- .../gsb_xml/cby_0__2_.xml | 72 +- .../gsb_xml/cby_1__1_.xml | 56 +- .../gsb_xml/cby_1__2_.xml | 56 +- .../gsb_xml/cby_2__1_.xml | 112 +- .../gsb_xml/cby_2__2_.xml | 112 +- .../gsb_xml_no_rr_info/cby_0__1_.xml | 72 +- .../gsb_xml_no_rr_info/cby_0__2_.xml | 72 +- .../gsb_xml_no_rr_info/cby_1__1_.xml | 56 +- .../gsb_xml_no_rr_info/cby_1__2_.xml | 56 +- .../gsb_xml_no_rr_info/cby_2__1_.xml | 112 +- .../gsb_xml_no_rr_info/cby_2__2_.xml | 112 +- 84 files changed, 15075 insertions(+), 15075 deletions(-) diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc index 8237fc2f9..2ccec1ac6 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc @@ -57,16 +57,24 @@ set_disable_timing gfpga_pad_GPIO_PAD[31] set_disable_timing set[0] set_disable_timing reset[0] set_disable_timing prog_clk[0] -set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q -set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN -set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q -set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q @@ -77,6 +85,10 @@ set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN +set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q +set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN +set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q +set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q @@ -91,30 +103,18 @@ set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/QN set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/ccff_timing.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/ccff_timing.sdc index df2b04e23..5a3b9e3df 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/ccff_timing.sdc +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/ccff_timing.sdc @@ -11,346 +11,6 @@ ############################################# set_units -time ns -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/sb_0__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFF_1_/D 5 set_min_delay -from fpga_top/sb_0__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/sb_0__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFF_2_/D 5 @@ -465,84 +125,8 @@ set_max_delay -from fpga_top/sb_0__0_/mem_right_track_22/DFF_1_/Q -to fpga_top/s set_min_delay -from fpga_top/sb_0__0_/mem_right_track_22/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_24/DFF_0_/D 2.5 set_max_delay -from fpga_top/sb_0__0_/mem_right_track_24/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_24/DFF_1_/D 5 set_min_delay -from fpga_top/sb_0__0_/mem_right_track_24/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_24/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__0_/mem_right_track_24/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__0_/mem_right_track_24/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_24/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_24/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_1_/D 5 set_min_delay -from fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/sb_1__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_2_/D 5 @@ -725,8 +309,424 @@ set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_0_/Q -to fpga_top/cbx_ set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_1_/D 2.5 set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/D 5 set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_1_/D 5 set_min_delay -from fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_2_/D 5 diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/disable_configurable_memory_outputs.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/disable_configurable_memory_outputs.sdc index 022a20fcf..8cd7edd67 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/disable_configurable_memory_outputs.sdc +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/disable_configurable_memory_outputs.sdc @@ -6,16 +6,24 @@ # Organization: University of Utah ############################################# -set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q -set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN -set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q -set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q @@ -26,6 +34,10 @@ set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN +set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q +set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN +set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q +set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q @@ -40,30 +52,18 @@ set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/QN set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_bitstream.bit b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_bitstream.bit index 3387708eb..7c8512c57 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_bitstream.bit +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_bitstream.bit @@ -197,18 +197,7 @@ 0 0 0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 +1 0 0 0 @@ -243,8 +232,19 @@ 0 0 0 -1 -1 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 0 0 0 @@ -267,67 +267,6 @@ 1 1 1 -1 -1 -1 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 0 0 0 @@ -423,34 +362,61 @@ 1 0 1 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 0 0 0 @@ -485,19 +451,8 @@ 0 0 0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 +1 +1 0 0 0 @@ -515,16 +470,61 @@ 1 1 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_bitstream.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_bitstream.xml index 4edf9cf2b..c42176d6b 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_bitstream.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_bitstream.xml @@ -344,721 +344,721 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fpga_top.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fpga_top.v index c8c3d7300..e0098e212 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fpga_top.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fpga_top.v @@ -162,7 +162,7 @@ wire [0:12] sb_1__1__0_chany_bottom_out; .bottom_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_), .bottom_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_), .bottom_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_), - .ccff_head(cbx_1__1__0_ccff_tail), + .ccff_head(grid_io_right_0_ccff_tail), .bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_), .bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_), .bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_), @@ -206,7 +206,7 @@ wire [0:12] sb_1__1__0_chany_bottom_out; .top_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_), .top_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_), .top_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_), - .ccff_head(ccff_head), + .ccff_head(cbx_1__0__0_ccff_tail), .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_), .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_), .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_), @@ -284,7 +284,7 @@ wire [0:12] sb_1__1__0_chany_bottom_out; .right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_5__pin_inpad_0_), .right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_6__pin_inpad_0_), .right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_7__pin_inpad_0_), - .ccff_head(sb_0__1__0_ccff_tail), + .ccff_head(ccff_head), .chany_top_out(sb_0__0__0_chany_top_out[0:12]), .chanx_right_out(sb_0__0__0_chanx_right_out[0:12]), .ccff_tail(sb_0__0__0_ccff_tail)); @@ -338,7 +338,7 @@ wire [0:12] sb_1__1__0_chany_bottom_out; .left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_5__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_6__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_7__pin_inpad_0_), - .ccff_head(grid_io_left_0_ccff_tail), + .ccff_head(sb_0__0__0_ccff_tail), .chany_top_out(sb_1__0__0_chany_top_out[0:12]), .chanx_left_out(sb_1__0__0_chanx_left_out[0:12]), .ccff_tail(sb_1__0__0_ccff_tail)); @@ -365,7 +365,7 @@ wire [0:12] sb_1__1__0_chany_bottom_out; .left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_6__pin_inpad_0_), .left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_7__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_2_), - .ccff_head(grid_io_right_0_ccff_tail), + .ccff_head(grid_io_left_0_ccff_tail), .chany_bottom_out(sb_1__1__0_chany_bottom_out[0:12]), .chanx_left_out(sb_1__1__0_chanx_left_out[0:12]), .ccff_tail(sb_1__1__0_ccff_tail)); @@ -414,7 +414,7 @@ wire [0:12] sb_1__1__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_0__0__0_chany_top_out[0:12]), .chany_top_in(sb_0__1__0_chany_bottom_out[0:12]), - .ccff_head(sb_0__0__0_ccff_tail), + .ccff_head(sb_0__1__0_ccff_tail), .chany_bottom_out(cby_0__1__0_chany_bottom_out[0:12]), .chany_top_out(cby_0__1__0_chany_top_out[0:12]), .right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_0__1__0_right_grid_left_width_0_height_0_subtile_0__pin_I_3_), @@ -433,7 +433,7 @@ wire [0:12] sb_1__1__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_1__0__0_chany_top_out[0:12]), .chany_top_in(sb_1__1__0_chany_bottom_out[0:12]), - .ccff_head(cbx_1__0__0_ccff_tail), + .ccff_head(cbx_1__1__0_ccff_tail), .chany_bottom_out(cby_1__1__0_chany_bottom_out[0:12]), .chany_top_out(cby_1__1__0_chany_top_out[0:12]), .right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml/cby_0__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml/cby_0__1_.xml index 99aadddf5..1943afce4 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml/cby_0__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml/cby_0__1_.xml @@ -1,82 +1,82 @@ - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml/cby_1__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml/cby_1__1_.xml index eefaf5cd9..d4af896d6 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml/cby_1__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml/cby_1__1_.xml @@ -1,90 +1,90 @@ - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__1_.xml index 5ecb11950..0e17019b1 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__1_.xml @@ -1,82 +1,82 @@ - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__1_.xml index edec22d72..010e9b689 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__1_.xml @@ -1,90 +1,90 @@ - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc index 897ef728e..3ef8489eb 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc @@ -153,48 +153,44 @@ set_disable_timing gfpga_pad_GPIO_PAD[127] set_disable_timing set[0] set_disable_timing reset[0] set_disable_timing prog_clk[0] -set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q -set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN -set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q -set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN +set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q +set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN -set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q -set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN +set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q +set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN +set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q +set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q @@ -207,12 +203,16 @@ set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logica set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q @@ -221,6 +221,14 @@ set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q @@ -231,6 +239,8 @@ set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN +set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q +set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q @@ -247,6 +257,14 @@ set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/mem_fle_ set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/mem_fle_*_in_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q @@ -255,32 +273,16 @@ set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN -set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q -set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q @@ -293,8 +295,6 @@ set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN ################################################## # Disable timing for Connection block cbx_1__0_ ################################################## diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/ccff_timing.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/ccff_timing.sdc index bc1f632f0..a44bb6090 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/ccff_timing.sdc +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/ccff_timing.sdc @@ -11,1324 +11,6 @@ ############################################# set_units -time ns -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_3/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_3/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_5/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_5/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_7/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_7/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_11/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_11/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_11/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_11/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_13/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_13/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_13/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_13/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_15/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_15/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_15/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_15/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_3/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_3/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_5/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_5/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_7/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_7/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_11/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_11/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_11/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_11/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_13/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_13/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_13/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_13/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_15/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_15/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_15/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_15/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__4_/mem_left_track_17/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__4_/mem_left_track_17/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__4_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__4_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_3__4_/mem_right_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_3__4_/mem_right_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_3__4_/mem_right_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_3__4_/mem_right_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_3__4_/mem_right_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_3__4_/mem_right_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_3__4_/mem_right_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_3__4_/mem_right_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_3__4_/mem_right_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_3__4_/mem_right_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_3__4_/mem_right_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_3__4_/mem_right_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_3__4_/mem_right_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_3__4_/mem_right_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_3__4_/mem_right_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_3__4_/mem_right_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_3__4_/mem_right_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_3__4_/mem_right_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_3__4_/mem_right_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_3__4_/mem_right_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_3__4_/mem_right_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_3__4_/mem_right_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_3__4_/mem_right_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_3__4_/mem_right_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_3__4_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_3__4_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_3/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_3/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_5/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_5/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_7/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_7/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_11/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_11/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_11/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_11/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_13/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_13/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_13/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_13/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_15/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_15/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_15/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_15/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_19/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_19/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_19/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_19/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_3__4_/mem_left_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_3__4_/mem_left_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_3__4_/mem_left_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_3__4_/mem_left_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_3__4_/mem_left_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_3__4_/mem_left_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_3__4_/mem_left_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_3__4_/mem_left_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_3__4_/mem_left_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_3__4_/mem_left_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_3__4_/mem_left_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_3__4_/mem_left_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_3__4_/mem_left_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_3__4_/mem_left_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_3__4_/mem_left_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_3__4_/mem_left_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_3__4_/mem_left_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_3__4_/mem_left_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_3__4_/mem_left_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_3__4_/mem_left_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_3__4_/mem_left_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_3__4_/mem_left_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_3__4_/mem_left_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_3__4_/mem_left_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__4_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__4_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__4_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__4_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_2__4_/mem_right_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_2__4_/mem_right_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_2__4_/mem_right_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_2__4_/mem_right_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_2__4_/mem_right_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_2__4_/mem_right_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_2__4_/mem_right_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_2__4_/mem_right_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_2__4_/mem_right_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_2__4_/mem_right_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_2__4_/mem_right_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_2__4_/mem_right_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_2__4_/mem_right_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_2__4_/mem_right_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_2__4_/mem_right_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_2__4_/mem_right_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_2__4_/mem_right_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_2__4_/mem_right_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_2__4_/mem_right_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_2__4_/mem_right_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_2__4_/mem_right_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_2__4_/mem_right_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_2__4_/mem_right_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_2__4_/mem_right_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_2__4_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_2__4_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_3/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_3/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_5/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_5/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_7/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_7/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_11/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_11/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_11/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_11/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_13/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_13/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_13/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_13/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_15/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_15/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_15/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_15/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_19/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_19/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_19/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_19/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_2__4_/mem_left_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_2__4_/mem_left_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_2__4_/mem_left_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_2__4_/mem_left_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_2__4_/mem_left_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_2__4_/mem_left_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_2__4_/mem_left_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_2__4_/mem_left_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_2__4_/mem_left_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_2__4_/mem_left_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_2__4_/mem_left_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_2__4_/mem_left_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_2__4_/mem_left_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_2__4_/mem_left_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_2__4_/mem_left_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_2__4_/mem_left_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_2__4_/mem_left_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_2__4_/mem_left_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_2__4_/mem_left_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_2__4_/mem_left_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_2__4_/mem_left_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_2__4_/mem_left_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_2__4_/mem_left_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_2__4_/mem_left_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__4_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__4_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__4_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__4_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__4_/mem_right_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__4_/mem_right_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_1__4_/mem_right_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_1__4_/mem_right_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_1__4_/mem_right_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_1__4_/mem_right_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_1__4_/mem_right_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_1__4_/mem_right_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_1__4_/mem_right_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_1__4_/mem_right_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_1__4_/mem_right_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_1__4_/mem_right_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_1__4_/mem_right_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_1__4_/mem_right_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_1__4_/mem_right_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_1__4_/mem_right_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_1__4_/mem_right_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_1__4_/mem_right_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_1__4_/mem_right_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_1__4_/mem_right_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_1__4_/mem_right_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_1__4_/mem_right_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_1__4_/mem_right_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_1__4_/mem_right_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_1__4_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_1__4_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_3/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_3/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_5/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_5/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_7/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_7/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_11/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_11/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_11/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_11/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_13/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_13/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_13/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_13/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_15/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_15/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_15/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_15/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_19/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_19/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_19/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_19/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_1__4_/mem_left_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_1__4_/mem_left_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__4_/mem_left_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__4_/mem_left_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__4_/mem_left_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__4_/mem_left_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__4_/mem_left_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__4_/mem_left_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_1__4_/mem_left_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_1__4_/mem_left_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__4_/mem_left_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__4_/mem_left_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__4_/mem_left_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__4_/mem_left_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_1__4_/mem_left_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_1__4_/mem_left_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_1__4_/mem_left_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_1__4_/mem_left_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__4_/mem_left_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__4_/mem_left_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__4_/mem_left_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__4_/mem_left_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_1__4_/mem_left_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_1__4_/mem_left_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__4_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__4_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__4_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__4_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_2/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_2/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_4/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_4/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_6/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_6/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_10/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_10/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_10/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_10/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_12/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_12/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_12/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_12/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_14/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_14/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_14/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_14/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_3/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_3/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_5/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_5/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_7/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_7/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_11/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_11/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_11/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_11/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_13/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_13/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_13/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_13/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_15/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_15/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_15/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_15/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__3_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__3_/mem_top_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_0__3_/mem_top_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_0__3_/mem_top_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_0__3_/mem_top_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_0__3_/mem_top_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_0__3_/mem_top_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_0__3_/mem_top_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_0__3_/mem_top_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_0__3_/mem_top_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_0__3_/mem_top_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_0__3_/mem_top_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_0__3_/mem_top_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_0__3_/mem_top_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_0__3_/mem_top_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_0__3_/mem_top_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_0__3_/mem_top_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_0__3_/mem_top_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_0__3_/mem_top_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_0__3_/mem_top_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_0__3_/mem_top_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_0__3_/mem_top_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_0__3_/mem_top_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_0__3_/mem_top_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_0__3_/mem_right_track_2/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_0__3_/mem_right_track_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_2/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_4/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_4/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_6/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_6/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_10/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_10/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_10/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_10/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_12/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_12/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_12/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_12/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_14/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_14/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_14/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_14/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__3_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__3_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__3_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__3_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__3_/mem_bottom_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__3_/mem_bottom_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__3_/mem_bottom_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__3_/mem_bottom_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_0__3_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_0__3_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__3_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__3_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__3_/mem_bottom_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__3_/mem_bottom_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_0__3_/mem_bottom_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_0__3_/mem_bottom_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_0__3_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_0__3_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__3_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__3_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__3_/mem_bottom_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__3_/mem_bottom_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_0__3_/mem_bottom_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_0__3_/mem_bottom_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/cby_0__4_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/cby_0__4_/mem_left_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__4_/mem_left_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__4_/mem_left_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__4_/mem_left_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__4_/mem_left_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__4_/mem_left_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__4_/mem_left_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__4_/mem_left_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__4_/mem_left_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_3/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_3/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_3/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_3/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_4/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_4/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_4/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_4/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_5/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_5/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_5/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_5/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_6/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_6/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_6/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_6/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_7/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_7/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_7/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_7/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__2_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__2_/mem_top_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_0__2_/mem_top_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_0__2_/mem_top_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_0__2_/mem_top_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_0__2_/mem_top_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_0__2_/mem_top_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_0__2_/mem_top_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_0__2_/mem_top_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_0__2_/mem_top_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_0__2_/mem_top_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_0__2_/mem_top_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_0__2_/mem_top_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_0__2_/mem_top_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_0__2_/mem_top_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_0__2_/mem_top_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_0__2_/mem_top_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_0__2_/mem_top_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_0__2_/mem_top_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_0__2_/mem_top_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_0__2_/mem_top_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_0__2_/mem_top_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_0__2_/mem_top_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_0__2_/mem_top_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_0__2_/mem_right_track_2/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_0__2_/mem_right_track_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_2/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_4/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_4/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_6/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_6/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_10/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_10/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_10/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_10/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_12/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_12/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_12/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_12/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_14/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_14/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_14/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_14/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_0__2_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_0__2_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_0__2_/mem_bottom_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_0__2_/mem_bottom_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/cby_0__3_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/cby_0__3_/mem_left_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__3_/mem_left_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__3_/mem_left_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__3_/mem_left_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__3_/mem_left_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__3_/mem_left_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__3_/mem_left_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__3_/mem_left_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__3_/mem_left_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_3/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_3/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_3/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_3/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_4/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_4/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_4/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_4/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_5/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_5/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_5/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_5/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_6/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_6/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_6/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_6/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_7/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_7/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_7/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_7/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__2_/mem_left_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__2_/mem_left_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__2_/mem_left_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__2_/mem_left_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/sb_0__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFF_1_/D 5 set_min_delay -from fpga_top/sb_0__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/sb_0__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_2/DFF_0_/D 5 @@ -1399,82 +81,8 @@ set_max_delay -from fpga_top/sb_0__0_/mem_right_track_14/DFF_1_/Q -to fpga_top/s set_min_delay -from fpga_top/sb_0__0_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_16/DFF_0_/D 2.5 set_max_delay -from fpga_top/sb_0__0_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_16/DFF_1_/D 5 set_min_delay -from fpga_top/sb_0__0_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__0_/mem_right_track_16/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__0_/mem_right_track_16/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_1_/D 5 set_min_delay -from fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/sb_1__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_2_/D 5 @@ -1613,8 +221,1352 @@ set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_0_/Q -to fpga_top/cbx_ set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_1_/D 2.5 set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/D 5 set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_2__0_/mem_top_track_2/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_2__0_/mem_top_track_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_2/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_2/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_2/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_2/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_2/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_10/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_10/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_10/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_10/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_10/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_10/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_10/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_10/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_18/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_18/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_18/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_18/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_18/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_18/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_18/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_18/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_18/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_18/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_18/DFF_2_/Q -to fpga_top/sb_2__0_/mem_right_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_18/DFF_2_/Q -to fpga_top/sb_2__0_/mem_right_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_2__0_/mem_right_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_2__0_/mem_right_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_2__0_/mem_right_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_2__0_/mem_right_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_2__0_/mem_right_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_2__0_/mem_right_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_2__0_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_2__0_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_2__0_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_2__0_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_2__0_/mem_right_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_2__0_/mem_right_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_2__0_/mem_right_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_2__0_/mem_right_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_2__0_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_2__0_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_2__0_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_2__0_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_2__0_/mem_right_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_2__0_/mem_right_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_2__0_/mem_right_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_2__0_/mem_right_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_3__0_/mem_top_track_2/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_3__0_/mem_top_track_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_top_track_2/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_2/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_top_track_2/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_top_track_2/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_top_track_2/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_10/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_10/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_top_track_10/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_10/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_top_track_10/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_10/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_top_track_10/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_top_track_10/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_18/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_18/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_top_track_18/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_18/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_top_track_18/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_18/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_top_track_18/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_18/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_top_track_18/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_18/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_top_track_18/DFF_2_/Q -to fpga_top/sb_3__0_/mem_right_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_top_track_18/DFF_2_/Q -to fpga_top/sb_3__0_/mem_right_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_3__0_/mem_right_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_3__0_/mem_right_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_3__0_/mem_right_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_3__0_/mem_right_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_3__0_/mem_right_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_3__0_/mem_right_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_3__0_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_3__0_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_3__0_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_3__0_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_3__0_/mem_right_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_3__0_/mem_right_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_3__0_/mem_right_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_3__0_/mem_right_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_3__0_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_3__0_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_3__0_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_3__0_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_3__0_/mem_right_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_3__0_/mem_right_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_3__0_/mem_right_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_3__0_/mem_right_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_3__0_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_3__0_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_3__0_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_3__0_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_3__0_/mem_left_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_3__0_/mem_left_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_3__0_/mem_left_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_3__0_/mem_left_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_3__0_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_3__0_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_3__0_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_3__0_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_3__0_/mem_left_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_3__0_/mem_left_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_3__0_/mem_left_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_3__0_/mem_left_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_3__0_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_3__0_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_3__0_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_3__0_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_3__0_/mem_left_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_3__0_/mem_left_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_3__0_/mem_left_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_3__0_/mem_left_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__0_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__0_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_3__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_2/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_top_track_2/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_2/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_top_track_2/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_top_track_2/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_4/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_top_track_2/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_top_track_4/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_4/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_top_track_4/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_top_track_4/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_6/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_top_track_4/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_top_track_6/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_6/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_top_track_6/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_top_track_6/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_top_track_6/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_10/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_10/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_top_track_10/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_10/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_top_track_10/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_10/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_top_track_10/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_12/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_top_track_10/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_12/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_top_track_12/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_12/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_top_track_12/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_12/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_top_track_12/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_14/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_top_track_12/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_14/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_top_track_14/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_14/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_top_track_14/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_14/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_top_track_14/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_top_track_14/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_3/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_3/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_5/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_5/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_7/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_7/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_11/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_11/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_11/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_11/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_13/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_13/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_13/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_13/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_15/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_15/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_15/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_15/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__0_/mem_left_track_17/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__0_/mem_left_track_17/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_4__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_5__4_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_4__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_3__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_2__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__5_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_2/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_2/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_4/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_4/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_6/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_6/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_10/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_10/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_10/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_10/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_12/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_12/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_12/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_12/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_14/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_14/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_14/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_14/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__4_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__4_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_3/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_3/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_5/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_5/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_7/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_7/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_11/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_11/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_11/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_11/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_13/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_13/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_13/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_13/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_15/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_15/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_15/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_15/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_0__4_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__4_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__4_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/cby_0__4_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__4_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/cby_0__4_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__4_/mem_left_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__4_/mem_left_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__4_/mem_left_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__4_/mem_left_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__4_/mem_left_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__4_/mem_left_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__4_/mem_left_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__4_/mem_left_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_3/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_3/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_3/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_4/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_4/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_4/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_4/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_5/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_5/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_5/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_5/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_6/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_6/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_6/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_6/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_7/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__4_/mem_right_ipin_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_7/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__4_/mem_right_ipin_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_7/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__4_/mem_right_ipin_7/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__4_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__4_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__3_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__4_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__3_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_0__3_/mem_top_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_0__3_/mem_top_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_0__3_/mem_top_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_0__3_/mem_top_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_0__3_/mem_top_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_0__3_/mem_top_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_0__3_/mem_top_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_0__3_/mem_top_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_0__3_/mem_top_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_0__3_/mem_top_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_0__3_/mem_top_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_0__3_/mem_top_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_0__3_/mem_top_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_0__3_/mem_top_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_0__3_/mem_top_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_0__3_/mem_top_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_0__3_/mem_top_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_0__3_/mem_top_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_0__3_/mem_top_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_0__3_/mem_top_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_0__3_/mem_top_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_0__3_/mem_top_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_0__3_/mem_right_track_2/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_0__3_/mem_right_track_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_2/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_4/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_4/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_6/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_6/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_10/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_10/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_10/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_10/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_12/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_12/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_12/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_12/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_14/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_14/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_14/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_14/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__3_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__3_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__3_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__3_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__3_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__3_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__3_/mem_bottom_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__3_/mem_bottom_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__3_/mem_bottom_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__3_/mem_bottom_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_0__3_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_0__3_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__3_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__3_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__3_/mem_bottom_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__3_/mem_bottom_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_0__3_/mem_bottom_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_0__3_/mem_bottom_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_0__3_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_0__3_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__3_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__3_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__3_/mem_bottom_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__3_/mem_bottom_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_0__3_/mem_bottom_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_0__3_/mem_bottom_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__3_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/cby_0__3_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__3_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/cby_0__3_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__3_/mem_left_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__3_/mem_left_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__3_/mem_left_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__3_/mem_left_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__3_/mem_left_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__3_/mem_left_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__3_/mem_left_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__3_/mem_left_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_3/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_3/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_3/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_4/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_4/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_4/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_4/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_5/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_5/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_5/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_5/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_6/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_6/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_6/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_6/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_7/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__3_/mem_right_ipin_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_7/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__3_/mem_right_ipin_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_7/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__3_/mem_right_ipin_7/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__3_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__3_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__2_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__2_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_0__2_/mem_top_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_0__2_/mem_top_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_0__2_/mem_top_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_0__2_/mem_top_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_0__2_/mem_top_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_0__2_/mem_top_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_0__2_/mem_top_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_0__2_/mem_top_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_0__2_/mem_top_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_0__2_/mem_top_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_0__2_/mem_top_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_0__2_/mem_top_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_0__2_/mem_top_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_0__2_/mem_top_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_0__2_/mem_top_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_0__2_/mem_top_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_0__2_/mem_top_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_0__2_/mem_top_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_0__2_/mem_top_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_0__2_/mem_top_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_0__2_/mem_top_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_0__2_/mem_top_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_0__2_/mem_right_track_2/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_0__2_/mem_right_track_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_2/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_4/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_4/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_6/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_6/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_10/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_10/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_10/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_10/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_12/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_12/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_12/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_12/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_14/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_14/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_14/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_14/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__2_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__2_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_0__2_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_0__2_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_0__2_/mem_bottom_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_0__2_/mem_bottom_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__2_/mem_left_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__2_/mem_left_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__2_/mem_left_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__2_/mem_left_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_1_/D 5 set_min_delay -from fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_2_/D 5 @@ -1909,148 +1861,136 @@ set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/D 2.5 set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 5 set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 2.5 -set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_2__0_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_2__0_/mem_top_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_2__0_/mem_top_track_2/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_2__0_/mem_top_track_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_2/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_2/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_2/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_2/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_2/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_10/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_10/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_10/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_10/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_10/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_10/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_10/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_10/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_18/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_18/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_18/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_18/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_18/DFF_0_/Q -to fpga_top/sb_2__0_/mem_top_track_18/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_18/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_18/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_18/DFF_1_/Q -to fpga_top/sb_2__0_/mem_top_track_18/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_18/DFF_2_/Q -to fpga_top/sb_2__0_/mem_right_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_18/DFF_2_/Q -to fpga_top/sb_2__0_/mem_right_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_2__0_/mem_right_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_2__0_/mem_right_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_2__0_/mem_right_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_2__0_/mem_right_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_2__0_/mem_right_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_2__0_/mem_right_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_2__0_/mem_right_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_2__0_/mem_right_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_2__0_/mem_right_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_2__0_/mem_right_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_2__0_/mem_right_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_2__0_/mem_right_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_2__0_/mem_right_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_2__0_/mem_right_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_2__0_/mem_right_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_2__0_/mem_right_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_2__0_/mem_right_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_2__0_/mem_right_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_2__0_/mem_right_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_2__0_/mem_right_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_2__0_/mem_right_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_2__0_/mem_right_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFF_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/cby_2__1_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/cby_2__1_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_2__1_/mem_right_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_2__1_/mem_right_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_2__1_/mem_right_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_2__1_/mem_right_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_2__1_/mem_right_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_2__1_/mem_right_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_2__1_/mem_right_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_2__1_/mem_right_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_2__1_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_2__1_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_2__1_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_2__1_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_2__1_/mem_right_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_2__1_/mem_right_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_2__1_/mem_right_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_2__1_/mem_right_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_2__1_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_2__1_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_2__1_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_2__1_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_2__1_/mem_right_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_2__1_/mem_right_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_2__1_/mem_right_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_2__1_/mem_right_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_2__1_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_2__1_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_2__1_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_2__1_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_2__1_/mem_left_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_2__1_/mem_left_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_2__1_/mem_left_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_2__1_/mem_left_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_2__1_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_2__1_/mem_left_ipin_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/cby_2__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_2__1_/mem_left_ipin_0/DFF_1_/D 5 set_min_delay -from fpga_top/cby_2__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_2__1_/mem_left_ipin_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/cby_2__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_2__1_/mem_left_ipin_0/DFF_2_/D 5 @@ -2345,148 +2285,136 @@ set_max_delay -from fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle set_min_delay -from fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_1_/Q -to fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/D 2.5 set_max_delay -from fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 5 set_min_delay -from fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 2.5 -set_max_delay -from fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_3__0_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_3__0_/mem_top_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_3__0_/mem_top_track_2/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_3__0_/mem_top_track_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_top_track_2/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_2/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_top_track_2/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_top_track_2/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_top_track_2/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_10/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_10/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_top_track_10/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_10/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_top_track_10/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_10/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_top_track_10/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_top_track_10/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_18/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_18/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_top_track_18/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_18/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_top_track_18/DFF_0_/Q -to fpga_top/sb_3__0_/mem_top_track_18/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_top_track_18/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_18/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_top_track_18/DFF_1_/Q -to fpga_top/sb_3__0_/mem_top_track_18/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_top_track_18/DFF_2_/Q -to fpga_top/sb_3__0_/mem_right_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_top_track_18/DFF_2_/Q -to fpga_top/sb_3__0_/mem_right_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_3__0_/mem_right_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_3__0_/mem_right_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_3__0_/mem_right_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_3__0_/mem_right_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_3__0_/mem_right_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_3__0_/mem_right_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_3__0_/mem_right_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_3__0_/mem_right_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_3__0_/mem_right_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_3__0_/mem_right_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_3__0_/mem_right_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_3__0_/mem_right_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_3__0_/mem_right_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_3__0_/mem_right_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_3__0_/mem_right_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_3__0_/mem_right_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_3__0_/mem_right_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_3__0_/mem_right_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_3__0_/mem_right_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_3__0_/mem_right_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_3__0_/mem_right_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_3__0_/mem_right_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_3__0_/mem_left_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_3__0_/mem_left_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_3__0_/mem_left_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_3__0_/mem_left_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_3__0_/mem_left_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_3__0_/mem_left_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_3__0_/mem_left_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_3__0_/mem_left_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_3__0_/mem_left_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_3__0_/mem_left_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_3__0_/mem_left_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_3__0_/mem_left_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_3__0_/mem_left_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_3__0_/mem_left_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_3__0_/mem_left_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_3__0_/mem_left_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_3__0_/mem_left_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_3__0_/mem_left_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_3__0_/mem_left_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_3__0_/mem_left_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_3__0_/mem_left_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_3__0_/mem_left_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_3__0_/mem_left_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_3__0_/mem_left_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__0_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__0_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_3/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_4/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_5/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_6/DFF_2_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_0_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_1_/Q -to fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/cby_3__1_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/cby_3__1_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_3__1_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_3__1_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_3__1_/mem_top_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_3__1_/mem_top_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_3__1_/mem_top_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_3__1_/mem_top_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_3__1_/mem_top_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_3__1_/mem_top_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_3__1_/mem_top_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_3__1_/mem_top_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_3__1_/mem_top_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_3__1_/mem_top_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_3__1_/mem_top_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_3__1_/mem_top_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_3__1_/mem_top_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_3__1_/mem_top_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_3__1_/mem_top_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_3__1_/mem_top_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_3__1_/mem_top_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_3__1_/mem_top_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_3__1_/mem_top_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_3__1_/mem_top_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_3__1_/mem_top_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_3__1_/mem_top_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_3__1_/mem_right_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_3__1_/mem_right_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_3__1_/mem_right_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_3__1_/mem_right_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_3__1_/mem_right_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_3__1_/mem_right_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_3__1_/mem_right_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_3__1_/mem_right_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_3__1_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_3__1_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_3__1_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_3__1_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_3__1_/mem_right_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_3__1_/mem_right_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_3__1_/mem_right_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_3__1_/mem_right_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_3__1_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_3__1_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_3__1_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_3__1_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_3__1_/mem_right_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_3__1_/mem_right_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_3__1_/mem_right_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_3__1_/mem_right_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_3__1_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_3__1_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_3__1_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_3__1_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_3__1_/mem_bottom_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_3__1_/mem_bottom_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_3__1_/mem_bottom_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_3__1_/mem_bottom_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_3__1_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_3__1_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_3__1_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_3__1_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_3__1_/mem_bottom_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_3__1_/mem_bottom_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_3__1_/mem_bottom_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_3__1_/mem_bottom_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_3__1_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_3__1_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_3__1_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_3__1_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_3__1_/mem_bottom_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_3__1_/mem_bottom_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_3__1_/mem_bottom_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_3__1_/mem_bottom_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_3__1_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_3__1_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_3__1_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_3__1_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_3__1_/mem_left_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_3__1_/mem_left_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_3__1_/mem_left_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_3__1_/mem_left_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_3__1_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_3__1_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_3__1_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_3__1_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_3__1_/mem_left_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_3__1_/mem_left_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_3__1_/mem_left_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_3__1_/mem_left_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_3__1_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_3__1_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_3__1_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_3__1_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_3__1_/mem_left_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_3__1_/mem_left_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_3__1_/mem_left_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_3__1_/mem_left_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__1_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__1_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_3__1_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_3__1_/mem_left_ipin_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/cby_3__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_3__1_/mem_left_ipin_0/DFF_1_/D 5 set_min_delay -from fpga_top/cby_3__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_3__1_/mem_left_ipin_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/cby_3__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_3__1_/mem_left_ipin_0/DFF_2_/D 5 @@ -2781,144 +2709,128 @@ set_max_delay -from fpga_top/grid_clb_3__1_/logical_tile_clb_mode_clb__0/mem_fle set_min_delay -from fpga_top/grid_clb_3__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_1_/Q -to fpga_top/grid_clb_3__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/D 2.5 set_max_delay -from fpga_top/grid_clb_3__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_3__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 5 set_min_delay -from fpga_top/grid_clb_3__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_3__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 2.5 -set_max_delay -from fpga_top/grid_clb_3__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_4__0_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_clb_3__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_4__0_/mem_top_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_2/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_top_track_2/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_2/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_top_track_2/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_top_track_2/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_4/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_top_track_2/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_top_track_4/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_4/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_top_track_4/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_top_track_4/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_6/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_top_track_4/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_top_track_6/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_6/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_top_track_6/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_top_track_6/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_top_track_6/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_10/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_10/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_top_track_10/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_10/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_top_track_10/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_10/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_top_track_10/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_12/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_top_track_10/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_12/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_top_track_12/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_12/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_top_track_12/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_12/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_top_track_12/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_14/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_top_track_12/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_14/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_top_track_14/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_14/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_top_track_14/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_14/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_top_track_14/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_top_track_14/DFF_1_/Q -to fpga_top/sb_4__0_/mem_top_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_4__0_/mem_top_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_3/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_3/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_5/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_5/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_7/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_7/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_11/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_11/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_11/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_11/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_13/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_13/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_13/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_13/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_15/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_15/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_15/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_15/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_4__0_/mem_left_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_4__0_/mem_left_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__0_/mem_left_track_17/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__0_/mem_left_track_17/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_3/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_4/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_5/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_6/DFF_2_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_0_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_1_/Q -to fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/cby_4__1_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/cby_4__1_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_3__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_4__1_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_3__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_4__1_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_4__1_/mem_top_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_4__1_/mem_top_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_4__1_/mem_top_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_4__1_/mem_top_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_4__1_/mem_top_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_4__1_/mem_top_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_4__1_/mem_top_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_4__1_/mem_top_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_4__1_/mem_top_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_4__1_/mem_top_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_4__1_/mem_top_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_4__1_/mem_top_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_4__1_/mem_top_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_4__1_/mem_top_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_4__1_/mem_top_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_4__1_/mem_top_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_4__1_/mem_top_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_4__1_/mem_top_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_4__1_/mem_top_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_4__1_/mem_top_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_4__1_/mem_top_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_4__1_/mem_top_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_4__1_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_4__1_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_4__1_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_4__1_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_4__1_/mem_bottom_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_4__1_/mem_bottom_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_4__1_/mem_bottom_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_4__1_/mem_bottom_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_4__1_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_4__1_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_4__1_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_4__1_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_4__1_/mem_bottom_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_4__1_/mem_bottom_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_4__1_/mem_bottom_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_4__1_/mem_bottom_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_4__1_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_4__1_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_4__1_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_4__1_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_4__1_/mem_bottom_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_4__1_/mem_bottom_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_4__1_/mem_bottom_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_4__1_/mem_bottom_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_4__1_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_4__1_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_3/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_3/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_5/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_5/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_7/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_7/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_11/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_11/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_11/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_11/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_13/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_13/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_13/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_13/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_15/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_15/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_15/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_15/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_19/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_19/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_19/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_19/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__1_/mem_left_track_19/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__1_/mem_left_track_19/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_4__1_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_4__1_/mem_left_ipin_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/cby_4__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_4__1_/mem_left_ipin_0/DFF_1_/D 5 set_min_delay -from fpga_top/cby_4__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_4__1_/mem_left_ipin_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/cby_4__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_4__1_/mem_left_ipin_0/DFF_2_/D 5 @@ -3251,128 +3163,128 @@ set_max_delay -from fpga_top/grid_clb_4__1_/logical_tile_clb_mode_clb__0/mem_fle set_min_delay -from fpga_top/grid_clb_4__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_1_/Q -to fpga_top/grid_clb_4__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/D 2.5 set_max_delay -from fpga_top/grid_clb_4__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_4__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 5 set_min_delay -from fpga_top/grid_clb_4__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_4__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 2.5 -set_max_delay -from fpga_top/grid_clb_4__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_4__1_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_clb_4__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_4__1_/mem_top_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_4__1_/mem_top_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_4__1_/mem_top_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_4__1_/mem_top_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_4__1_/mem_top_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_4__1_/mem_top_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_4__1_/mem_top_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_4__1_/mem_top_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_4__1_/mem_top_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_4__1_/mem_top_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_4__1_/mem_top_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_4__1_/mem_top_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_4__1_/mem_top_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_4__1_/mem_top_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_4__1_/mem_top_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_4__1_/mem_top_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_4__1_/mem_top_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_4__1_/mem_top_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_4__1_/mem_top_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_4__1_/mem_top_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_4__1_/mem_top_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_4__1_/mem_top_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_4__1_/mem_top_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_4__1_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_4__1_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_4__1_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_4__1_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_4__1_/mem_bottom_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_4__1_/mem_bottom_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_4__1_/mem_bottom_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_4__1_/mem_bottom_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_4__1_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_4__1_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_4__1_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_4__1_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_4__1_/mem_bottom_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_4__1_/mem_bottom_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_4__1_/mem_bottom_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_4__1_/mem_bottom_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_4__1_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_4__1_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_4__1_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_4__1_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_4__1_/mem_bottom_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_4__1_/mem_bottom_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_4__1_/mem_bottom_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_4__1_/mem_bottom_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_4__1_/mem_left_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_4__1_/mem_left_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_3/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_3/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_5/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_5/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_7/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_7/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_11/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_11/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_11/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_11/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_13/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_13/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_13/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_13/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_15/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_15/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_15/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_15/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_19/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_4__1_/mem_left_track_19/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_19/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_4__1_/mem_left_track_19/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__1_/mem_left_track_19/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__1_/mem_left_track_19/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__1_/mem_top_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_4__2_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_4__2_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_4__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_4__2_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_4__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_4__2_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_4__2_/mem_top_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_4__2_/mem_top_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_4__2_/mem_top_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_4__2_/mem_top_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_4__2_/mem_top_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_4__2_/mem_top_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_4__2_/mem_top_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_4__2_/mem_top_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_4__2_/mem_top_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_4__2_/mem_top_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_4__2_/mem_top_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_4__2_/mem_top_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_4__2_/mem_top_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_4__2_/mem_top_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_4__2_/mem_top_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_4__2_/mem_top_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_4__2_/mem_top_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_4__2_/mem_top_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_4__2_/mem_top_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_4__2_/mem_top_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_4__2_/mem_top_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_4__2_/mem_top_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_4__2_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_4__2_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_4__2_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_4__2_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_4__2_/mem_bottom_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_4__2_/mem_bottom_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_4__2_/mem_bottom_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_4__2_/mem_bottom_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_4__2_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_4__2_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_4__2_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_4__2_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_4__2_/mem_bottom_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_4__2_/mem_bottom_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_4__2_/mem_bottom_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_4__2_/mem_bottom_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_4__2_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_4__2_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_4__2_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_4__2_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_4__2_/mem_bottom_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_4__2_/mem_bottom_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_4__2_/mem_bottom_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_4__2_/mem_bottom_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_4__2_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_4__2_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_3/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_3/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_5/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_5/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_7/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_7/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_11/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_11/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_11/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_11/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_13/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_13/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_13/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_13/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_15/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_15/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_15/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_15/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_19/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_19/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_19/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_19/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__2_/mem_left_track_19/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__2_/mem_left_track_19/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__2_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__2_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__2_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_4__2_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__2_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_4__2_/mem_left_ipin_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/cby_4__2_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_4__2_/mem_left_ipin_0/DFF_1_/D 5 set_min_delay -from fpga_top/cby_4__2_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_4__2_/mem_left_ipin_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/cby_4__2_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_4__2_/mem_left_ipin_0/DFF_2_/D 5 @@ -3705,136 +3617,136 @@ set_max_delay -from fpga_top/grid_clb_4__2_/logical_tile_clb_mode_clb__0/mem_fle set_min_delay -from fpga_top/grid_clb_4__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_1_/Q -to fpga_top/grid_clb_4__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/D 2.5 set_max_delay -from fpga_top/grid_clb_4__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_4__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 5 set_min_delay -from fpga_top/grid_clb_4__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_4__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 2.5 -set_max_delay -from fpga_top/grid_clb_4__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_3__1_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_clb_4__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_3__1_/mem_top_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_3__1_/mem_top_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_3__1_/mem_top_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_3__1_/mem_top_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_3__1_/mem_top_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_3__1_/mem_top_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_3__1_/mem_top_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_3__1_/mem_top_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_3__1_/mem_top_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_3__1_/mem_top_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_3__1_/mem_top_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_3__1_/mem_top_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_3__1_/mem_top_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_3__1_/mem_top_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_3__1_/mem_top_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_3__1_/mem_top_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_3__1_/mem_top_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_3__1_/mem_top_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_3__1_/mem_top_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_3__1_/mem_top_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_3__1_/mem_top_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_3__1_/mem_top_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_3__1_/mem_top_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_3__1_/mem_right_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_3__1_/mem_right_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_3__1_/mem_right_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_3__1_/mem_right_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_3__1_/mem_right_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_3__1_/mem_right_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_3__1_/mem_right_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_3__1_/mem_right_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_3__1_/mem_right_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_3__1_/mem_right_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_3__1_/mem_right_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_3__1_/mem_right_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_3__1_/mem_right_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_3__1_/mem_right_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_3__1_/mem_right_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_3__1_/mem_right_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_3__1_/mem_right_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_3__1_/mem_right_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_3__1_/mem_right_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_3__1_/mem_right_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_3__1_/mem_right_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_3__1_/mem_right_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_3__1_/mem_right_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_3__1_/mem_right_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_3__1_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_3__1_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_3__1_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_3__1_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_3__1_/mem_bottom_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_3__1_/mem_bottom_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_3__1_/mem_bottom_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_3__1_/mem_bottom_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_3__1_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_3__1_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_3__1_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_3__1_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_3__1_/mem_bottom_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_3__1_/mem_bottom_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_3__1_/mem_bottom_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_3__1_/mem_bottom_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_3__1_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_3__1_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_3__1_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_3__1_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_3__1_/mem_bottom_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_3__1_/mem_bottom_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_3__1_/mem_bottom_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_3__1_/mem_bottom_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_3__1_/mem_left_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_3__1_/mem_left_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_3__1_/mem_left_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_3__1_/mem_left_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_3__1_/mem_left_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_3__1_/mem_left_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_3__1_/mem_left_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_3__1_/mem_left_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_3__1_/mem_left_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_3__1_/mem_left_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_3__1_/mem_left_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_3__1_/mem_left_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_3__1_/mem_left_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_3__1_/mem_left_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_3__1_/mem_left_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_3__1_/mem_left_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_3__1_/mem_left_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_3__1_/mem_left_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_3__1_/mem_left_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_3__1_/mem_left_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_3__1_/mem_left_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_3__1_/mem_left_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_3__1_/mem_left_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_3__1_/mem_left_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__1_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__1_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__1_/mem_top_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_3__2_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_3__2_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_4__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_3__2_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_4__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_3__2_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_3__2_/mem_top_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_3__2_/mem_top_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_3__2_/mem_top_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_3__2_/mem_top_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_3__2_/mem_top_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_3__2_/mem_top_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_3__2_/mem_top_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_3__2_/mem_top_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_3__2_/mem_top_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_3__2_/mem_top_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_3__2_/mem_top_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_3__2_/mem_top_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_3__2_/mem_top_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_3__2_/mem_top_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_3__2_/mem_top_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_3__2_/mem_top_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_3__2_/mem_top_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_3__2_/mem_top_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_3__2_/mem_top_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_3__2_/mem_top_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_3__2_/mem_top_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_3__2_/mem_top_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_3__2_/mem_right_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_3__2_/mem_right_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_3__2_/mem_right_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_3__2_/mem_right_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_3__2_/mem_right_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_3__2_/mem_right_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_3__2_/mem_right_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_3__2_/mem_right_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_3__2_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_3__2_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_3__2_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_3__2_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_3__2_/mem_right_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_3__2_/mem_right_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_3__2_/mem_right_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_3__2_/mem_right_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_3__2_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_3__2_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_3__2_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_3__2_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_3__2_/mem_right_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_3__2_/mem_right_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_3__2_/mem_right_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_3__2_/mem_right_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_3__2_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_3__2_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_3__2_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_3__2_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_3__2_/mem_bottom_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_3__2_/mem_bottom_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_3__2_/mem_bottom_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_3__2_/mem_bottom_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_3__2_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_3__2_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_3__2_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_3__2_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_3__2_/mem_bottom_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_3__2_/mem_bottom_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_3__2_/mem_bottom_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_3__2_/mem_bottom_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_3__2_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_3__2_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_3__2_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_3__2_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_3__2_/mem_bottom_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_3__2_/mem_bottom_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_3__2_/mem_bottom_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_3__2_/mem_bottom_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_3__2_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_3__2_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_3__2_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_3__2_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_3__2_/mem_left_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_3__2_/mem_left_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_3__2_/mem_left_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_3__2_/mem_left_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_3__2_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_3__2_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_3__2_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_3__2_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_3__2_/mem_left_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_3__2_/mem_left_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_3__2_/mem_left_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_3__2_/mem_left_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_3__2_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_3__2_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_3__2_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_3__2_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_3__2_/mem_left_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_3__2_/mem_left_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_3__2_/mem_left_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_3__2_/mem_left_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__2_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__2_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__2_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__2_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__2_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_3__2_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__2_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_3__2_/mem_left_ipin_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/cby_3__2_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_3__2_/mem_left_ipin_0/DFF_1_/D 5 set_min_delay -from fpga_top/cby_3__2_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_3__2_/mem_left_ipin_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/cby_3__2_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_3__2_/mem_left_ipin_0/DFF_2_/D 5 @@ -4129,136 +4041,136 @@ set_max_delay -from fpga_top/grid_clb_3__2_/logical_tile_clb_mode_clb__0/mem_fle set_min_delay -from fpga_top/grid_clb_3__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_1_/Q -to fpga_top/grid_clb_3__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/D 2.5 set_max_delay -from fpga_top/grid_clb_3__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_3__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 5 set_min_delay -from fpga_top/grid_clb_3__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_3__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 2.5 -set_max_delay -from fpga_top/grid_clb_3__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_clb_3__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_2__1_/mem_right_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_2__1_/mem_right_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_2__1_/mem_right_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_2__1_/mem_right_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_2__1_/mem_right_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_2__1_/mem_right_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_2__1_/mem_right_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_2__1_/mem_right_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_2__1_/mem_right_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_2__1_/mem_right_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_2__1_/mem_right_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_2__1_/mem_right_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_2__1_/mem_right_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_2__1_/mem_right_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_2__1_/mem_right_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_2__1_/mem_right_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_2__1_/mem_right_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_2__1_/mem_right_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_2__1_/mem_right_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_2__1_/mem_right_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_2__1_/mem_right_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_2__1_/mem_right_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_2__1_/mem_right_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_2__1_/mem_right_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_2__1_/mem_left_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_2__1_/mem_left_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_2__1_/mem_left_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_2__1_/mem_left_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_2__1_/mem_left_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_2__1_/mem_left_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_2__1_/mem_left_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_2__1_/mem_left_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__1_/mem_top_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_2__2_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_2__2_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_3__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_2__2_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_3__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_2__2_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_2__2_/mem_top_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_2__2_/mem_top_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_2__2_/mem_top_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_2__2_/mem_top_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_2__2_/mem_top_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_2__2_/mem_top_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_2__2_/mem_top_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_2__2_/mem_top_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_2__2_/mem_top_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_2__2_/mem_top_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_2__2_/mem_top_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_2__2_/mem_top_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_2__2_/mem_top_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_2__2_/mem_top_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_2__2_/mem_top_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_2__2_/mem_top_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_2__2_/mem_top_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_2__2_/mem_top_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_2__2_/mem_top_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_2__2_/mem_top_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_2__2_/mem_top_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_2__2_/mem_top_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_2__2_/mem_right_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_2__2_/mem_right_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_2__2_/mem_right_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_2__2_/mem_right_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_2__2_/mem_right_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_2__2_/mem_right_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_2__2_/mem_right_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_2__2_/mem_right_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_2__2_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_2__2_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_2__2_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_2__2_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_2__2_/mem_right_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_2__2_/mem_right_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_2__2_/mem_right_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_2__2_/mem_right_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_2__2_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_2__2_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_2__2_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_2__2_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_2__2_/mem_right_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_2__2_/mem_right_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_2__2_/mem_right_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_2__2_/mem_right_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_2__2_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_2__2_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_2__2_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_2__2_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_2__2_/mem_left_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_2__2_/mem_left_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_2__2_/mem_left_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_2__2_/mem_left_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_2__2_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_2__2_/mem_left_ipin_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/cby_2__2_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_2__2_/mem_left_ipin_0/DFF_1_/D 5 set_min_delay -from fpga_top/cby_2__2_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_2__2_/mem_left_ipin_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/cby_2__2_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_2__2_/mem_left_ipin_0/DFF_2_/D 5 @@ -4553,136 +4465,136 @@ set_max_delay -from fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle set_min_delay -from fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_1_/Q -to fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/D 2.5 set_max_delay -from fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 5 set_min_delay -from fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 2.5 -set_max_delay -from fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_1__2_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_1__2_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_1__2_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_1__2_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_1__2_/mem_top_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_1__2_/mem_top_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_1__2_/mem_top_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_1__2_/mem_top_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_1__2_/mem_top_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_1__2_/mem_top_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_1__2_/mem_top_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_1__2_/mem_top_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_1__2_/mem_top_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_1__2_/mem_top_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_1__2_/mem_top_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_1__2_/mem_top_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_1__2_/mem_top_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_1__2_/mem_top_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_1__2_/mem_top_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_1__2_/mem_top_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_1__2_/mem_top_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_1__2_/mem_top_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_1__2_/mem_top_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_1__2_/mem_top_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_1__2_/mem_top_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_1__2_/mem_top_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_1__2_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_1__2_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_1__2_/mem_bottom_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_1__2_/mem_bottom_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_1__2_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_1__2_/mem_left_ipin_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/cby_1__2_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_1__2_/mem_left_ipin_0/DFF_1_/D 5 set_min_delay -from fpga_top/cby_1__2_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_1__2_/mem_left_ipin_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/cby_1__2_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_1__2_/mem_left_ipin_0/DFF_2_/D 5 @@ -4977,136 +4889,136 @@ set_max_delay -from fpga_top/grid_clb_1__2_/logical_tile_clb_mode_clb__0/mem_fle set_min_delay -from fpga_top/grid_clb_1__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_1_/Q -to fpga_top/grid_clb_1__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/D 2.5 set_max_delay -from fpga_top/grid_clb_1__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_1__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 5 set_min_delay -from fpga_top/grid_clb_1__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_1__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 2.5 -set_max_delay -from fpga_top/grid_clb_1__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_1__2_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_clb_1__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_1__2_/mem_top_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_1__2_/mem_top_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_1__2_/mem_top_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_1__2_/mem_top_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_1__2_/mem_top_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_1__2_/mem_top_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_1__2_/mem_top_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_1__2_/mem_top_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_1__2_/mem_top_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_1__2_/mem_top_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_1__2_/mem_top_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_1__2_/mem_top_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_1__2_/mem_top_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_1__2_/mem_top_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_1__2_/mem_top_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_1__2_/mem_top_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_1__2_/mem_top_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_1__2_/mem_top_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_1__2_/mem_top_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_1__2_/mem_top_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_1__2_/mem_top_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_1__2_/mem_top_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_1__2_/mem_top_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_1__2_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_1__2_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_1__2_/mem_bottom_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_1__2_/mem_bottom_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__2_/mem_top_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_1__3_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_1__3_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_1__3_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_1__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_1__3_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_1__3_/mem_top_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_1__3_/mem_top_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_1__3_/mem_top_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_1__3_/mem_top_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_1__3_/mem_top_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_1__3_/mem_top_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_1__3_/mem_top_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_1__3_/mem_top_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_1__3_/mem_top_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_1__3_/mem_top_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_1__3_/mem_top_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_1__3_/mem_top_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_1__3_/mem_top_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_1__3_/mem_top_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_1__3_/mem_top_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_1__3_/mem_top_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_1__3_/mem_top_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_1__3_/mem_top_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_1__3_/mem_top_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_1__3_/mem_top_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_1__3_/mem_top_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_1__3_/mem_top_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_1__3_/mem_right_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_1__3_/mem_right_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_1__3_/mem_right_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_1__3_/mem_right_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_1__3_/mem_right_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_1__3_/mem_right_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_1__3_/mem_right_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_1__3_/mem_right_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_1__3_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_1__3_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_1__3_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_1__3_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_1__3_/mem_right_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_1__3_/mem_right_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_1__3_/mem_right_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_1__3_/mem_right_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_1__3_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_1__3_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_1__3_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_1__3_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_1__3_/mem_right_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_1__3_/mem_right_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_1__3_/mem_right_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_1__3_/mem_right_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_1__3_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_1__3_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__3_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__3_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__3_/mem_bottom_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__3_/mem_bottom_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__3_/mem_bottom_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__3_/mem_bottom_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_1__3_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_1__3_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__3_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__3_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__3_/mem_bottom_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__3_/mem_bottom_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_1__3_/mem_bottom_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_1__3_/mem_bottom_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_1__3_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_1__3_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__3_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__3_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__3_/mem_bottom_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__3_/mem_bottom_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_1__3_/mem_bottom_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_1__3_/mem_bottom_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_1__3_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_1__3_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__3_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__3_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__3_/mem_left_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__3_/mem_left_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__3_/mem_left_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__3_/mem_left_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_1__3_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_1__3_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__3_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__3_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__3_/mem_left_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__3_/mem_left_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_1__3_/mem_left_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_1__3_/mem_left_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_1__3_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_1__3_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__3_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__3_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__3_/mem_left_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__3_/mem_left_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_1__3_/mem_left_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_1__3_/mem_left_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__3_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__3_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__3_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__3_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__3_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_1__3_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__3_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_1__3_/mem_left_ipin_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/cby_1__3_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_1__3_/mem_left_ipin_0/DFF_1_/D 5 set_min_delay -from fpga_top/cby_1__3_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_1__3_/mem_left_ipin_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/cby_1__3_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_1__3_/mem_left_ipin_0/DFF_2_/D 5 @@ -5401,136 +5313,136 @@ set_max_delay -from fpga_top/grid_clb_1__3_/logical_tile_clb_mode_clb__0/mem_fle set_min_delay -from fpga_top/grid_clb_1__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_1_/Q -to fpga_top/grid_clb_1__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/D 2.5 set_max_delay -from fpga_top/grid_clb_1__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_1__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 5 set_min_delay -from fpga_top/grid_clb_1__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_1__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 2.5 -set_max_delay -from fpga_top/grid_clb_1__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_2__2_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_clb_1__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_2__2_/mem_top_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_2__2_/mem_top_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_2__2_/mem_top_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_2__2_/mem_top_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_2__2_/mem_top_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_2__2_/mem_top_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_2__2_/mem_top_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_2__2_/mem_top_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_2__2_/mem_top_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_2__2_/mem_top_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_2__2_/mem_top_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_2__2_/mem_top_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_2__2_/mem_top_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_2__2_/mem_top_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_2__2_/mem_top_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_2__2_/mem_top_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_2__2_/mem_top_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_2__2_/mem_top_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_2__2_/mem_top_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_2__2_/mem_top_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_2__2_/mem_top_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_2__2_/mem_top_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_2__2_/mem_top_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_2__2_/mem_right_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_2__2_/mem_right_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_2__2_/mem_right_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_2__2_/mem_right_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_2__2_/mem_right_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_2__2_/mem_right_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_2__2_/mem_right_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_2__2_/mem_right_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_2__2_/mem_right_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_2__2_/mem_right_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_2__2_/mem_right_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_2__2_/mem_right_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_2__2_/mem_right_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_2__2_/mem_right_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_2__2_/mem_right_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_2__2_/mem_right_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_2__2_/mem_right_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_2__2_/mem_right_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_2__2_/mem_right_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_2__2_/mem_right_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_2__2_/mem_right_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_2__2_/mem_right_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_2__2_/mem_right_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_2__2_/mem_right_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_2__2_/mem_left_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_2__2_/mem_left_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_2__2_/mem_left_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_2__2_/mem_left_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_2__2_/mem_left_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_2__2_/mem_left_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_2__2_/mem_left_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_2__2_/mem_left_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__2_/mem_top_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_2__3_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_2__3_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_2__3_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_1__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_2__3_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_2__3_/mem_top_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_2__3_/mem_top_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_2__3_/mem_top_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_2__3_/mem_top_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_2__3_/mem_top_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_2__3_/mem_top_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_2__3_/mem_top_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_2__3_/mem_top_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_2__3_/mem_top_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_2__3_/mem_top_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_2__3_/mem_top_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_2__3_/mem_top_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_2__3_/mem_top_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_2__3_/mem_top_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_2__3_/mem_top_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_2__3_/mem_top_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_2__3_/mem_top_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_2__3_/mem_top_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_2__3_/mem_top_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_2__3_/mem_top_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_2__3_/mem_top_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_2__3_/mem_top_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_2__3_/mem_right_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_2__3_/mem_right_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_2__3_/mem_right_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_2__3_/mem_right_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_2__3_/mem_right_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_2__3_/mem_right_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_2__3_/mem_right_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_2__3_/mem_right_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_2__3_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_2__3_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_2__3_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_2__3_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_2__3_/mem_right_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_2__3_/mem_right_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_2__3_/mem_right_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_2__3_/mem_right_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_2__3_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_2__3_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_2__3_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_2__3_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_2__3_/mem_right_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_2__3_/mem_right_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_2__3_/mem_right_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_2__3_/mem_right_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_2__3_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_2__3_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_2__3_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_2__3_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_2__3_/mem_bottom_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_2__3_/mem_bottom_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_2__3_/mem_bottom_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_2__3_/mem_bottom_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_2__3_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_2__3_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_2__3_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_2__3_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_2__3_/mem_bottom_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_2__3_/mem_bottom_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_2__3_/mem_bottom_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_2__3_/mem_bottom_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_2__3_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_2__3_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_2__3_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_2__3_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_2__3_/mem_bottom_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_2__3_/mem_bottom_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_2__3_/mem_bottom_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_2__3_/mem_bottom_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_2__3_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_2__3_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_2__3_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_2__3_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_2__3_/mem_left_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_2__3_/mem_left_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_2__3_/mem_left_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_2__3_/mem_left_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_2__3_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_2__3_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_2__3_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_2__3_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_2__3_/mem_left_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_2__3_/mem_left_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_2__3_/mem_left_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_2__3_/mem_left_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_2__3_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_2__3_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_2__3_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_2__3_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_2__3_/mem_left_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_2__3_/mem_left_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_2__3_/mem_left_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_2__3_/mem_left_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__3_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__3_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__3_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__3_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__3_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_2__3_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__3_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_2__3_/mem_left_ipin_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/cby_2__3_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_2__3_/mem_left_ipin_0/DFF_1_/D 5 set_min_delay -from fpga_top/cby_2__3_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_2__3_/mem_left_ipin_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/cby_2__3_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_2__3_/mem_left_ipin_0/DFF_2_/D 5 @@ -5825,136 +5737,136 @@ set_max_delay -from fpga_top/grid_clb_2__3_/logical_tile_clb_mode_clb__0/mem_fle set_min_delay -from fpga_top/grid_clb_2__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_1_/Q -to fpga_top/grid_clb_2__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/D 2.5 set_max_delay -from fpga_top/grid_clb_2__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_2__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 5 set_min_delay -from fpga_top/grid_clb_2__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_2__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 2.5 -set_max_delay -from fpga_top/grid_clb_2__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_3__2_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_clb_2__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_3__2_/mem_top_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_3__2_/mem_top_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_3__2_/mem_top_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_3__2_/mem_top_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_3__2_/mem_top_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_3__2_/mem_top_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_3__2_/mem_top_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_3__2_/mem_top_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_3__2_/mem_top_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_3__2_/mem_top_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_3__2_/mem_top_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_3__2_/mem_top_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_3__2_/mem_top_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_3__2_/mem_top_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_3__2_/mem_top_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_3__2_/mem_top_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_3__2_/mem_top_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_3__2_/mem_top_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_3__2_/mem_top_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_3__2_/mem_top_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_3__2_/mem_top_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_3__2_/mem_top_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_3__2_/mem_top_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_3__2_/mem_right_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_3__2_/mem_right_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_3__2_/mem_right_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_3__2_/mem_right_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_3__2_/mem_right_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_3__2_/mem_right_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_3__2_/mem_right_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_3__2_/mem_right_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_3__2_/mem_right_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_3__2_/mem_right_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_3__2_/mem_right_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_3__2_/mem_right_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_3__2_/mem_right_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_3__2_/mem_right_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_3__2_/mem_right_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_3__2_/mem_right_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_3__2_/mem_right_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_3__2_/mem_right_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_3__2_/mem_right_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_3__2_/mem_right_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_3__2_/mem_right_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_3__2_/mem_right_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_3__2_/mem_right_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_3__2_/mem_right_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_3__2_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_3__2_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_3__2_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_3__2_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_3__2_/mem_bottom_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_3__2_/mem_bottom_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_3__2_/mem_bottom_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_3__2_/mem_bottom_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_3__2_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_3__2_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_3__2_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_3__2_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_3__2_/mem_bottom_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_3__2_/mem_bottom_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_3__2_/mem_bottom_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_3__2_/mem_bottom_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_3__2_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_3__2_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_3__2_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_3__2_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_3__2_/mem_bottom_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_3__2_/mem_bottom_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_3__2_/mem_bottom_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_3__2_/mem_bottom_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_3__2_/mem_left_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_3__2_/mem_left_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_3__2_/mem_left_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_3__2_/mem_left_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_3__2_/mem_left_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_3__2_/mem_left_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_3__2_/mem_left_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_3__2_/mem_left_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_3__2_/mem_left_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_3__2_/mem_left_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_3__2_/mem_left_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_3__2_/mem_left_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_3__2_/mem_left_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_3__2_/mem_left_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_3__2_/mem_left_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_3__2_/mem_left_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_3__2_/mem_left_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_3__2_/mem_left_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_3__2_/mem_left_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_3__2_/mem_left_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_3__2_/mem_left_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_3__2_/mem_left_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_3__2_/mem_left_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_3__2_/mem_left_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__2_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__2_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__2_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__2_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__2_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__2_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__2_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__2_/mem_top_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__2_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_3__3_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__2_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_3__3_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_2__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_3__3_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_2__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_3__3_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_3__3_/mem_top_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_3__3_/mem_top_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_3__3_/mem_top_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_3__3_/mem_top_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_3__3_/mem_top_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_3__3_/mem_top_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_3__3_/mem_top_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_3__3_/mem_top_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_3__3_/mem_top_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_3__3_/mem_top_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_3__3_/mem_top_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_3__3_/mem_top_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_3__3_/mem_top_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_3__3_/mem_top_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_3__3_/mem_top_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_3__3_/mem_top_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_3__3_/mem_top_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_3__3_/mem_top_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_3__3_/mem_top_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_3__3_/mem_top_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_3__3_/mem_top_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_3__3_/mem_top_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_3__3_/mem_right_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_3__3_/mem_right_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_3__3_/mem_right_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_3__3_/mem_right_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_3__3_/mem_right_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_3__3_/mem_right_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_3__3_/mem_right_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_3__3_/mem_right_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_3__3_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_3__3_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_3__3_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_3__3_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_3__3_/mem_right_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_3__3_/mem_right_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_3__3_/mem_right_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_3__3_/mem_right_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_3__3_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_3__3_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_3__3_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_3__3_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_3__3_/mem_right_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_3__3_/mem_right_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_3__3_/mem_right_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_3__3_/mem_right_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_3__3_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_3__3_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_3__3_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_3__3_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_3__3_/mem_bottom_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_3__3_/mem_bottom_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_3__3_/mem_bottom_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_3__3_/mem_bottom_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_3__3_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_3__3_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_3__3_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_3__3_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_3__3_/mem_bottom_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_3__3_/mem_bottom_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_3__3_/mem_bottom_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_3__3_/mem_bottom_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_3__3_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_3__3_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_3__3_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_3__3_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_3__3_/mem_bottom_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_3__3_/mem_bottom_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_3__3_/mem_bottom_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_3__3_/mem_bottom_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_3__3_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_3__3_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_3__3_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_3__3_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_3__3_/mem_left_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_3__3_/mem_left_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_3__3_/mem_left_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_3__3_/mem_left_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_3__3_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_3__3_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_3__3_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_3__3_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_3__3_/mem_left_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_3__3_/mem_left_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_3__3_/mem_left_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_3__3_/mem_left_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_3__3_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_3__3_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_3__3_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_3__3_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_3__3_/mem_left_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_3__3_/mem_left_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_3__3_/mem_left_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_3__3_/mem_left_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__3_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__3_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__3_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__3_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__3_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_3__3_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__3_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_3__3_/mem_left_ipin_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/cby_3__3_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_3__3_/mem_left_ipin_0/DFF_1_/D 5 set_min_delay -from fpga_top/cby_3__3_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_3__3_/mem_left_ipin_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/cby_3__3_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_3__3_/mem_left_ipin_0/DFF_2_/D 5 @@ -6249,128 +6161,128 @@ set_max_delay -from fpga_top/grid_clb_3__3_/logical_tile_clb_mode_clb__0/mem_fle set_min_delay -from fpga_top/grid_clb_3__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_1_/Q -to fpga_top/grid_clb_3__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/D 2.5 set_max_delay -from fpga_top/grid_clb_3__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_3__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 5 set_min_delay -from fpga_top/grid_clb_3__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_3__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 2.5 -set_max_delay -from fpga_top/grid_clb_3__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_4__2_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_clb_3__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_4__2_/mem_top_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_4__2_/mem_top_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_4__2_/mem_top_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_4__2_/mem_top_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_4__2_/mem_top_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_4__2_/mem_top_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_4__2_/mem_top_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_4__2_/mem_top_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_4__2_/mem_top_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_4__2_/mem_top_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_4__2_/mem_top_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_4__2_/mem_top_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_4__2_/mem_top_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_4__2_/mem_top_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_4__2_/mem_top_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_4__2_/mem_top_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_4__2_/mem_top_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_4__2_/mem_top_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_4__2_/mem_top_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_4__2_/mem_top_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_4__2_/mem_top_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_4__2_/mem_top_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_4__2_/mem_top_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_4__2_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_4__2_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_4__2_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_4__2_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_4__2_/mem_bottom_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_4__2_/mem_bottom_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_4__2_/mem_bottom_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_4__2_/mem_bottom_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_4__2_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_4__2_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_4__2_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_4__2_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_4__2_/mem_bottom_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_4__2_/mem_bottom_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_4__2_/mem_bottom_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_4__2_/mem_bottom_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_4__2_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_4__2_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_4__2_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_4__2_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_4__2_/mem_bottom_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_4__2_/mem_bottom_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_4__2_/mem_bottom_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_4__2_/mem_bottom_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_4__2_/mem_left_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_4__2_/mem_left_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_3/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_3/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_5/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_5/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_7/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_7/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_11/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_11/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_11/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_11/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_13/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_13/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_13/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_13/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_15/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_15/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_15/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_15/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_19/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_4__2_/mem_left_track_19/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_19/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_4__2_/mem_left_track_19/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__2_/mem_left_track_19/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__2_/mem_left_track_19/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__2_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__2_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__2_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__2_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__2_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__2_/mem_top_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__2_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_4__3_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__2_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_4__3_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_3__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_4__3_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_3__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_4__3_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_4__3_/mem_top_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_4__3_/mem_top_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_4__3_/mem_top_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_4__3_/mem_top_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_4__3_/mem_top_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_4__3_/mem_top_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_4__3_/mem_top_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_4__3_/mem_top_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_4__3_/mem_top_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_4__3_/mem_top_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_4__3_/mem_top_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_4__3_/mem_top_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_4__3_/mem_top_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_4__3_/mem_top_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_4__3_/mem_top_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_4__3_/mem_top_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_4__3_/mem_top_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_4__3_/mem_top_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_4__3_/mem_top_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_4__3_/mem_top_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_4__3_/mem_top_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_4__3_/mem_top_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_4__3_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_4__3_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_4__3_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_4__3_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_4__3_/mem_bottom_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_4__3_/mem_bottom_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_4__3_/mem_bottom_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_4__3_/mem_bottom_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_4__3_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_4__3_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_4__3_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_4__3_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_4__3_/mem_bottom_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_4__3_/mem_bottom_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_4__3_/mem_bottom_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_4__3_/mem_bottom_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_4__3_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_4__3_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_4__3_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_4__3_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_4__3_/mem_bottom_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_4__3_/mem_bottom_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_4__3_/mem_bottom_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_4__3_/mem_bottom_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_4__3_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_4__3_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_3/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_3/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_5/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_5/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_7/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_7/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_11/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_11/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_11/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_11/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_13/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_13/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_13/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_13/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_15/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_15/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_15/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_15/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_19/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_19/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_19/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_19/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__3_/mem_left_track_19/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__3_/mem_left_track_19/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__3_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__3_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__3_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_4__3_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__3_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_4__3_/mem_left_ipin_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/cby_4__3_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_4__3_/mem_left_ipin_0/DFF_1_/D 5 set_min_delay -from fpga_top/cby_4__3_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_4__3_/mem_left_ipin_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/cby_4__3_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_4__3_/mem_left_ipin_0/DFF_2_/D 5 @@ -6703,128 +6615,144 @@ set_max_delay -from fpga_top/grid_clb_4__3_/logical_tile_clb_mode_clb__0/mem_fle set_min_delay -from fpga_top/grid_clb_4__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_1_/Q -to fpga_top/grid_clb_4__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/D 2.5 set_max_delay -from fpga_top/grid_clb_4__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_4__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 5 set_min_delay -from fpga_top/grid_clb_4__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_4__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 2.5 -set_max_delay -from fpga_top/grid_clb_4__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_4__3_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_clb_4__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_4__3_/mem_top_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_4__3_/mem_top_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_4__3_/mem_top_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_4__3_/mem_top_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_4__3_/mem_top_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_4__3_/mem_top_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_4__3_/mem_top_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_4__3_/mem_top_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_4__3_/mem_top_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_4__3_/mem_top_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_4__3_/mem_top_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_4__3_/mem_top_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_4__3_/mem_top_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_4__3_/mem_top_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_4__3_/mem_top_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_4__3_/mem_top_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_4__3_/mem_top_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_4__3_/mem_top_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_4__3_/mem_top_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_4__3_/mem_top_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_4__3_/mem_top_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_4__3_/mem_top_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_4__3_/mem_top_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_4__3_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_4__3_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_4__3_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_4__3_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_4__3_/mem_bottom_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_4__3_/mem_bottom_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_4__3_/mem_bottom_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_4__3_/mem_bottom_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_4__3_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_4__3_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_4__3_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_4__3_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_4__3_/mem_bottom_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_4__3_/mem_bottom_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_4__3_/mem_bottom_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_4__3_/mem_bottom_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_4__3_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_4__3_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_4__3_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_4__3_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_4__3_/mem_bottom_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_4__3_/mem_bottom_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_4__3_/mem_bottom_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_4__3_/mem_bottom_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_4__3_/mem_left_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_4__3_/mem_left_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_3/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_3/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_5/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_5/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_7/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_7/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_11/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_11/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_11/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_11/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_13/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_13/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_13/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_13/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_15/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_15/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_15/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_15/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_19/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_4__3_/mem_left_track_19/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_19/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_4__3_/mem_left_track_19/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_4__3_/mem_left_track_19/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_4__3_/mem_left_track_19/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__3_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__3_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__3_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_4__3_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_4__3_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__3_/mem_top_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_4__3_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_4__4_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_4__3_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_4__4_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_4__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_4__4_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_4__3_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_4__4_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_3/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_3/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_5/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_5/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_7/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_7/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_11/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_11/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_11/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_11/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_13/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_13/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_13/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_13/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_15/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_15/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_15/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_15/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_4__4_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_4__4_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_3/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_3/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_5/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_5/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_7/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_7/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_11/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_11/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_11/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_11/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_13/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_13/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_13/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_13/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_15/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_15/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_15/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_15/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_4__4_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_4__4_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_4__4_/mem_left_track_17/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_4__4_/mem_left_track_17/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_4__4_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_4__4_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_4__4_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_4__4_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_4__4_/mem_left_ipin_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/cby_4__4_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_4__4_/mem_left_ipin_0/DFF_1_/D 5 set_min_delay -from fpga_top/cby_4__4_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_4__4_/mem_left_ipin_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/cby_4__4_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_4__4_/mem_left_ipin_0/DFF_2_/D 5 @@ -7157,136 +7085,160 @@ set_max_delay -from fpga_top/grid_clb_4__4_/logical_tile_clb_mode_clb__0/mem_fle set_min_delay -from fpga_top/grid_clb_4__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_1_/Q -to fpga_top/grid_clb_4__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/D 2.5 set_max_delay -from fpga_top/grid_clb_4__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_4__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 5 set_min_delay -from fpga_top/grid_clb_4__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_4__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 2.5 -set_max_delay -from fpga_top/grid_clb_4__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_3__3_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_clb_4__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_3__3_/mem_top_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_3__3_/mem_top_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_3__3_/mem_top_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_3__3_/mem_top_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_3__3_/mem_top_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_3__3_/mem_top_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_3__3_/mem_top_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_3__3_/mem_top_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_3__3_/mem_top_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_3__3_/mem_top_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_3__3_/mem_top_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_3__3_/mem_top_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_3__3_/mem_top_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_3__3_/mem_top_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_3__3_/mem_top_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_3__3_/mem_top_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_3__3_/mem_top_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_3__3_/mem_top_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_3__3_/mem_top_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_3__3_/mem_top_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_3__3_/mem_top_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_3__3_/mem_top_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_3__3_/mem_top_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_3__3_/mem_right_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_3__3_/mem_right_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_3__3_/mem_right_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_3__3_/mem_right_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_3__3_/mem_right_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_3__3_/mem_right_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_3__3_/mem_right_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_3__3_/mem_right_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_3__3_/mem_right_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_3__3_/mem_right_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_3__3_/mem_right_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_3__3_/mem_right_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_3__3_/mem_right_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_3__3_/mem_right_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_3__3_/mem_right_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_3__3_/mem_right_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_3__3_/mem_right_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_3__3_/mem_right_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_3__3_/mem_right_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_3__3_/mem_right_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_3__3_/mem_right_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_3__3_/mem_right_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_3__3_/mem_right_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_3__3_/mem_right_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_3__3_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_3__3_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_3__3_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_3__3_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_3__3_/mem_bottom_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_3__3_/mem_bottom_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_3__3_/mem_bottom_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_3__3_/mem_bottom_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_3__3_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_3__3_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_3__3_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_3__3_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_3__3_/mem_bottom_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_3__3_/mem_bottom_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_3__3_/mem_bottom_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_3__3_/mem_bottom_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_3__3_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_3__3_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_3__3_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_3__3_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_3__3_/mem_bottom_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_3__3_/mem_bottom_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_3__3_/mem_bottom_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_3__3_/mem_bottom_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_3__3_/mem_left_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_3__3_/mem_left_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_3__3_/mem_left_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_3__3_/mem_left_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_3__3_/mem_left_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_3__3_/mem_left_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_3__3_/mem_left_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_3__3_/mem_left_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_3__3_/mem_left_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_3__3_/mem_left_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_3__3_/mem_left_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_3__3_/mem_left_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_3__3_/mem_left_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_3__3_/mem_left_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_3__3_/mem_left_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_3__3_/mem_left_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_3__3_/mem_left_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_3__3_/mem_left_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_3__3_/mem_left_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_3__3_/mem_left_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_3__3_/mem_left_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_3__3_/mem_left_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_3__3_/mem_left_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_3__3_/mem_left_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_3__3_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_3__3_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__3_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__3_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__3_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_3__3_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_3__3_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__3_/mem_top_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_3__3_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_3__4_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_3__3_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_3__4_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_4__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_3__4_/mem_right_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_4__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_3__4_/mem_right_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_3__4_/mem_right_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_3__4_/mem_right_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_3__4_/mem_right_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_3__4_/mem_right_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_3__4_/mem_right_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_3__4_/mem_right_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_3__4_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_3__4_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_3__4_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_3__4_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_3__4_/mem_right_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_3__4_/mem_right_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_3__4_/mem_right_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_3__4_/mem_right_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_3__4_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_3__4_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_3__4_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_3__4_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_3__4_/mem_right_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_3__4_/mem_right_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_3__4_/mem_right_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_3__4_/mem_right_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_3__4_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_3__4_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_3/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_3/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_5/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_5/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_7/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_7/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_11/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_11/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_11/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_11/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_13/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_13/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_13/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_13/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_15/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_15/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_15/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_15/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_19/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_3__4_/mem_bottom_track_19/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_19/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_3__4_/mem_bottom_track_19/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_3__4_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_3__4_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_3__4_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_3__4_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_3__4_/mem_left_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_3__4_/mem_left_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_3__4_/mem_left_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_3__4_/mem_left_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_3__4_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_3__4_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_3__4_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_3__4_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_3__4_/mem_left_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_3__4_/mem_left_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_3__4_/mem_left_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_3__4_/mem_left_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_3__4_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_3__4_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_3__4_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_3__4_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_3__4_/mem_left_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_3__4_/mem_left_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_3__4_/mem_left_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_3__4_/mem_left_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_3__4_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_3__4_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_3__4_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_3__4_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_3__4_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_3__4_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_3__4_/mem_left_ipin_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/cby_3__4_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_3__4_/mem_left_ipin_0/DFF_1_/D 5 set_min_delay -from fpga_top/cby_3__4_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_3__4_/mem_left_ipin_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/cby_3__4_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_3__4_/mem_left_ipin_0/DFF_2_/D 5 @@ -7581,136 +7533,160 @@ set_max_delay -from fpga_top/grid_clb_3__4_/logical_tile_clb_mode_clb__0/mem_fle set_min_delay -from fpga_top/grid_clb_3__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_1_/Q -to fpga_top/grid_clb_3__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/D 2.5 set_max_delay -from fpga_top/grid_clb_3__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_3__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 5 set_min_delay -from fpga_top/grid_clb_3__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_3__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 2.5 -set_max_delay -from fpga_top/grid_clb_3__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_2__3_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_clb_3__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_2__3_/mem_top_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_2__3_/mem_top_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_2__3_/mem_top_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_2__3_/mem_top_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_2__3_/mem_top_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_2__3_/mem_top_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_2__3_/mem_top_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_2__3_/mem_top_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_2__3_/mem_top_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_2__3_/mem_top_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_2__3_/mem_top_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_2__3_/mem_top_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_2__3_/mem_top_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_2__3_/mem_top_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_2__3_/mem_top_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_2__3_/mem_top_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_2__3_/mem_top_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_2__3_/mem_top_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_2__3_/mem_top_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_2__3_/mem_top_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_2__3_/mem_top_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_2__3_/mem_top_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_2__3_/mem_top_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_2__3_/mem_right_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_2__3_/mem_right_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_2__3_/mem_right_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_2__3_/mem_right_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_2__3_/mem_right_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_2__3_/mem_right_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_2__3_/mem_right_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_2__3_/mem_right_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_2__3_/mem_right_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_2__3_/mem_right_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_2__3_/mem_right_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_2__3_/mem_right_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_2__3_/mem_right_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_2__3_/mem_right_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_2__3_/mem_right_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_2__3_/mem_right_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_2__3_/mem_right_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_2__3_/mem_right_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_2__3_/mem_right_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_2__3_/mem_right_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_2__3_/mem_right_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_2__3_/mem_right_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_2__3_/mem_right_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_2__3_/mem_right_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_2__3_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_2__3_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_2__3_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_2__3_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_2__3_/mem_bottom_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_2__3_/mem_bottom_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_2__3_/mem_bottom_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_2__3_/mem_bottom_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_2__3_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_2__3_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_2__3_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_2__3_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_2__3_/mem_bottom_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_2__3_/mem_bottom_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_2__3_/mem_bottom_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_2__3_/mem_bottom_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_2__3_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_2__3_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_2__3_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_2__3_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_2__3_/mem_bottom_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_2__3_/mem_bottom_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_2__3_/mem_bottom_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_2__3_/mem_bottom_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_2__3_/mem_left_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_2__3_/mem_left_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_2__3_/mem_left_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_2__3_/mem_left_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_2__3_/mem_left_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_2__3_/mem_left_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_2__3_/mem_left_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_2__3_/mem_left_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_2__3_/mem_left_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_2__3_/mem_left_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_2__3_/mem_left_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_2__3_/mem_left_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_2__3_/mem_left_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_2__3_/mem_left_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_2__3_/mem_left_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_2__3_/mem_left_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_2__3_/mem_left_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_2__3_/mem_left_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_2__3_/mem_left_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_2__3_/mem_left_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_2__3_/mem_left_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_2__3_/mem_left_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_2__3_/mem_left_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_2__3_/mem_left_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__3_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_2__3_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__3_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__3_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__3_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__3_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_2__3_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__3_/mem_top_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__3_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_2__4_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_2__3_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_2__4_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_3__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_2__4_/mem_right_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_3__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_2__4_/mem_right_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_2__4_/mem_right_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_2__4_/mem_right_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_2__4_/mem_right_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_2__4_/mem_right_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_2__4_/mem_right_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_2__4_/mem_right_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_2__4_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_2__4_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_2__4_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_2__4_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_2__4_/mem_right_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_2__4_/mem_right_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_2__4_/mem_right_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_2__4_/mem_right_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_2__4_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_2__4_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_2__4_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_2__4_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_2__4_/mem_right_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_2__4_/mem_right_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_2__4_/mem_right_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_2__4_/mem_right_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_2__4_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_2__4_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_3/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_3/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_5/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_5/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_7/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_7/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_11/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_11/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_11/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_11/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_13/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_13/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_13/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_13/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_15/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_15/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_15/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_15/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_19/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_2__4_/mem_bottom_track_19/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_19/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_2__4_/mem_bottom_track_19/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_2__4_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_2__4_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_2__4_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_2__4_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_2__4_/mem_left_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_2__4_/mem_left_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_2__4_/mem_left_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_2__4_/mem_left_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_2__4_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_2__4_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_2__4_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_2__4_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_2__4_/mem_left_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_2__4_/mem_left_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_2__4_/mem_left_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_2__4_/mem_left_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_2__4_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_2__4_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_2__4_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_2__4_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_2__4_/mem_left_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_2__4_/mem_left_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_2__4_/mem_left_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_2__4_/mem_left_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__4_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_2__4_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_2__4_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__4_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_2__4_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_2__4_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_2__4_/mem_left_ipin_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/cby_2__4_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_2__4_/mem_left_ipin_0/DFF_1_/D 5 set_min_delay -from fpga_top/cby_2__4_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_2__4_/mem_left_ipin_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/cby_2__4_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_2__4_/mem_left_ipin_0/DFF_2_/D 5 @@ -8005,136 +7981,160 @@ set_max_delay -from fpga_top/grid_clb_2__4_/logical_tile_clb_mode_clb__0/mem_fle set_min_delay -from fpga_top/grid_clb_2__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_1_/Q -to fpga_top/grid_clb_2__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/D 2.5 set_max_delay -from fpga_top/grid_clb_2__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_2__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 5 set_min_delay -from fpga_top/grid_clb_2__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_2__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 2.5 -set_max_delay -from fpga_top/grid_clb_2__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_1__3_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_clb_2__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_1__3_/mem_top_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_1__3_/mem_top_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_1__3_/mem_top_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_1__3_/mem_top_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_1__3_/mem_top_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_1__3_/mem_top_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_1__3_/mem_top_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_1__3_/mem_top_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_top_track_0/DFF_3_/Q -to fpga_top/sb_1__3_/mem_top_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_1__3_/mem_top_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_1__3_/mem_top_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_1__3_/mem_top_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_1__3_/mem_top_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_1__3_/mem_top_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_top_track_8/DFF_2_/Q -to fpga_top/sb_1__3_/mem_top_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_1__3_/mem_top_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_top_track_8/DFF_3_/Q -to fpga_top/sb_1__3_/mem_top_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_1__3_/mem_top_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_1__3_/mem_top_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_1__3_/mem_top_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_1__3_/mem_top_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_1__3_/mem_top_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_top_track_16/DFF_2_/Q -to fpga_top/sb_1__3_/mem_top_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_1__3_/mem_right_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_top_track_16/DFF_3_/Q -to fpga_top/sb_1__3_/mem_right_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_1__3_/mem_right_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_1__3_/mem_right_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_1__3_/mem_right_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_1__3_/mem_right_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_1__3_/mem_right_track_0/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_1__3_/mem_right_track_0/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_1__3_/mem_right_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_1__3_/mem_right_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_1__3_/mem_right_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_1__3_/mem_right_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_1__3_/mem_right_track_8/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_1__3_/mem_right_track_8/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_1__3_/mem_right_track_8/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_1__3_/mem_right_track_8/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_1__3_/mem_right_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_1__3_/mem_right_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_1__3_/mem_right_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_1__3_/mem_right_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_1__3_/mem_right_track_16/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_1__3_/mem_right_track_16/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_1__3_/mem_right_track_16/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_1__3_/mem_right_track_16/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_1__3_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_1__3_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__3_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__3_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__3_/mem_bottom_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__3_/mem_bottom_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__3_/mem_bottom_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__3_/mem_bottom_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_1__3_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_1/DFF_3_/Q -to fpga_top/sb_1__3_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__3_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__3_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__3_/mem_bottom_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__3_/mem_bottom_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_1__3_/mem_bottom_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_9/DFF_2_/Q -to fpga_top/sb_1__3_/mem_bottom_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_1__3_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_9/DFF_3_/Q -to fpga_top/sb_1__3_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__3_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__3_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__3_/mem_bottom_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__3_/mem_bottom_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_1__3_/mem_bottom_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_17/DFF_2_/Q -to fpga_top/sb_1__3_/mem_bottom_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_1__3_/mem_left_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_bottom_track_17/DFF_3_/Q -to fpga_top/sb_1__3_/mem_left_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__3_/mem_left_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__3_/mem_left_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__3_/mem_left_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__3_/mem_left_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__3_/mem_left_track_1/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__3_/mem_left_track_1/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_1__3_/mem_left_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_1__3_/mem_left_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__3_/mem_left_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__3_/mem_left_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__3_/mem_left_track_9/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__3_/mem_left_track_9/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_1__3_/mem_left_track_9/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_1__3_/mem_left_track_9/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_1__3_/mem_left_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_1__3_/mem_left_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__3_/mem_left_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__3_/mem_left_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__3_/mem_left_track_17/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__3_/mem_left_track_17/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_1__3_/mem_left_track_17/DFF_3_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_1__3_/mem_left_track_17/DFF_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__3_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__3_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__3_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__3_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__3_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__3_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__3_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__3_/mem_top_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__3_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_1__4_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__3_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_1__4_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_2__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_1__4_/mem_right_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_2__4_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/Q -to fpga_top/sb_1__4_/mem_right_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_1__4_/mem_right_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_1__4_/mem_right_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_1__4_/mem_right_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_1__4_/mem_right_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_1__4_/mem_right_track_0/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_1__4_/mem_right_track_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_1__4_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_right_track_0/DFF_3_/Q -to fpga_top/sb_1__4_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_1__4_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_1__4_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_1__4_/mem_right_track_8/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_1__4_/mem_right_track_8/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_1__4_/mem_right_track_8/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_right_track_8/DFF_2_/Q -to fpga_top/sb_1__4_/mem_right_track_8/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_1__4_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_right_track_8/DFF_3_/Q -to fpga_top/sb_1__4_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_1__4_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_1__4_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_1__4_/mem_right_track_16/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_1__4_/mem_right_track_16/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_1__4_/mem_right_track_16/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_right_track_16/DFF_2_/Q -to fpga_top/sb_1__4_/mem_right_track_16/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_1__4_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_right_track_16/DFF_3_/Q -to fpga_top/sb_1__4_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_3/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_3/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_5/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_5/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_7/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_7/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_11/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_11/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_11/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_11/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_13/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_13/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_13/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_13/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_15/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_15/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_15/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_15/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_19/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__4_/mem_bottom_track_19/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_19/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_1__4_/mem_bottom_track_19/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_1__4_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_1__4_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__4_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__4_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__4_/mem_left_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__4_/mem_left_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__4_/mem_left_track_1/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__4_/mem_left_track_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_1__4_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_left_track_1/DFF_3_/Q -to fpga_top/sb_1__4_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__4_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__4_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__4_/mem_left_track_9/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__4_/mem_left_track_9/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_1__4_/mem_left_track_9/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_left_track_9/DFF_2_/Q -to fpga_top/sb_1__4_/mem_left_track_9/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_1__4_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_left_track_9/DFF_3_/Q -to fpga_top/sb_1__4_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__4_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__4_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__4_/mem_left_track_17/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__4_/mem_left_track_17/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_1__4_/mem_left_track_17/DFF_3_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_left_track_17/DFF_2_/Q -to fpga_top/sb_1__4_/mem_left_track_17/DFF_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__4_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__4_/mem_left_track_17/DFF_3_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__4_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__4_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_1__4_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__4_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cby_1__4_/mem_left_ipin_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/cby_1__4_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_1__4_/mem_left_ipin_0/DFF_1_/D 5 set_min_delay -from fpga_top/cby_1__4_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_1__4_/mem_left_ipin_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/cby_1__4_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_1__4_/mem_left_ipin_0/DFF_2_/D 5 diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/disable_configurable_memory_outputs.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/disable_configurable_memory_outputs.sdc index 3c755b028..e644f9251 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/disable_configurable_memory_outputs.sdc +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/disable_configurable_memory_outputs.sdc @@ -6,48 +6,44 @@ # Organization: University of Utah ############################################# -set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q -set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN -set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q -set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN +set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q +set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN -set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q -set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN +set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q +set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN +set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q +set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q @@ -60,12 +56,16 @@ set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logica set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q @@ -74,6 +74,14 @@ set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q @@ -84,6 +92,8 @@ set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN +set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q +set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q @@ -100,6 +110,14 @@ set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/mem_fle_ set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/mem_fle_*_in_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q @@ -108,32 +126,16 @@ set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN -set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q -set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q @@ -146,5 +148,3 @@ set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_bitstream.bit b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_bitstream.bit index fc17891b4..1a79dc354 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_bitstream.bit +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_bitstream.bit @@ -221,6 +221,8 @@ 0 0 0 +1 +1 0 0 0 @@ -621,6 +623,9 @@ 0 0 0 +1 +1 +1 0 0 0 @@ -804,7 +809,6 @@ 0 0 0 -1 0 0 0 @@ -828,8 +832,6 @@ 0 0 0 -1 -1 0 0 0 @@ -840,9 +842,7 @@ 0 0 0 -1 0 -1 0 0 0 @@ -864,7 +864,6 @@ 0 0 0 -1 0 0 0 @@ -877,9 +876,6 @@ 0 0 0 -1 -1 -1 0 0 0 @@ -898,6 +894,8 @@ 0 0 0 +1 +1 0 0 0 @@ -910,6 +908,7 @@ 0 0 0 +1 0 0 0 @@ -922,13 +921,15 @@ 0 0 0 +1 +1 +1 0 0 0 0 0 0 -1 0 0 0 @@ -939,13 +940,9 @@ 0 0 0 -1 0 -1 0 -1 0 -1 0 0 0 @@ -975,6 +972,7 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- + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fpga_top.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fpga_top.v index 560ad7620..8d1c9cd5f 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fpga_top.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fpga_top.v @@ -807,7 +807,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .bottom_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__4__0_top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_), .bottom_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__4__0_top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_), .bottom_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__4__0_top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_), - .ccff_head(cbx_1__4__0_ccff_tail), + .ccff_head(grid_io_top_1_ccff_tail), .bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_), .bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_), .bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_), @@ -829,7 +829,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .bottom_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__4__1_top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_), .bottom_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__4__1_top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_), .bottom_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__4__1_top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_), - .ccff_head(cbx_1__4__1_ccff_tail), + .ccff_head(grid_io_top_2_ccff_tail), .bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_1_bottom_width_0_height_0_subtile_0__pin_inpad_0_), .bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_1_bottom_width_0_height_0_subtile_1__pin_inpad_0_), .bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_1_bottom_width_0_height_0_subtile_2__pin_inpad_0_), @@ -851,7 +851,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .bottom_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__4__2_top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_), .bottom_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__4__2_top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_), .bottom_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__4__2_top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_), - .ccff_head(cbx_1__4__2_ccff_tail), + .ccff_head(grid_io_top_3_ccff_tail), .bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_2_bottom_width_0_height_0_subtile_0__pin_inpad_0_), .bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_2_bottom_width_0_height_0_subtile_1__pin_inpad_0_), .bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_2_bottom_width_0_height_0_subtile_2__pin_inpad_0_), @@ -873,7 +873,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .bottom_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__4__3_top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_), .bottom_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__4__3_top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_), .bottom_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__4__3_top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_), - .ccff_head(cbx_1__4__3_ccff_tail), + .ccff_head(grid_io_right_0_ccff_tail), .bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_3_bottom_width_0_height_0_subtile_0__pin_inpad_0_), .bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_3_bottom_width_0_height_0_subtile_1__pin_inpad_0_), .bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_3_bottom_width_0_height_0_subtile_2__pin_inpad_0_), @@ -983,7 +983,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .top_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_), .top_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_), .top_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_), - .ccff_head(grid_io_bottom_1_ccff_tail), + .ccff_head(cbx_1__0__3_ccff_tail), .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_), .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_), .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_), @@ -1005,7 +1005,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .top_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_), .top_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_), .top_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_), - .ccff_head(grid_io_bottom_2_ccff_tail), + .ccff_head(cbx_1__0__2_ccff_tail), .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_0__pin_inpad_0_), .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_1__pin_inpad_0_), .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_2__pin_inpad_0_), @@ -1027,7 +1027,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .top_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_), .top_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_), .top_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_), - .ccff_head(grid_io_bottom_3_ccff_tail), + .ccff_head(cbx_1__0__1_ccff_tail), .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_2_top_width_0_height_0_subtile_0__pin_inpad_0_), .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_2_top_width_0_height_0_subtile_1__pin_inpad_0_), .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_2_top_width_0_height_0_subtile_2__pin_inpad_0_), @@ -1049,7 +1049,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .top_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_), .top_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_), .top_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_), - .ccff_head(ccff_head), + .ccff_head(cbx_1__0__0_ccff_tail), .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_3_top_width_0_height_0_subtile_0__pin_inpad_0_), .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_3_top_width_0_height_0_subtile_1__pin_inpad_0_), .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_3_top_width_0_height_0_subtile_2__pin_inpad_0_), @@ -1538,7 +1538,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_3_top_width_0_height_0_subtile_5__pin_inpad_0_), .right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_3_top_width_0_height_0_subtile_6__pin_inpad_0_), .right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_3_top_width_0_height_0_subtile_7__pin_inpad_0_), - .ccff_head(grid_io_left_1_ccff_tail), + .ccff_head(ccff_head), .chany_top_out(sb_0__0__0_chany_top_out[0:9]), .chanx_right_out(sb_0__0__0_chanx_right_out[0:9]), .ccff_tail(sb_0__0__0_ccff_tail)); @@ -1568,7 +1568,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_5__pin_inpad_0_), .bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_6__pin_inpad_0_), .bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_7__pin_inpad_0_), - .ccff_head(grid_io_left_2_ccff_tail), + .ccff_head(grid_io_left_1_ccff_tail), .chany_top_out(sb_0__1__0_chany_top_out[0:9]), .chanx_right_out(sb_0__1__0_chanx_right_out[0:9]), .chany_bottom_out(sb_0__1__0_chany_bottom_out[0:9]), @@ -1599,7 +1599,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_left_1_right_width_0_height_0_subtile_5__pin_inpad_0_), .bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_left_1_right_width_0_height_0_subtile_6__pin_inpad_0_), .bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_left_1_right_width_0_height_0_subtile_7__pin_inpad_0_), - .ccff_head(grid_io_left_3_ccff_tail), + .ccff_head(grid_io_left_2_ccff_tail), .chany_top_out(sb_0__1__1_chany_top_out[0:9]), .chanx_right_out(sb_0__1__1_chanx_right_out[0:9]), .chany_bottom_out(sb_0__1__1_chany_bottom_out[0:9]), @@ -1630,7 +1630,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_left_2_right_width_0_height_0_subtile_5__pin_inpad_0_), .bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_left_2_right_width_0_height_0_subtile_6__pin_inpad_0_), .bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_left_2_right_width_0_height_0_subtile_7__pin_inpad_0_), - .ccff_head(sb_0__4__0_ccff_tail), + .ccff_head(grid_io_left_3_ccff_tail), .chany_top_out(sb_0__1__2_chany_top_out[0:9]), .chanx_right_out(sb_0__1__2_chanx_right_out[0:9]), .chany_bottom_out(sb_0__1__2_chany_bottom_out[0:9]), @@ -1688,7 +1688,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_3_top_width_0_height_0_subtile_5__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_3_top_width_0_height_0_subtile_6__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_3_top_width_0_height_0_subtile_7__pin_inpad_0_), - .ccff_head(grid_io_left_0_ccff_tail), + .ccff_head(sb_0__0__0_ccff_tail), .chany_top_out(sb_1__0__0_chany_top_out[0:9]), .chanx_right_out(sb_1__0__0_chanx_right_out[0:9]), .chanx_left_out(sb_1__0__0_chanx_left_out[0:9]), @@ -1719,7 +1719,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_2_top_width_0_height_0_subtile_5__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_2_top_width_0_height_0_subtile_6__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_2_top_width_0_height_0_subtile_7__pin_inpad_0_), - .ccff_head(grid_clb_0_ccff_tail), + .ccff_head(grid_io_bottom_3_ccff_tail), .chany_top_out(sb_1__0__1_chany_top_out[0:9]), .chanx_right_out(sb_1__0__1_chanx_right_out[0:9]), .chanx_left_out(sb_1__0__1_chanx_left_out[0:9]), @@ -1750,7 +1750,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_5__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_6__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_7__pin_inpad_0_), - .ccff_head(grid_clb_4_ccff_tail), + .ccff_head(grid_io_bottom_2_ccff_tail), .chany_top_out(sb_1__0__2_chany_top_out[0:9]), .chanx_right_out(sb_1__0__2_chanx_right_out[0:9]), .chanx_left_out(sb_1__0__2_chanx_left_out[0:9]), @@ -1770,7 +1770,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .chanx_left_in(cbx_1__1__0_chanx_right_out[0:9]), .left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_1_bottom_width_0_height_0_subtile_0__pin_O_0_), .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_2_), - .ccff_head(grid_clb_5_ccff_tail), + .ccff_head(grid_io_left_0_ccff_tail), .chany_top_out(sb_1__1__0_chany_top_out[0:9]), .chanx_right_out(sb_1__1__0_chanx_right_out[0:9]), .chany_bottom_out(sb_1__1__0_chany_bottom_out[0:9]), @@ -1791,7 +1791,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .chanx_left_in(cbx_1__1__1_chanx_right_out[0:9]), .left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_2_bottom_width_0_height_0_subtile_0__pin_O_0_), .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_2_), - .ccff_head(grid_clb_1_ccff_tail), + .ccff_head(grid_clb_5_ccff_tail), .chany_top_out(sb_1__1__1_chany_top_out[0:9]), .chanx_right_out(sb_1__1__1_chanx_right_out[0:9]), .chany_bottom_out(sb_1__1__1_chany_bottom_out[0:9]), @@ -1812,7 +1812,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .chanx_left_in(cbx_1__1__2_chanx_right_out[0:9]), .left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_3_bottom_width_0_height_0_subtile_0__pin_O_0_), .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_2_), - .ccff_head(grid_clb_7_ccff_tail), + .ccff_head(grid_clb_1_ccff_tail), .chany_top_out(sb_1__1__2_chany_top_out[0:9]), .chanx_right_out(sb_1__1__2_chanx_right_out[0:9]), .chany_bottom_out(sb_1__1__2_chany_bottom_out[0:9]), @@ -1833,7 +1833,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .chanx_left_in(cbx_1__1__3_chanx_right_out[0:9]), .left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_5_bottom_width_0_height_0_subtile_0__pin_O_0_), .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_2_), - .ccff_head(grid_clb_9_ccff_tail), + .ccff_head(grid_clb_0_ccff_tail), .chany_top_out(sb_1__1__3_chany_top_out[0:9]), .chanx_right_out(sb_1__1__3_chanx_right_out[0:9]), .chany_bottom_out(sb_1__1__3_chany_bottom_out[0:9]), @@ -1854,7 +1854,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .chanx_left_in(cbx_1__1__4_chanx_right_out[0:9]), .left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_6_bottom_width_0_height_0_subtile_0__pin_O_0_), .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_2_), - .ccff_head(grid_clb_2_ccff_tail), + .ccff_head(grid_clb_9_ccff_tail), .chany_top_out(sb_1__1__4_chany_top_out[0:9]), .chanx_right_out(sb_1__1__4_chanx_right_out[0:9]), .chany_bottom_out(sb_1__1__4_chany_bottom_out[0:9]), @@ -1875,7 +1875,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .chanx_left_in(cbx_1__1__5_chanx_right_out[0:9]), .left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_7_bottom_width_0_height_0_subtile_0__pin_O_0_), .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_2_), - .ccff_head(grid_clb_11_ccff_tail), + .ccff_head(grid_clb_2_ccff_tail), .chany_top_out(sb_1__1__5_chany_top_out[0:9]), .chanx_right_out(sb_1__1__5_chanx_right_out[0:9]), .chany_bottom_out(sb_1__1__5_chany_bottom_out[0:9]), @@ -1896,7 +1896,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .chanx_left_in(cbx_1__1__6_chanx_right_out[0:9]), .left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_9_bottom_width_0_height_0_subtile_0__pin_O_0_), .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_2_), - .ccff_head(grid_clb_13_ccff_tail), + .ccff_head(grid_clb_4_ccff_tail), .chany_top_out(sb_1__1__6_chany_top_out[0:9]), .chanx_right_out(sb_1__1__6_chanx_right_out[0:9]), .chany_bottom_out(sb_1__1__6_chany_bottom_out[0:9]), @@ -1917,7 +1917,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .chanx_left_in(cbx_1__1__7_chanx_right_out[0:9]), .left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_10_bottom_width_0_height_0_subtile_0__pin_O_0_), .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_2_), - .ccff_head(grid_clb_6_ccff_tail), + .ccff_head(grid_clb_13_ccff_tail), .chany_top_out(sb_1__1__7_chany_top_out[0:9]), .chanx_right_out(sb_1__1__7_chanx_right_out[0:9]), .chany_bottom_out(sb_1__1__7_chany_bottom_out[0:9]), @@ -1938,7 +1938,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .chanx_left_in(cbx_1__1__8_chanx_right_out[0:9]), .left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_11_bottom_width_0_height_0_subtile_0__pin_O_0_), .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_2_), - .ccff_head(grid_clb_15_ccff_tail), + .ccff_head(grid_clb_6_ccff_tail), .chany_top_out(sb_1__1__8_chany_top_out[0:9]), .chanx_right_out(sb_1__1__8_chanx_right_out[0:9]), .chany_bottom_out(sb_1__1__8_chany_bottom_out[0:9]), @@ -1970,7 +1970,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_6__pin_inpad_0_), .left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_7__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_2_), - .ccff_head(grid_io_top_1_ccff_tail), + .ccff_head(grid_clb_7_ccff_tail), .chanx_right_out(sb_1__4__0_chanx_right_out[0:9]), .chany_bottom_out(sb_1__4__0_chany_bottom_out[0:9]), .chanx_left_out(sb_1__4__0_chanx_left_out[0:9]), @@ -2001,7 +2001,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_top_1_bottom_width_0_height_0_subtile_6__pin_inpad_0_), .left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_top_1_bottom_width_0_height_0_subtile_7__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_2_), - .ccff_head(grid_io_top_2_ccff_tail), + .ccff_head(grid_clb_11_ccff_tail), .chanx_right_out(sb_1__4__1_chanx_right_out[0:9]), .chany_bottom_out(sb_1__4__1_chany_bottom_out[0:9]), .chanx_left_out(sb_1__4__1_chanx_left_out[0:9]), @@ -2032,7 +2032,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_top_2_bottom_width_0_height_0_subtile_6__pin_inpad_0_), .left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_top_2_bottom_width_0_height_0_subtile_7__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_2_), - .ccff_head(grid_io_top_3_ccff_tail), + .ccff_head(grid_clb_15_ccff_tail), .chanx_right_out(sb_1__4__2_chanx_right_out[0:9]), .chany_bottom_out(sb_1__4__2_chany_bottom_out[0:9]), .chanx_left_out(sb_1__4__2_chanx_left_out[0:9]), @@ -2060,7 +2060,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_5__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_6__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_7__pin_inpad_0_), - .ccff_head(grid_clb_8_ccff_tail), + .ccff_head(grid_io_bottom_1_ccff_tail), .chany_top_out(sb_4__0__0_chany_top_out[0:9]), .chanx_left_out(sb_4__0__0_chanx_left_out[0:9]), .ccff_tail(sb_4__0__0_ccff_tail)); @@ -2090,7 +2090,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .chanx_left_in(cbx_1__1__9_chanx_right_out[0:9]), .left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_13_bottom_width_0_height_0_subtile_0__pin_O_0_), .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_2_), - .ccff_head(grid_clb_12_ccff_tail), + .ccff_head(grid_clb_8_ccff_tail), .chany_top_out(sb_4__1__0_chany_top_out[0:9]), .chany_bottom_out(sb_4__1__0_chany_bottom_out[0:9]), .chanx_left_out(sb_4__1__0_chanx_left_out[0:9]), @@ -2121,7 +2121,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .chanx_left_in(cbx_1__1__10_chanx_right_out[0:9]), .left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_14_bottom_width_0_height_0_subtile_0__pin_O_0_), .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_2_), - .ccff_head(grid_clb_10_ccff_tail), + .ccff_head(grid_clb_12_ccff_tail), .chany_top_out(sb_4__1__1_chany_top_out[0:9]), .chany_bottom_out(sb_4__1__1_chany_bottom_out[0:9]), .chanx_left_out(sb_4__1__1_chanx_left_out[0:9]), @@ -2152,7 +2152,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .chanx_left_in(cbx_1__1__11_chanx_right_out[0:9]), .left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_15_bottom_width_0_height_0_subtile_0__pin_O_0_), .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_2_), - .ccff_head(grid_clb_14_ccff_tail), + .ccff_head(grid_clb_10_ccff_tail), .chany_top_out(sb_4__1__2_chany_top_out[0:9]), .chany_bottom_out(sb_4__1__2_chany_bottom_out[0:9]), .chanx_left_out(sb_4__1__2_chanx_left_out[0:9]), @@ -2180,7 +2180,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_top_3_bottom_width_0_height_0_subtile_6__pin_inpad_0_), .left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_top_3_bottom_width_0_height_0_subtile_7__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_2_), - .ccff_head(grid_io_right_0_ccff_tail), + .ccff_head(grid_clb_14_ccff_tail), .chany_bottom_out(sb_4__4__0_chany_bottom_out[0:9]), .chanx_left_out(sb_4__4__0_chanx_left_out[0:9]), .ccff_tail(sb_4__4__0_ccff_tail)); @@ -2529,7 +2529,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_0__0__0_chany_top_out[0:9]), .chany_top_in(sb_0__1__0_chany_bottom_out[0:9]), - .ccff_head(sb_0__0__0_ccff_tail), + .ccff_head(sb_0__1__0_ccff_tail), .chany_bottom_out(cby_0__1__0_chany_bottom_out[0:9]), .chany_top_out(cby_0__1__0_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_0__1__0_right_grid_left_width_0_height_0_subtile_0__pin_I_3_), @@ -2548,7 +2548,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_0__1__0_chany_top_out[0:9]), .chany_top_in(sb_0__1__1_chany_bottom_out[0:9]), - .ccff_head(sb_0__1__0_ccff_tail), + .ccff_head(sb_0__1__1_ccff_tail), .chany_bottom_out(cby_0__1__1_chany_bottom_out[0:9]), .chany_top_out(cby_0__1__1_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_0__1__1_right_grid_left_width_0_height_0_subtile_0__pin_I_3_), @@ -2567,7 +2567,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_0__1__1_chany_top_out[0:9]), .chany_top_in(sb_0__1__2_chany_bottom_out[0:9]), - .ccff_head(sb_0__1__1_ccff_tail), + .ccff_head(sb_0__1__2_ccff_tail), .chany_bottom_out(cby_0__1__2_chany_bottom_out[0:9]), .chany_top_out(cby_0__1__2_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_0__1__2_right_grid_left_width_0_height_0_subtile_0__pin_I_3_), @@ -2586,7 +2586,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_0__1__2_chany_top_out[0:9]), .chany_top_in(sb_0__4__0_chany_bottom_out[0:9]), - .ccff_head(sb_0__1__2_ccff_tail), + .ccff_head(sb_0__4__0_ccff_tail), .chany_bottom_out(cby_0__1__3_chany_bottom_out[0:9]), .chany_top_out(cby_0__1__3_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_0__1__3_right_grid_left_width_0_height_0_subtile_0__pin_I_3_), @@ -2605,7 +2605,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_1__0__0_chany_top_out[0:9]), .chany_top_in(sb_1__1__0_chany_bottom_out[0:9]), - .ccff_head(cbx_1__0__0_ccff_tail), + .ccff_head(cbx_1__1__0_ccff_tail), .chany_bottom_out(cby_1__1__0_chany_bottom_out[0:9]), .chany_top_out(cby_1__1__0_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_0__pin_I_3_), @@ -2619,7 +2619,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_1__1__0_chany_top_out[0:9]), .chany_top_in(sb_1__1__1_chany_bottom_out[0:9]), - .ccff_head(cbx_1__1__0_ccff_tail), + .ccff_head(cbx_1__1__1_ccff_tail), .chany_bottom_out(cby_1__1__1_chany_bottom_out[0:9]), .chany_top_out(cby_1__1__1_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_1__1__1_right_grid_left_width_0_height_0_subtile_0__pin_I_3_), @@ -2633,7 +2633,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_1__1__1_chany_top_out[0:9]), .chany_top_in(sb_1__1__2_chany_bottom_out[0:9]), - .ccff_head(cbx_1__1__1_ccff_tail), + .ccff_head(cbx_1__1__2_ccff_tail), .chany_bottom_out(cby_1__1__2_chany_bottom_out[0:9]), .chany_top_out(cby_1__1__2_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_1__1__2_right_grid_left_width_0_height_0_subtile_0__pin_I_3_), @@ -2647,7 +2647,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_1__1__2_chany_top_out[0:9]), .chany_top_in(sb_1__4__0_chany_bottom_out[0:9]), - .ccff_head(cbx_1__1__2_ccff_tail), + .ccff_head(cbx_1__4__0_ccff_tail), .chany_bottom_out(cby_1__1__3_chany_bottom_out[0:9]), .chany_top_out(cby_1__1__3_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_1__1__3_right_grid_left_width_0_height_0_subtile_0__pin_I_3_), @@ -2661,7 +2661,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_1__0__1_chany_top_out[0:9]), .chany_top_in(sb_1__1__3_chany_bottom_out[0:9]), - .ccff_head(cbx_1__0__1_ccff_tail), + .ccff_head(cbx_1__1__3_ccff_tail), .chany_bottom_out(cby_1__1__4_chany_bottom_out[0:9]), .chany_top_out(cby_1__1__4_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_1__1__4_right_grid_left_width_0_height_0_subtile_0__pin_I_3_), @@ -2675,7 +2675,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_1__1__3_chany_top_out[0:9]), .chany_top_in(sb_1__1__4_chany_bottom_out[0:9]), - .ccff_head(cbx_1__1__3_ccff_tail), + .ccff_head(cbx_1__1__4_ccff_tail), .chany_bottom_out(cby_1__1__5_chany_bottom_out[0:9]), .chany_top_out(cby_1__1__5_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_1__1__5_right_grid_left_width_0_height_0_subtile_0__pin_I_3_), @@ -2689,7 +2689,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_1__1__4_chany_top_out[0:9]), .chany_top_in(sb_1__1__5_chany_bottom_out[0:9]), - .ccff_head(cbx_1__1__4_ccff_tail), + .ccff_head(cbx_1__1__5_ccff_tail), .chany_bottom_out(cby_1__1__6_chany_bottom_out[0:9]), .chany_top_out(cby_1__1__6_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_1__1__6_right_grid_left_width_0_height_0_subtile_0__pin_I_3_), @@ -2703,7 +2703,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_1__1__5_chany_top_out[0:9]), .chany_top_in(sb_1__4__1_chany_bottom_out[0:9]), - .ccff_head(cbx_1__1__5_ccff_tail), + .ccff_head(cbx_1__4__1_ccff_tail), .chany_bottom_out(cby_1__1__7_chany_bottom_out[0:9]), .chany_top_out(cby_1__1__7_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_1__1__7_right_grid_left_width_0_height_0_subtile_0__pin_I_3_), @@ -2717,7 +2717,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_1__0__2_chany_top_out[0:9]), .chany_top_in(sb_1__1__6_chany_bottom_out[0:9]), - .ccff_head(cbx_1__0__2_ccff_tail), + .ccff_head(cbx_1__1__6_ccff_tail), .chany_bottom_out(cby_1__1__8_chany_bottom_out[0:9]), .chany_top_out(cby_1__1__8_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_1__1__8_right_grid_left_width_0_height_0_subtile_0__pin_I_3_), @@ -2731,7 +2731,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_1__1__6_chany_top_out[0:9]), .chany_top_in(sb_1__1__7_chany_bottom_out[0:9]), - .ccff_head(cbx_1__1__6_ccff_tail), + .ccff_head(cbx_1__1__7_ccff_tail), .chany_bottom_out(cby_1__1__9_chany_bottom_out[0:9]), .chany_top_out(cby_1__1__9_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_1__1__9_right_grid_left_width_0_height_0_subtile_0__pin_I_3_), @@ -2745,7 +2745,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_1__1__7_chany_top_out[0:9]), .chany_top_in(sb_1__1__8_chany_bottom_out[0:9]), - .ccff_head(cbx_1__1__7_ccff_tail), + .ccff_head(cbx_1__1__8_ccff_tail), .chany_bottom_out(cby_1__1__10_chany_bottom_out[0:9]), .chany_top_out(cby_1__1__10_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_1__1__10_right_grid_left_width_0_height_0_subtile_0__pin_I_3_), @@ -2759,7 +2759,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_1__1__8_chany_top_out[0:9]), .chany_top_in(sb_1__4__2_chany_bottom_out[0:9]), - .ccff_head(cbx_1__1__8_ccff_tail), + .ccff_head(cbx_1__4__2_ccff_tail), .chany_bottom_out(cby_1__1__11_chany_bottom_out[0:9]), .chany_top_out(cby_1__1__11_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_1__1__11_right_grid_left_width_0_height_0_subtile_0__pin_I_3_), @@ -2773,7 +2773,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_4__0__0_chany_top_out[0:9]), .chany_top_in(sb_4__1__0_chany_bottom_out[0:9]), - .ccff_head(cbx_1__0__3_ccff_tail), + .ccff_head(cbx_1__1__9_ccff_tail), .chany_bottom_out(cby_4__1__0_chany_bottom_out[0:9]), .chany_top_out(cby_4__1__0_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_4__1__0_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), @@ -2793,7 +2793,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_4__1__0_chany_top_out[0:9]), .chany_top_in(sb_4__1__1_chany_bottom_out[0:9]), - .ccff_head(cbx_1__1__9_ccff_tail), + .ccff_head(cbx_1__1__10_ccff_tail), .chany_bottom_out(cby_4__1__1_chany_bottom_out[0:9]), .chany_top_out(cby_4__1__1_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_4__1__1_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), @@ -2813,7 +2813,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_4__1__1_chany_top_out[0:9]), .chany_top_in(sb_4__1__2_chany_bottom_out[0:9]), - .ccff_head(cbx_1__1__10_ccff_tail), + .ccff_head(cbx_1__1__11_ccff_tail), .chany_bottom_out(cby_4__1__2_chany_bottom_out[0:9]), .chany_top_out(cby_4__1__2_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_4__1__2_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), @@ -2833,7 +2833,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_4__1__2_chany_top_out[0:9]), .chany_top_in(sb_4__4__0_chany_bottom_out[0:9]), - .ccff_head(cbx_1__1__11_ccff_tail), + .ccff_head(cbx_1__4__3_ccff_tail), .chany_bottom_out(cby_4__1__3_chany_bottom_out[0:9]), .chany_top_out(cby_4__1__3_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_4__1__3_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_0__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_0__1_.xml index a9421575e..07928fe3f 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_0__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_0__1_.xml @@ -1,60 +1,60 @@ - - - - + + + + - - + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_0__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_0__2_.xml index 2b935694f..ce309ecbf 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_0__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_0__2_.xml @@ -1,60 +1,60 @@ - - - - + + + + - - + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_0__3_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_0__3_.xml index 5dc83d65a..6131cf308 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_0__3_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_0__3_.xml @@ -1,60 +1,60 @@ - - - - + + + + - - + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_0__4_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_0__4_.xml index 82f30d5b4..9691260da 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_0__4_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_0__4_.xml @@ -1,60 +1,60 @@ - - - - + + + + - - + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_1__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_1__1_.xml index 685366747..e3e56cf32 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_1__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_1__1_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_1__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_1__2_.xml index af800832a..4050ce7e4 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_1__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_1__2_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_1__3_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_1__3_.xml index ee71fb230..cf7a01345 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_1__3_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_1__3_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_1__4_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_1__4_.xml index 00d00a5fd..4faa064fa 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_1__4_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_1__4_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_2__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_2__1_.xml index c93bbf890..18b761b42 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_2__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_2__1_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_2__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_2__2_.xml index de31ff3cc..6b602276f 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_2__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_2__2_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_2__3_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_2__3_.xml index e10d1106b..cfdad6f99 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_2__3_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_2__3_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_2__4_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_2__4_.xml index cd54a99c7..1e6dabda1 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_2__4_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_2__4_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_3__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_3__1_.xml index e3f7a395c..8abb31ff2 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_3__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_3__1_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_3__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_3__2_.xml index 4f8024349..709dbbb2e 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_3__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_3__2_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_3__3_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_3__3_.xml index c19441be6..c5573a4b5 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_3__3_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_3__3_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_3__4_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_3__4_.xml index 102048421..e2de46537 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_3__4_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_3__4_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_4__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_4__1_.xml index f3007ec85..f86ea9caa 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_4__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_4__1_.xml @@ -1,64 +1,64 @@ - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_4__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_4__2_.xml index 9f589a7be..0d5b16c52 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_4__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_4__2_.xml @@ -1,64 +1,64 @@ - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_4__3_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_4__3_.xml index f9e0b6a9c..a3d189670 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_4__3_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_4__3_.xml @@ -1,64 +1,64 @@ - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_4__4_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_4__4_.xml index dea12ded1..3646dcf7a 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_4__4_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_4__4_.xml @@ -1,64 +1,64 @@ - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__1_.xml index 793b5628b..e2b960d51 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__1_.xml @@ -1,60 +1,60 @@ - - - - + + + + - - + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__2_.xml index 4533c39bc..f63dde147 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__2_.xml @@ -1,60 +1,60 @@ - - - - + + + + - - + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__3_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__3_.xml index 176b9f5f6..dff12bf3c 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__3_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__3_.xml @@ -1,60 +1,60 @@ - - - - + + + + - - + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__4_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__4_.xml index bee8e919c..1eb7f09a9 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__4_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__4_.xml @@ -1,60 +1,60 @@ - - - - + + + + - - + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__1_.xml index 11fbfd51f..682749130 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__1_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__2_.xml index 0026bd554..7a5e114c5 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__2_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__3_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__3_.xml index 50006d9d2..e514f592d 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__3_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__3_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__4_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__4_.xml index 4063f260e..ec581676c 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__4_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__4_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__1_.xml index 488bff99b..d65b5ca5c 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__1_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__2_.xml index ea86b5480..b69d7bd68 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__2_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__3_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__3_.xml index c3ac067bd..15ba71944 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__3_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__3_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__4_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__4_.xml index 387479a35..5a77185a4 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__4_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__4_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_3__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_3__1_.xml index a3b68c168..47a94e7cd 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_3__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_3__1_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_3__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_3__2_.xml index 83e9f50db..414f19d95 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_3__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_3__2_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_3__3_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_3__3_.xml index ccaa1b7fb..b4b8d746e 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_3__3_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_3__3_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_3__4_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_3__4_.xml index df8bca3f2..146fe9653 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_3__4_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_3__4_.xml @@ -1,26 +1,26 @@ - - - - + + + + - - + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_4__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_4__1_.xml index 20f9f7b50..763e7a89a 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_4__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_4__1_.xml @@ -1,64 +1,64 @@ - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_4__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_4__2_.xml index d533a55a7..e98acc918 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_4__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_4__2_.xml @@ -1,64 +1,64 @@ - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_4__3_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_4__3_.xml index c9874c86b..655ea8946 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_4__3_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_4__3_.xml @@ -1,64 +1,64 @@ - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_4__4_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_4__4_.xml index 52722e4bb..5847f5e49 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_4__4_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_4__4_.xml @@ -1,64 +1,64 @@ - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - + + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc index 8237fc2f9..2ccec1ac6 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc @@ -57,16 +57,24 @@ set_disable_timing gfpga_pad_GPIO_PAD[31] set_disable_timing set[0] set_disable_timing reset[0] set_disable_timing prog_clk[0] -set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q -set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN -set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q -set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q @@ -77,6 +85,10 @@ set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN +set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q +set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN +set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q +set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q @@ -91,30 +103,18 @@ set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/QN set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/ccff_timing.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/ccff_timing.sdc index df2b04e23..5a3b9e3df 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/ccff_timing.sdc +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/ccff_timing.sdc @@ -11,346 +11,6 @@ ############################################# set_units -time ns -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/sb_0__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFF_1_/D 5 set_min_delay -from fpga_top/sb_0__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/sb_0__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFF_2_/D 5 @@ -465,84 +125,8 @@ set_max_delay -from fpga_top/sb_0__0_/mem_right_track_22/DFF_1_/Q -to fpga_top/s set_min_delay -from fpga_top/sb_0__0_/mem_right_track_22/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_24/DFF_0_/D 2.5 set_max_delay -from fpga_top/sb_0__0_/mem_right_track_24/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_24/DFF_1_/D 5 set_min_delay -from fpga_top/sb_0__0_/mem_right_track_24/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_24/DFF_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__0_/mem_right_track_24/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/sb_0__0_/mem_right_track_24/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_24/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_24/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_1_/D 5 set_min_delay -from fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/sb_1__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_2_/D 5 @@ -725,8 +309,424 @@ set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_0_/Q -to fpga_top/cbx_ set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_1_/D 2.5 set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/D 5 set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/D 5 -set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/D 2.5 set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_1_/D 5 set_min_delay -from fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_1_/D 2.5 set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_2_/D 5 diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/disable_configurable_memory_outputs.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/disable_configurable_memory_outputs.sdc index 022a20fcf..8cd7edd67 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/disable_configurable_memory_outputs.sdc +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/disable_configurable_memory_outputs.sdc @@ -6,16 +6,24 @@ # Organization: University of Utah ############################################# -set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q -set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN -set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q -set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q @@ -26,6 +34,10 @@ set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN +set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q +set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN +set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q +set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q @@ -40,30 +52,18 @@ set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/Q set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/QN set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_bitstream.bit b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_bitstream.bit index 3387708eb..7c8512c57 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_bitstream.bit +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_bitstream.bit @@ -197,18 +197,7 @@ 0 0 0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 +1 0 0 0 @@ -243,8 +232,19 @@ 0 0 0 -1 -1 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 0 0 0 @@ -267,67 +267,6 @@ 1 1 1 -1 -1 -1 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 0 0 0 @@ -423,34 +362,61 @@ 1 0 1 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 0 0 0 @@ -485,19 +451,8 @@ 0 0 0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 +1 +1 0 0 0 @@ -515,16 +470,61 @@ 1 1 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_bitstream.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_bitstream.xml index 4edf9cf2b..c42176d6b 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_bitstream.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_bitstream.xml @@ -344,721 +344,721 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fpga_top.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fpga_top.v index c8c3d7300..e0098e212 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fpga_top.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fpga_top.v @@ -162,7 +162,7 @@ wire [0:12] sb_1__1__0_chany_bottom_out; .bottom_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_), .bottom_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_), .bottom_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_), - .ccff_head(cbx_1__1__0_ccff_tail), + .ccff_head(grid_io_right_0_ccff_tail), .bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_), .bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_), .bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_), @@ -206,7 +206,7 @@ wire [0:12] sb_1__1__0_chany_bottom_out; .top_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_), .top_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_), .top_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_), - .ccff_head(ccff_head), + .ccff_head(cbx_1__0__0_ccff_tail), .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_), .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_), .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_), @@ -284,7 +284,7 @@ wire [0:12] sb_1__1__0_chany_bottom_out; .right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_5__pin_inpad_0_), .right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_6__pin_inpad_0_), .right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_7__pin_inpad_0_), - .ccff_head(sb_0__1__0_ccff_tail), + .ccff_head(ccff_head), .chany_top_out(sb_0__0__0_chany_top_out[0:12]), .chanx_right_out(sb_0__0__0_chanx_right_out[0:12]), .ccff_tail(sb_0__0__0_ccff_tail)); @@ -338,7 +338,7 @@ wire [0:12] sb_1__1__0_chany_bottom_out; .left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_5__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_6__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_7__pin_inpad_0_), - .ccff_head(grid_io_left_0_ccff_tail), + .ccff_head(sb_0__0__0_ccff_tail), .chany_top_out(sb_1__0__0_chany_top_out[0:12]), .chanx_left_out(sb_1__0__0_chanx_left_out[0:12]), .ccff_tail(sb_1__0__0_ccff_tail)); @@ -365,7 +365,7 @@ wire [0:12] sb_1__1__0_chany_bottom_out; .left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_6__pin_inpad_0_), .left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_7__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_2_), - .ccff_head(grid_io_right_0_ccff_tail), + .ccff_head(grid_io_left_0_ccff_tail), .chany_bottom_out(sb_1__1__0_chany_bottom_out[0:12]), .chanx_left_out(sb_1__1__0_chanx_left_out[0:12]), .ccff_tail(sb_1__1__0_ccff_tail)); @@ -414,7 +414,7 @@ wire [0:12] sb_1__1__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_0__0__0_chany_top_out[0:12]), .chany_top_in(sb_0__1__0_chany_bottom_out[0:12]), - .ccff_head(sb_0__0__0_ccff_tail), + .ccff_head(sb_0__1__0_ccff_tail), .chany_bottom_out(cby_0__1__0_chany_bottom_out[0:12]), .chany_top_out(cby_0__1__0_chany_top_out[0:12]), .right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_0__1__0_right_grid_left_width_0_height_0_subtile_0__pin_I_3_), @@ -433,7 +433,7 @@ wire [0:12] sb_1__1__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_1__0__0_chany_top_out[0:12]), .chany_top_in(sb_1__1__0_chany_bottom_out[0:12]), - .ccff_head(cbx_1__0__0_ccff_tail), + .ccff_head(cbx_1__1__0_ccff_tail), .chany_bottom_out(cby_1__1__0_chany_bottom_out[0:12]), .chany_top_out(cby_1__1__0_chany_top_out[0:12]), .right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cby_0__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cby_0__1_.xml index 99aadddf5..1943afce4 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cby_0__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cby_0__1_.xml @@ -1,82 +1,82 @@ - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cby_1__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cby_1__1_.xml index eefaf5cd9..d4af896d6 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cby_1__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cby_1__1_.xml @@ -1,90 +1,90 @@ - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__1_.xml index 5ecb11950..0e17019b1 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__1_.xml @@ -1,82 +1,82 @@ - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__1_.xml index edec22d72..010e9b689 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__1_.xml @@ -1,90 +1,90 @@ - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc index a45d6aa34..e96165350 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc @@ -90,58 +90,6 @@ set_disable_timing set[0] set_disable_timing reset[0] set_disable_timing pReset[0] set_disable_timing prog_clk[0] -set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q -set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN -set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q -set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN -set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/Q -set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/QN -set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q -set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN -set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/Q -set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/QN -set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFFR_*_/Q -set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFFR_*_/QN -set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q -set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q @@ -168,6 +116,62 @@ set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/QN set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFFR_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFFR_*_/QN +set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q +set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN +set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q +set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN +set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q +set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN +set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/Q +set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/QN +set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFFR_*_/Q +set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFFR_*_/QN +set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q +set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN +set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/Q +set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/Q set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFFR_*_/Q @@ -186,6 +190,10 @@ set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q @@ -194,24 +202,14 @@ set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/Q set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFFR_*_/Q set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q @@ -220,6 +218,8 @@ set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/ccff_timing.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/ccff_timing.sdc index a07071979..ca7724279 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/ccff_timing.sdc +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/ccff_timing.sdc @@ -11,822 +11,6 @@ ############################################# set_units -time ns -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_3/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_3/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_3/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_3/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_3/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_3/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_3/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_5/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_3/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_5/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_5/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_5/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_5/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_5/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_5/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_7/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_5/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_7/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_7/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_7/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_7/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_7/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_7/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_7/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_11/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_11/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_11/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_11/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_11/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_11/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_11/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_13/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_11/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_13/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_13/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_13/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_13/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_13/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_13/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_15/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_13/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_15/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_15/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_15/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_15/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_15/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_15/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_15/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_19/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_19/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_19/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_19/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_19/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_19/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_19/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_19/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_3/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_3/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_3/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_3/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_3/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_3/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_3/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_5/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_3/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_5/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_5/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_5/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_5/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_5/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_5/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_7/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_5/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_7/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_7/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_7/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_7/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_7/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_7/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_7/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_11/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_11/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_11/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_11/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_11/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_11/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_11/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_13/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_11/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_13/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_13/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_13/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_13/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_13/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_13/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_15/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_13/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_15/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_15/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_15/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_15/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_15/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__2_/mem_left_track_15/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__2_/mem_left_track_15/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_5_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_5_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_6_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_6_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_7_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_7_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_6_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_6_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_7_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_7_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_bottom_track_5/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_bottom_track_5/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_5/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_5/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_5/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_5/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_5/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_7/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_5/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_7/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_7/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_7/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_7/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_7/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_7/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_7/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_11/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_11/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_11/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_11/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_11/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_11/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_11/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_13/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_11/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_13/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_13/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_13/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_13/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_13/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_13/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_13/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_6_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_6_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_7_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_7_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_6_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_6_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_7_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_7_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_5_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_5_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_0/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_0/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_0/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_0/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_0/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_0/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_2/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_0/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_2/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_2/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_2/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_2/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_2/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_2/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_4/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_2/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_4/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_4/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_4/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_4/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_4/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_4/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_6/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_4/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_6/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_6/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_6/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_6/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_6/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_6/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_8/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_6/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_8/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_8/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_8/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_8/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_8/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_8/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_10/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_8/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_10/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_10/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_10/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_10/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_10/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_10/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_12/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_10/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_12/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_12/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_12/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_12/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_12/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_12/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_14/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_12/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_14/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_14/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_14/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_14/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_14/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_right_track_14/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_right_track_14/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_3/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_3/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_3/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_3/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_3/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_3/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_3/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_5/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_3/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_5/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_5/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_5/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_5/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_5/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_5/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_7/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_5/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_7/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_7/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_7/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_7/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_7/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_7/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_7/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_11/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_11/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_11/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_11/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_11/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_11/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_11/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_13/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_11/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_13/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_13/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_13/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_13/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_13/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_13/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_15/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_13/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_15/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_15/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_15/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_15/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_15/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_15/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_15/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_6_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_6_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_7_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_7_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_6_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_6_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_7_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_7_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_6_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_6_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_7_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_7_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_1_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_2_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_3_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_4_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_5_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_1_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_2_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_3_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_4_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_5_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_0_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_1_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_2_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_3_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_4_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_5_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_0_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_1_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_2_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_3_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_4_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_5_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_0_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_1_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_2_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_3_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_4_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_5_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_0_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_1_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_2_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_3_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_4_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_5_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_0_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_1_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_2_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_3_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_4_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_5_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_0_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_1_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_2_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_3_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_4_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_5_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_0_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_1_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_2_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_3_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_4_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_5_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_5_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_5_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFFR_0_/D 2.5 set_max_delay -from fpga_top/sb_0__0_/mem_top_track_0/DFFR_0_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFFR_1_/D 5 set_min_delay -from fpga_top/sb_0__0_/mem_top_track_0/DFFR_0_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFFR_1_/D 2.5 set_max_delay -from fpga_top/sb_0__0_/mem_top_track_0/DFFR_1_/Q -to fpga_top/sb_0__0_/mem_top_track_2/DFFR_0_/D 5 @@ -897,132 +81,8 @@ set_max_delay -from fpga_top/sb_0__0_/mem_right_track_16/DFFR_1_/Q -to fpga_top/ set_min_delay -from fpga_top/sb_0__0_/mem_right_track_16/DFFR_1_/Q -to fpga_top/sb_0__0_/mem_right_track_18/DFFR_0_/D 2.5 set_max_delay -from fpga_top/sb_0__0_/mem_right_track_18/DFFR_0_/Q -to fpga_top/sb_0__0_/mem_right_track_18/DFFR_1_/D 5 set_min_delay -from fpga_top/sb_0__0_/mem_right_track_18/DFFR_0_/Q -to fpga_top/sb_0__0_/mem_right_track_18/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_0__0_/mem_right_track_18/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_0__0_/mem_right_track_18/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_3_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_4_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_5_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_3_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_4_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_5_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_3_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_4_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_5_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_3_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_4_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_5_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_3_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_4_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_5_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_3_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_4_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_5_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_3_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_4_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_5_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_3_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_4_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_5_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_1_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_2_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_3_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_4_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_5_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_5_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_5_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_18/DFFR_1_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_18/DFFR_1_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFFR_0_/D 2.5 set_max_delay -from fpga_top/sb_1__0_/mem_top_track_0/DFFR_0_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFFR_1_/D 5 set_min_delay -from fpga_top/sb_1__0_/mem_top_track_0/DFFR_0_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFFR_1_/D 2.5 set_max_delay -from fpga_top/sb_1__0_/mem_top_track_0/DFFR_1_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFFR_2_/D 5 @@ -1285,8 +345,968 @@ set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFFR_3_/Q -to fpga_top/cbx set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFFR_3_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_7/DFFR_4_/D 2.5 set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFFR_4_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_7/DFFR_5_/D 5 set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFFR_4_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_7/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFFR_5_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFFR_5_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFFR_5_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFFR_5_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_0/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_0/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_0/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_0/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_0/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_2/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_0/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_2/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_2/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_2/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_2/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_2/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_2/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_4/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_2/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_4/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_4/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_4/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_4/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_4/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_4/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_6/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_4/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_6/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_6/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_6/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_6/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_6/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_6/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_8/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_6/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_8/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_8/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_8/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_8/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_8/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_8/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_10/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_8/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_10/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_10/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_10/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_10/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_10/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_10/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_12/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_10/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_12/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_12/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_12/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_12/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_12/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_12/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_14/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_12/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_14/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_14/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_14/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_14/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_14/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_14/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_16/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_14/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_16/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_16/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_16/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_16/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_16/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_16/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_18/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_16/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_18/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_18/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_18/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_18/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_18/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_top_track_18/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_top_track_18/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_3/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_3/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_3/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_3/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_3/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_3/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_3/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_5/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_3/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_5/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_5/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_5/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_5/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_5/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_5/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_7/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_5/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_7/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_7/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_7/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_7/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_7/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_7/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_7/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_11/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_11/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_11/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_11/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_11/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_11/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_11/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_13/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_11/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_13/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_13/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_13/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_13/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_13/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_13/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_15/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_13/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_15/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_15/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_15/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_15/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_15/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_15/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_15/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_19/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_19/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_19/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_19/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_19/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_19/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__0_/mem_left_track_19/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__0_/mem_left_track_19/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_3/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_3/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_3/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_3/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_3/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_3/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_3/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_4/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_3/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_4/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_4/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_4/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_4/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_4/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_4/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_5/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_4/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_5/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_5/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_5/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_5/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_5/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_5/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_5/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_5_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_5_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_2__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_3__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_3__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_2__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__3_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_0/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_0/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_0/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_0/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_0/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_2/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_0/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_2/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_2/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_2/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_2/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_2/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_2/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_4/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_2/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_4/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_4/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_4/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_4/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_4/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_4/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_6/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_4/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_6/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_6/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_6/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_6/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_6/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_6/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_8/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_6/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_8/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_8/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_8/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_8/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_8/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_8/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_10/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_8/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_10/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_10/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_10/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_10/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_10/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_10/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_12/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_10/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_12/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_12/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_12/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_12/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_12/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_12/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_14/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_12/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_right_track_14/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_14/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_14/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_14/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_right_track_14/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_right_track_14/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_right_track_14/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_1/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_3/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_3/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_3/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_3/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_3/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_3/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_3/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_5/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_3/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_5/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_5/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_5/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_5/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_5/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_5/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_7/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_5/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_7/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_7/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_7/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_7/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_7/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_7/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_7/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_9/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_11/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_11/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_11/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_11/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_11/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_11/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_11/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_13/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_11/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_13/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_13/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_13/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_13/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_13/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_13/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_15/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_13/DFFR_1_/Q -to fpga_top/sb_0__2_/mem_bottom_track_15/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_15/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_15/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_15/DFFR_0_/Q -to fpga_top/sb_0__2_/mem_bottom_track_15/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__2_/mem_bottom_track_15/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__2_/mem_bottom_track_15/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_1_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_2_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_3_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_4_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_5_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_left_ipin_0/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_1_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_2_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_3_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_4_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_5_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_0_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_0/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_1_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_2_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_3_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_4_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_5_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_0_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_1/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_1_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_2_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_3_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_4_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_5_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_0_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_2/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_1_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_2_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_3_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_4_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_5_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_0_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_3/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_1_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_2_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_3_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_4_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_5_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_0_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_4/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_1_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_2_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_3_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_4_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_5_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_0_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_5/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_1_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_2_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_3_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_4_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_5_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_0_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_6/DFFR_5_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_1_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_0_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_2_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_1_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_3_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_2_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_4_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_3_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_5_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_4_/Q -to fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_5_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/cby_0__2_/mem_right_ipin_7/DFFR_5_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_6_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_6_/Q -to fpga_top/sb_0__1_/mem_top_track_0/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_7_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_0/DFFR_7_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_top_track_8/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_8/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_top_track_16/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_top_track_16/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_6_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_6_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_7_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFFR_7_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_5_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_6_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_6_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_7_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFFR_7_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_3_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_4_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_3_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_4_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_5_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_3_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_4_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_5_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_3_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_4_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_5_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_3_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_4_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_5_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_3_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_4_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_5_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_3_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_4_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_5_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_3_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_4_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_5_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_3_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_4_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_5_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFFR_5_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_3_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_4_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_3_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_5_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_4_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_5_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFFR_5_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFFR_mem/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_7_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_7_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFFR_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFFR_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFFR_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFFR_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFFR_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFFR_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFFR_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFFR_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFFR_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFFR_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFFR_1_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFFR_1_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFFR_0_/D 2.5 set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_0/DFFR_0_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFFR_1_/D 5 set_min_delay -from fpga_top/cby_1__1_/mem_left_ipin_0/DFFR_0_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFFR_1_/D 2.5 set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_0/DFFR_1_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFFR_2_/D 5 @@ -1961,208 +1981,188 @@ set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_7_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_8_/D 2.5 set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_8_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_9_/D 5 set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_8_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_9_/D 2.5 -set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_9_/Q -to fpga_top/sb_2__0_/mem_top_track_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_9_/Q -to fpga_top/sb_2__0_/mem_top_track_0/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_0/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_0/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_0/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_0/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_0/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_2/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_0/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_2/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_2/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_2/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_2/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_2/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_2/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_4/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_2/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_4/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_4/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_4/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_4/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_4/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_4/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_6/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_4/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_6/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_6/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_6/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_6/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_6/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_6/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_8/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_6/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_8/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_8/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_8/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_8/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_8/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_8/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_10/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_8/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_10/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_10/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_10/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_10/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_10/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_10/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_12/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_10/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_12/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_12/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_12/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_12/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_12/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_12/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_14/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_12/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_14/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_14/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_14/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_14/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_14/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_14/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_16/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_14/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_16/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_16/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_16/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_16/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_16/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_16/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_18/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_16/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_top_track_18/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_18/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_18/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_18/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_top_track_18/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_top_track_18/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_top_track_18/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_1/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_3/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_1/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_3/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_3/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_3/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_3/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_3/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_3/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_5/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_3/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_5/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_5/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_5/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_5/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_5/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_5/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_7/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_5/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_7/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_7/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_7/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_7/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_7/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_7/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_7/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_9/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_11/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_9/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_11/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_11/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_11/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_11/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_11/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_11/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_13/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_11/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_13/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_13/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_13/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_13/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_13/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_13/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_15/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_13/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_15/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_15/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_15/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_15/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_15/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_15/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_15/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_17/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_19/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_17/DFFR_1_/Q -to fpga_top/sb_2__0_/mem_left_track_19/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_19/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_19/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_19/DFFR_0_/Q -to fpga_top/sb_2__0_/mem_left_track_19/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__0_/mem_left_track_19/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__0_/mem_left_track_19/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_0/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_1/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_3/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_2/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_3/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_3/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_3/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_3/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_3/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_3/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_4/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_3/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_4/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_4/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_4/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_4/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_4/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_4/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_5/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_4/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_5/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_5/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_5/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_5/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_bottom_ipin_5/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_5/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_bottom_ipin_5/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_0/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_1/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_2/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_3/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_4/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_5/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_6/DFFR_5_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_0_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_2_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_1_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_3_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_2_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_4_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_3_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_5_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_4_/Q -to fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_5_/Q -to fpga_top/cby_2__1_/mem_left_ipin_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__0_/mem_top_ipin_7/DFFR_5_/Q -to fpga_top/cby_2__1_/mem_left_ipin_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_9_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_9_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_11/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_11/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_11/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_11/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_11/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_11/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_11/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_13/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_11/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_13/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_13/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_13/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_13/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_13/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__1_/mem_left_track_13/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__1_/mem_left_track_13/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_3/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_3/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_3/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_3/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_3/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_3/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_3/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_4/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_3/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_4/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_4/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_4/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_4/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_4/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_4/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_5/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_4/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_5/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_5/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_5/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_5/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_5/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_5/DFFR_1_/Q -to fpga_top/cby_2__1_/mem_left_ipin_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_5/DFFR_1_/Q -to fpga_top/cby_2__1_/mem_left_ipin_0/DFFR_0_/D 2.5 set_max_delay -from fpga_top/cby_2__1_/mem_left_ipin_0/DFFR_0_/Q -to fpga_top/cby_2__1_/mem_left_ipin_0/DFFR_1_/D 5 set_min_delay -from fpga_top/cby_2__1_/mem_left_ipin_0/DFFR_0_/Q -to fpga_top/cby_2__1_/mem_left_ipin_0/DFFR_1_/D 2.5 set_max_delay -from fpga_top/cby_2__1_/mem_left_ipin_0/DFFR_1_/Q -to fpga_top/cby_2__1_/mem_left_ipin_0/DFFR_2_/D 5 @@ -2921,188 +2921,176 @@ set_max_delay -from fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle set_min_delay -from fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_7_/Q -to fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_8_/D 2.5 set_max_delay -from fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_8_/Q -to fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_9_/D 5 set_min_delay -from fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_8_/Q -to fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_9_/D 2.5 -set_max_delay -from fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_9_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_9_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_top_track_0/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_0/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_top_track_8/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_8/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_top_track_16/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_top_track_16/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_1/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_9/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_6_/Q -to fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_bottom_track_17/DFFR_7_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_left_track_1/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_1/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_left_track_3/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_3/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_left_track_5/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_5/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_2_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_3_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_4_/Q -to fpga_top/sb_2__1_/mem_left_track_7/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_7/DFFR_5_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_9/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_11/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_9/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_11/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_11/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_11/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_11/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_11/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_11/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_13/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_11/DFFR_1_/Q -to fpga_top/sb_2__1_/mem_left_track_13/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_13/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_13/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_13/DFFR_0_/Q -to fpga_top/sb_2__1_/mem_left_track_13/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_2__1_/mem_left_track_13/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_2__1_/mem_left_track_13/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_0/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_1/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_3/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_2/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_3/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_3/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_3/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_3/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_3/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_3/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_4/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_3/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_4/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_4/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_4/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_4/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_4/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_4/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_5/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_4/DFFR_1_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_5/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_5/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_5/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_5/DFFR_0_/Q -to fpga_top/cbx_2__1_/mem_bottom_ipin_5/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_5/DFFR_1_/Q -to fpga_top/cby_2__2_/mem_left_ipin_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_2__1_/mem_bottom_ipin_5/DFFR_1_/Q -to fpga_top/cby_2__2_/mem_left_ipin_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_9_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_clb_2__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_9_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_1/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_3/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_3/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_3/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_3/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_3/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_3/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_3/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_5/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_3/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_5/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_5/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_5/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_5/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_5/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_5/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_7/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_5/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_7/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_7/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_7/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_7/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_7/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_7/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_7/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_9/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_11/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_11/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_11/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_11/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_11/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_11/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_11/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_13/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_11/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_13/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_13/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_13/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_13/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_13/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_13/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_15/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_13/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_15/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_15/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_15/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_15/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_15/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_15/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_15/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_17/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_19/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_17/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_bottom_track_19/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_19/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_19/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_19/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_bottom_track_19/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_bottom_track_19/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_bottom_track_19/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_1/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_3/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_1/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_3/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_3/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_3/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_3/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_3/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_3/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_5/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_3/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_5/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_5/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_5/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_5/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_5/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_5/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_7/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_5/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_7/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_7/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_7/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_7/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_7/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_7/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_7/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_9/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_11/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_9/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_11/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_11/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_11/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_11/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_11/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_11/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_13/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_11/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_13/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_13/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_13/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_13/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_13/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_13/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_15/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_13/DFFR_1_/Q -to fpga_top/sb_2__2_/mem_left_track_15/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_15/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_15/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_15/DFFR_0_/Q -to fpga_top/sb_2__2_/mem_left_track_15/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_2__2_/mem_left_track_15/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_2__2_/mem_left_track_15/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_0/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_1/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_2/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_3/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_4/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_5/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_6/DFFR_5_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_0_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_1_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_2_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_3_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_4_/Q -to fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_5_/Q -to fpga_top/cby_2__2_/mem_left_ipin_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_2__2_/mem_bottom_ipin_7/DFFR_5_/Q -to fpga_top/cby_2__2_/mem_left_ipin_0/DFFR_0_/D 2.5 set_max_delay -from fpga_top/cby_2__2_/mem_left_ipin_0/DFFR_0_/Q -to fpga_top/cby_2__2_/mem_left_ipin_0/DFFR_1_/D 5 set_min_delay -from fpga_top/cby_2__2_/mem_left_ipin_0/DFFR_0_/Q -to fpga_top/cby_2__2_/mem_left_ipin_0/DFFR_1_/D 2.5 set_max_delay -from fpga_top/cby_2__2_/mem_left_ipin_0/DFFR_1_/Q -to fpga_top/cby_2__2_/mem_left_ipin_0/DFFR_2_/D 5 @@ -3861,224 +3849,236 @@ set_max_delay -from fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle set_min_delay -from fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_7_/Q -to fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_8_/D 2.5 set_max_delay -from fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_8_/Q -to fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_9_/D 5 set_min_delay -from fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_8_/Q -to fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_9_/D 2.5 -set_max_delay -from fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_9_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_9_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_top_track_0/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_0/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_top_track_8/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_8/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_top_track_16/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_top_track_16/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_right_track_0/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_0/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_right_track_8/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_8/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_right_track_16/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_right_track_16/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFFR_7_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_1_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_0_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_2_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_1_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_2_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_3_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_2_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_3_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_4_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_3_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_4_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_5_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_4_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_5_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_6_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_5_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_6_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_7_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_6_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFFR_7_/D 2.5 -set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_7_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFFR_7_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFFR_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFFR_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFFR_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFFR_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFFR_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFFR_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFFR_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFFR_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFFR_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFFR_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFFR_0_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFFR_1_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFFR_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFFR_1_/D 2.5 -set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFFR_1_/Q -to fpga_top/cby_1__2_/mem_left_ipin_0/DFFR_0_/D 5 -set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFFR_1_/Q -to fpga_top/cby_1__2_/mem_left_ipin_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_9_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/grid_clb_2__2_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFFR_9_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_6_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_6_/Q -to fpga_top/sb_1__2_/mem_right_track_0/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_7_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_0/DFFR_7_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_6_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_6_/Q -to fpga_top/sb_1__2_/mem_right_track_8/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_7_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_8/DFFR_7_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_right_track_16/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_right_track_16/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_1/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_bottom_track_5/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_3/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_bottom_track_5/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_5/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_5/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_5/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_5/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_5/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_7/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_5/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_7/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_7/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_7/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_7/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_7/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_7/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_7/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_9/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_11/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_9/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_11/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_11/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_11/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_11/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_11/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_11/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_13/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_11/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_bottom_track_13/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_13/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_13/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_13/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_bottom_track_13/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_bottom_track_13/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_bottom_track_13/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_6_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_6_/Q -to fpga_top/sb_1__2_/mem_left_track_1/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_7_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_1/DFFR_7_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_6_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_5_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_6_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_6_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_7_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_6_/Q -to fpga_top/sb_1__2_/mem_left_track_9/DFFR_7_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_7_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_9/DFFR_7_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_1_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_0_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_2_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_1_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_3_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_2_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_4_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_3_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_5_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_4_/Q -to fpga_top/sb_1__2_/mem_left_track_17/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/sb_1__2_/mem_left_track_17/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_0/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_1/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_2/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_3/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_4/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_5/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_6/DFFR_5_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_1_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_0_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_2_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_1_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_3_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_2_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_3_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_4_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_3_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_4_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_5_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_4_/Q -to fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_5_/D 2.5 +set_max_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_5_/Q -to fpga_top/cby_1__2_/mem_left_ipin_0/DFFR_0_/D 5 +set_min_delay -from fpga_top/cbx_1__2_/mem_bottom_ipin_7/DFFR_5_/Q -to fpga_top/cby_1__2_/mem_left_ipin_0/DFFR_0_/D 2.5 set_max_delay -from fpga_top/cby_1__2_/mem_left_ipin_0/DFFR_0_/Q -to fpga_top/cby_1__2_/mem_left_ipin_0/DFFR_1_/D 5 set_min_delay -from fpga_top/cby_1__2_/mem_left_ipin_0/DFFR_0_/Q -to fpga_top/cby_1__2_/mem_left_ipin_0/DFFR_1_/D 2.5 set_max_delay -from fpga_top/cby_1__2_/mem_left_ipin_0/DFFR_1_/Q -to fpga_top/cby_1__2_/mem_left_ipin_0/DFFR_2_/D 5 diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/disable_configurable_memory_outputs.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/disable_configurable_memory_outputs.sdc index b5e84a4e8..2a3f42473 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/disable_configurable_memory_outputs.sdc +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/disable_configurable_memory_outputs.sdc @@ -6,58 +6,6 @@ # Organization: University of Utah ############################################# -set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q -set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN -set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q -set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN -set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/Q -set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/QN -set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q -set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN -set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/Q -set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/QN -set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFFR_*_/Q -set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFFR_*_/QN -set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q -set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q @@ -84,6 +32,62 @@ set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/QN set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFFR_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFFR_*_/QN +set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q +set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN +set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q +set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN +set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q +set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN +set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/Q +set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/QN +set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFFR_*_/Q +set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFFR_*_/QN +set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q +set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN +set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/Q +set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/Q set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFFR_*_/Q @@ -102,6 +106,10 @@ set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q @@ -110,24 +118,14 @@ set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/Q set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/QN set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFFR_*_/Q set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/Q set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q -set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q @@ -136,6 +134,8 @@ set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fabric_bitstream.bit b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fabric_bitstream.bit index 3575fa16e..5336e6ed6 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fabric_bitstream.bit +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fabric_bitstream.bit @@ -339,13 +339,13 @@ 0 0 0 +1 0 0 0 0 0 -0 -0 +1 0 0 0 @@ -357,11 +357,13 @@ 0 0 0 +1 +0 0 0 -1 0 0 +1 0 0 0 @@ -375,21 +377,21 @@ 0 1 0 -1 -0 0 0 0 0 +1 0 0 -1 0 0 0 +1 0 0 0 +1 0 1 0 @@ -397,7 +399,7 @@ 0 0 0 -1 +0 0 1 0 @@ -407,7 +409,7 @@ 0 0 0 -1 +0 0 0 0 @@ -421,7 +423,7 @@ 0 0 0 -1 +0 0 1 0 @@ -429,10 +431,14 @@ 0 0 0 +1 +0 0 0 1 0 +1 +0 0 0 0 @@ -445,7 +451,7 @@ 0 0 0 -1 +0 0 1 0 @@ -827,19 +833,19 @@ 0 0 0 +1 0 0 0 0 0 +1 0 0 0 0 0 -0 -0 -0 +1 0 0 0 @@ -863,11 +869,11 @@ 0 0 0 -1 -0 0 0 +1 0 +1 0 1 0 @@ -877,7 +883,6 @@ 0 0 0 -1 0 0 0 @@ -885,15 +890,15 @@ 0 0 0 -1 0 0 0 +1 +1 0 0 0 0 -1 0 0 0 @@ -904,16 +909,11 @@ 0 0 0 -1 -1 0 0 0 0 0 -1 -0 -1 0 0 0 @@ -1297,26 +1297,20 @@ 0 0 0 -1 -0 0 0 0 0 -1 0 0 0 0 0 -1 0 0 0 0 0 -1 -0 0 0 0 @@ -1345,6 +1339,7 @@ 0 0 0 +1 0 0 0 @@ -1352,6 +1347,7 @@ 0 0 0 +1 0 0 0 @@ -1359,6 +1355,7 @@ 0 0 0 +1 0 0 0 @@ -1366,13 +1363,7 @@ 0 0 0 -0 -0 -0 -0 -0 -0 -0 +1 0 0 0 @@ -1390,10 +1381,9 @@ 0 0 0 +1 0 -0 -0 -0 +1 0 0 0 @@ -1735,25 +1725,21 @@ 0 0 0 -1 0 0 0 0 0 -1 0 0 0 0 0 -1 -0 0 0 +1 0 0 -1 0 0 0 @@ -1765,6 +1751,8 @@ 0 0 0 +0 +0 1 0 0 @@ -1773,15 +1761,15 @@ 0 1 0 +1 0 0 0 0 -1 -0 0 0 0 +1 0 0 0 @@ -1789,11 +1777,13 @@ 0 0 0 +1 0 0 0 0 0 +1 0 1 0 @@ -1811,13 +1801,13 @@ 0 0 0 -1 -0 0 0 +1 0 0 0 +1 0 1 0 @@ -1841,15 +1831,23 @@ 0 0 0 +1 0 +1 +1 +1 +1 +1 +1 +1 +1 +1 0 0 0 0 0 -0 -0 -0 +1 0 0 0 @@ -1868,14 +1866,6 @@ 0 0 1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 @@ -1909,7 +1899,7 @@ 0 0 0 -0 +1 0 1 0 @@ -1917,13 +1907,12 @@ 0 0 0 -1 0 0 +1 0 0 0 -1 0 0 0 @@ -1934,16 +1923,19 @@ 0 0 0 +1 0 0 0 0 0 +1 0 0 0 0 0 +1 0 0 0 @@ -1951,13 +1943,19 @@ 0 0 0 +1 0 0 +1 +0 0 +1 0 0 +1 0 0 +1 0 0 0 @@ -2027,13 +2025,10 @@ 0 0 0 -1 0 0 0 -1 0 -1 0 0 0 @@ -2041,7 +2036,6 @@ 0 0 0 -1 0 0 0 @@ -2055,12 +2049,54 @@ 0 0 0 -1 0 0 0 0 0 +0 +0 +0 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +0 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 1 0 0 @@ -2073,31 +2109,41 @@ 0 0 0 +1 +0 0 0 -1 0 0 1 0 0 -1 +0 0 0 1 0 0 +0 +0 +0 1 0 0 0 0 0 +1 0 0 0 0 0 +1 +0 +0 +0 +0 0 0 0 @@ -2127,38 +2173,38 @@ 0 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0 0 0 -1 0 0 0 0 0 1 +1 0 0 0 0 0 -1 0 0 0 0 0 +0 +0 +1 +1 +1 +1 +1 +1 +1 +1 1 0 0 @@ -2187,7 +2233,7 @@ 0 0 0 -1 +0 0 1 0 @@ -2195,6 +2241,10 @@ 0 0 0 +1 +0 +0 +0 0 0 1 @@ -2221,17 +2271,15 @@ 0 0 0 -1 0 0 +1 0 0 0 -1 0 0 0 -1 0 1 0 @@ -2250,38 +2298,28 @@ 0 0 1 -1 -1 -1 -1 -1 0 -1 -1 0 0 0 0 0 -1 0 +1 0 0 0 0 -1 0 0 0 0 0 -1 0 0 0 0 0 -1 0 0 0 @@ -2293,13 +2331,9 @@ 0 0 0 -0 -0 1 0 -1 0 -1 0 0 0 @@ -2317,8 +2351,6 @@ 0 0 0 -1 -1 0 0 0 @@ -2341,35 +2373,3 @@ 0 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fabric_bitstream.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fabric_bitstream.xml index a2bf18b06..09c3c7723 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fabric_bitstream.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fabric_bitstream.xml @@ -682,1161 +682,1161 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + 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- + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fpga_top.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fpga_top.v index 0ca441363..cf224f409 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fpga_top.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fpga_top.v @@ -359,7 +359,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out; .bottom_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__2__0_top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_), .bottom_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__2__0_top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_), .bottom_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__2__0_top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_), - .ccff_head(cbx_1__2__0_ccff_tail), + .ccff_head(grid_io_top_1_ccff_tail), .bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_), .bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_), .bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_), @@ -382,7 +382,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out; .bottom_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__2__1_top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_), .bottom_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__2__1_top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_), .bottom_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__2__1_top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_), - .ccff_head(cbx_1__2__1_ccff_tail), + .ccff_head(grid_io_right_0_ccff_tail), .bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_1_bottom_width_0_height_0_subtile_0__pin_inpad_0_), .bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_1_bottom_width_0_height_0_subtile_1__pin_inpad_0_), .bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_1_bottom_width_0_height_0_subtile_2__pin_inpad_0_), @@ -451,7 +451,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out; .top_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_), .top_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_), .top_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_), - .ccff_head(grid_io_bottom_1_ccff_tail), + .ccff_head(cbx_1__0__1_ccff_tail), .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_), .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_), .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_), @@ -474,7 +474,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out; .top_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_), .top_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_), .top_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_), - .ccff_head(ccff_head), + .ccff_head(cbx_1__0__0_ccff_tail), .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_0__pin_inpad_0_), .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_1__pin_inpad_0_), .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_2__pin_inpad_0_), @@ -684,7 +684,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out; .right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_5__pin_inpad_0_), .right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_6__pin_inpad_0_), .right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_7__pin_inpad_0_), - .ccff_head(grid_io_left_1_ccff_tail), + .ccff_head(ccff_head), .chany_top_out(sb_0__0__0_chany_top_out[0:9]), .chanx_right_out(sb_0__0__0_chanx_right_out[0:9]), .ccff_tail(sb_0__0__0_ccff_tail)); @@ -715,7 +715,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out; .bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_5__pin_inpad_0_), .bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_6__pin_inpad_0_), .bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_7__pin_inpad_0_), - .ccff_head(sb_0__2__0_ccff_tail), + .ccff_head(grid_io_left_1_ccff_tail), .chany_top_out(sb_0__1__0_chany_top_out[0:9]), .chanx_right_out(sb_0__1__0_chanx_right_out[0:9]), .chany_bottom_out(sb_0__1__0_chany_bottom_out[0:9]), @@ -781,7 +781,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out; .left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_5__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_6__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_7__pin_inpad_0_), - .ccff_head(grid_io_left_0_ccff_tail), + .ccff_head(sb_0__0__0_ccff_tail), .chany_top_out(sb_1__0__0_chany_top_out[0:9]), .chanx_right_out(sb_1__0__0_chanx_right_out[0:9]), .chanx_left_out(sb_1__0__0_chanx_left_out[0:9]), @@ -810,7 +810,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out; .left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_5_(grid_clb_1_bottom_width_0_height_0_subtile_0__pin_O_5_), .left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_6_(grid_clb_1_bottom_width_0_height_0_subtile_0__pin_O_6_), .left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_7_(grid_clb_1_bottom_width_0_height_0_subtile_0__pin_O_7_), - .ccff_head(grid_clb_3_ccff_tail), + .ccff_head(grid_io_left_0_ccff_tail), .chany_top_out(sb_1__1__0_chany_top_out[0:9]), .chanx_right_out(sb_1__1__0_chanx_right_out[0:9]), .chany_bottom_out(sb_1__1__0_chany_bottom_out[0:9]), @@ -843,7 +843,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out; .left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_5__pin_inpad_0_), .left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_6__pin_inpad_0_), .left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_7__pin_inpad_0_), - .ccff_head(grid_io_top_1_ccff_tail), + .ccff_head(grid_clb_3_ccff_tail), .chanx_right_out(sb_1__2__0_chanx_right_out[0:9]), .chany_bottom_out(sb_1__2__0_chany_bottom_out[0:9]), .chanx_left_out(sb_1__2__0_chanx_left_out[0:9]), @@ -878,7 +878,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out; .left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_5__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_6__pin_inpad_0_), .left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_7__pin_inpad_0_), - .ccff_head(grid_clb_0_ccff_tail), + .ccff_head(grid_io_bottom_1_ccff_tail), .chany_top_out(sb_2__0__0_chany_top_out[0:9]), .chanx_left_out(sb_2__0__0_chanx_left_out[0:9]), .ccff_tail(sb_2__0__0_ccff_tail)); @@ -917,7 +917,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out; .left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_5_(grid_clb_3_bottom_width_0_height_0_subtile_0__pin_O_5_), .left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_6_(grid_clb_3_bottom_width_0_height_0_subtile_0__pin_O_6_), .left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_7_(grid_clb_3_bottom_width_0_height_0_subtile_0__pin_O_7_), - .ccff_head(grid_clb_2_ccff_tail), + .ccff_head(grid_clb_0_ccff_tail), .chany_top_out(sb_2__1__0_chany_top_out[0:9]), .chany_bottom_out(sb_2__1__0_chany_bottom_out[0:9]), .chanx_left_out(sb_2__1__0_chanx_left_out[0:9]), @@ -948,7 +948,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out; .left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_top_1_bottom_width_0_height_0_subtile_5__pin_inpad_0_), .left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_top_1_bottom_width_0_height_0_subtile_6__pin_inpad_0_), .left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_top_1_bottom_width_0_height_0_subtile_7__pin_inpad_0_), - .ccff_head(grid_io_right_0_ccff_tail), + .ccff_head(grid_clb_2_ccff_tail), .chany_bottom_out(sb_2__2__0_chany_bottom_out[0:9]), .chanx_left_out(sb_2__2__0_chanx_left_out[0:9]), .ccff_tail(sb_2__2__0_ccff_tail)); @@ -1074,7 +1074,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_0__0__0_chany_top_out[0:9]), .chany_top_in(sb_0__1__0_chany_bottom_out[0:9]), - .ccff_head(sb_0__0__0_ccff_tail), + .ccff_head(sb_0__1__0_ccff_tail), .chany_bottom_out(cby_0__1__0_chany_bottom_out[0:9]), .chany_top_out(cby_0__1__0_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_clk_0_(cby_0__1__0_right_grid_left_width_0_height_0_subtile_0__pin_clk_0_), @@ -1093,7 +1093,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_0__1__0_chany_top_out[0:9]), .chany_top_in(sb_0__2__0_chany_bottom_out[0:9]), - .ccff_head(sb_0__1__0_ccff_tail), + .ccff_head(sb_0__2__0_ccff_tail), .chany_bottom_out(cby_0__1__1_chany_bottom_out[0:9]), .chany_top_out(cby_0__1__1_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_clk_0_(cby_0__1__1_right_grid_left_width_0_height_0_subtile_0__pin_clk_0_), @@ -1112,7 +1112,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_1__0__0_chany_top_out[0:9]), .chany_top_in(sb_1__1__0_chany_bottom_out[0:9]), - .ccff_head(cbx_1__0__0_ccff_tail), + .ccff_head(cbx_1__1__0_ccff_tail), .chany_bottom_out(cby_1__1__0_chany_bottom_out[0:9]), .chany_top_out(cby_1__1__0_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_clk_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_0__pin_clk_0_), @@ -1129,7 +1129,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_1__1__0_chany_top_out[0:9]), .chany_top_in(sb_1__2__0_chany_bottom_out[0:9]), - .ccff_head(cbx_1__1__0_ccff_tail), + .ccff_head(cbx_1__2__0_ccff_tail), .chany_bottom_out(cby_1__1__1_chany_bottom_out[0:9]), .chany_top_out(cby_1__1__1_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_clk_0_(cby_1__1__1_right_grid_left_width_0_height_0_subtile_0__pin_clk_0_), @@ -1146,7 +1146,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_2__0__0_chany_top_out[0:9]), .chany_top_in(sb_2__1__0_chany_bottom_out[0:9]), - .ccff_head(cbx_1__0__1_ccff_tail), + .ccff_head(cbx_1__1__1_ccff_tail), .chany_bottom_out(cby_2__1__0_chany_bottom_out[0:9]), .chany_top_out(cby_2__1__0_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_2__1__0_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), @@ -1170,7 +1170,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out; .prog_clk(prog_clk), .chany_bottom_in(sb_2__1__0_chany_top_out[0:9]), .chany_top_in(sb_2__2__0_chany_bottom_out[0:9]), - .ccff_head(cbx_1__1__1_ccff_tail), + .ccff_head(cbx_1__2__1_ccff_tail), .chany_bottom_out(cby_2__1__1_chany_bottom_out[0:9]), .chany_top_out(cby_2__1__1_chany_top_out[0:9]), .right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_2__1__1_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_0__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_0__1_.xml index 8e3ce2cdb..58b265d13 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_0__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_0__1_.xml @@ -1,56 +1,56 @@ - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_0__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_0__2_.xml index 598b91e22..15a476439 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_0__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_0__2_.xml @@ -1,56 +1,56 @@ - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_1__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_1__1_.xml index 4742a8f45..9fc5a8117 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_1__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_1__1_.xml @@ -1,44 +1,44 @@ - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_1__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_1__2_.xml index d96c9a38d..405c9abaf 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_1__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_1__2_.xml @@ -1,44 +1,44 @@ - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_2__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_2__1_.xml index 853598113..d3421c3bc 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_2__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_2__1_.xml @@ -1,86 +1,86 @@ - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_2__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_2__2_.xml index a5aff3785..586a15615 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_2__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_2__2_.xml @@ -1,86 +1,86 @@ - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__1_.xml index 3afea90e8..d09d7c254 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__1_.xml @@ -1,56 +1,56 @@ - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__2_.xml index 3a9b8024d..6b47a0491 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__2_.xml @@ -1,56 +1,56 @@ - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__1_.xml index 2e584b8ab..6acef668f 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__1_.xml @@ -1,44 +1,44 @@ - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__2_.xml index f3b69185d..106e8f2bb 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__2_.xml @@ -1,44 +1,44 @@ - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__1_.xml index 6561ddb64..c3c93bfa1 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__1_.xml @@ -1,86 +1,86 @@ - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__2_.xml index 5d742ce89..b99a0f7f3 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__2_.xml @@ -1,86 +1,86 @@ - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + From f42884304aff1d0d05dd692cc1f0ba7617ab99aa Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 9 Jul 2024 11:40:41 -0700 Subject: [PATCH 91/91] [doc] update clock network details --- docs/source/manual/file_formats/clock_network.rst | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/docs/source/manual/file_formats/clock_network.rst b/docs/source/manual/file_formats/clock_network.rst index 8bab91b43..60cd10eff 100644 --- a/docs/source/manual/file_formats/clock_network.rst +++ b/docs/source/manual/file_formats/clock_network.rst @@ -187,6 +187,8 @@ Switch Point Settings The following syntax are applicable to the XML definition tagged by ``switch_point``. Note that a number of switch points can be defined under each clock spine ``spine``. +.. note:: Use the coordinate of switch block to define switching points! + .. option:: tap="" Define which clock spine will be tapped from the current clock spine. @@ -307,6 +309,8 @@ For example, where all the clock spines of the clock network ``clk_tree_0`` tap the clock pins ``clk`` of tile ``clb`` in a VPR architecture description file: +.. note:: Use the name of ``subtile`` in the ``to_pin`` when there are a number of subtiles in your tile! + .. code-block:: xml

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