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[test] debugging

This commit is contained in:
tangxifan 2024-07-07 23:07:51 -07:00
parent b0851a6299
commit ff56139a53
4 changed files with 12 additions and 6 deletions
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5
openfpga_flow/openfpga_arch/k4_N4_40nm_ClkNtwk_registerable_io_cc_openfpga.xml
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@ -175,7 +175,10 @@
<tile_annotations>
<global_port name="clk" is_clock="true" default_val="0" clk_tree_name="clk_tree_2lvl">
<tile name="clb" port="clk" x="-1" y="-1"/>
<tile name="io" port="clk" x="-1" y="-1"/>
<tile name="io_top" port="clk" x="-1" y="-1"/>
<tile name="io_right" port="clk" x="-1" y="-1"/>
<tile name="io_bottom" port="clk" x="-1" y="-1"/>
<tile name="io_left" port="clk" x="-1" y="-1"/>
</global_port>
</tile_annotations>
<pb_type_annotations>

7
openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/clk_arch_1clk_2layer.xml
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@ -4,7 +4,7 @@
<switch_point tap="rib_lvl1_sw0_upper" x="0" y="1"/>
<switch_point tap="rib_lvl1_sw0_lower" x="0" y="1"/>
<switch_point tap="rib_lvl1_sw1_upper" x="1" y="1"/>
<switch_point tap="rib_lvl1_sw2_lower" x="1" y="1"/>
<switch_point tap="rib_lvl1_sw1_lower" x="1" y="1"/>
<switch_point tap="rib_lvl1_sw2_upper" x="2" y="1"/>
<switch_point tap="rib_lvl1_sw2_lower" x="2" y="1"/>
</spine>
@ -16,7 +16,10 @@
<spine name="rib_lvl1_sw2_lower" start_x="2" start_y="1" end_x="2" end_y="0" type="CHANY" direction="DEC_DIRECTION"/>
<taps>
<all from_pin="clk[0:0]" to_pin="clb[0:0].clk[0:0]"/>
<all from_pin="clk[0:0]" to_pin="io[0:0].clk[0:0]"/>
<all from_pin="clk[0:0]" to_pin="io_top[0:0].clk[0:0]"/>
<all from_pin="clk[0:0]" to_pin="io_right[0:0].clk[0:0]"/>
<all from_pin="clk[0:0]" to_pin="io_bottom[0:0].clk[0:0]"/>
<all from_pin="clk[0:0]" to_pin="io_left[0:0].clk[0:0]"/>
</taps>
</clock_network>
</clock_networks>

2
openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile/config/task.conf
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@ -22,7 +22,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio
openfpga_vpr_extra_options=
openfpga_pb_pin_fixup_command=
openfpga_vpr_device=2x2
openfpga_vpr_route_chan_width=20
openfpga_vpr_route_chan_width=40
openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml
openfpga_verilog_testbench_options=--explicit_port_mapping
openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_2layer.xml

4
openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml
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@ -206,12 +206,12 @@
<!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.
With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
<segment name="L1" freq="0.000000" length="1" type="unidir" Rmetal="101" Cmetal="22.5e-15">
<segment name="L1" freq="0.800000" length="1" type="unidir" Rmetal="101" Cmetal="22.5e-15">
<mux name="0"/>
<sb type="pattern">1 1</sb>
<cb type="pattern">1</cb>
</segment>
<segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
<segment name="L4" freq="0.200000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
<mux name="0"/>
<sb type="pattern">1 1 1 1 1</sb>
<cb type="pattern">1 1 1 1</cb>