tangxifan
|
91b072d7c5
|
documentation update on the bitstream file format to synchronize with the latest codes
|
2020-06-17 11:56:40 -06:00 |
|
tangxifan
|
ba38120093
|
add documentation for fabric key and reorganize command references
|
2020-06-12 16:15:16 -06:00 |
|
tangxifan
|
1a006f2ddb
|
update documentation for separated XML files
|
2020-06-11 19:31:16 -06:00 |
|
tangxifan
|
b9dd47d465
|
update documentation about memory bank configuration protocol
|
2020-06-11 19:31:14 -06:00 |
|
tangxifan
|
c00653961e
|
minor format fix in documentation
|
2020-06-11 19:31:13 -06:00 |
|
tangxifan
|
0931eccbf6
|
update documentation for the fast configuration options
|
2020-06-11 19:31:13 -06:00 |
|
tangxifan
|
fe2ba7d50a
|
update documentation for standalone configuration protocol
|
2020-06-11 19:31:13 -06:00 |
|
tangxifan
|
de07712a3a
|
update documentation about the frame-based configuration protocol
|
2020-06-11 19:31:11 -06:00 |
|
tangxifan
|
1150b903a5
|
add quick start tutorial for architecture modeling
|
2020-06-11 19:31:09 -06:00 |
|
tangxifan
|
339bf87c43
|
add missing file
|
2020-06-11 19:31:09 -06:00 |
|
tangxifan
|
aa77ee9af6
|
add tutorial for full testbench run
|
2020-06-11 19:31:09 -06:00 |
|
tangxifan
|
35536ee594
|
renaming design flows in documentation
|
2020-06-11 19:31:09 -06:00 |
|
tangxifan
|
011ce5cdf6
|
minor fix on the documentation
|
2020-06-11 19:31:08 -06:00 |
|
tangxifan
|
f079c61bd3
|
re organize tutorials
|
2020-06-11 19:31:08 -06:00 |
|
tangxifan
|
dcce782a46
|
update documentation about Verilog testbenches
|
2020-06-11 19:31:08 -06:00 |
|
tangxifan
|
c5a3e44e61
|
Update Verilog fabric netlist documentation
|
2020-06-11 19:31:08 -06:00 |
|
tangxifan
|
cae7fe0fed
|
minor fix on the manual subtree
|
2020-06-11 19:31:08 -06:00 |
|
tangxifan
|
c27d77a418
|
clean-up documentation for a shallow hierarchy
|
2020-06-11 19:31:08 -06:00 |
|
tangxifan
|
f6895fcc14
|
update documentation for new options of Verilog testbench writer
|
2020-06-11 19:31:07 -06:00 |
|
tangxifan
|
c2a81c76e1
|
update doc for new options
|
2020-06-11 19:31:07 -06:00 |
|
tangxifan
|
f4dd882f0f
|
documentation updated for new command
|
2020-06-11 19:31:06 -06:00 |
|
tangxifan
|
df9cf32b49
|
update documenation for configuration chain writer
|
2020-06-11 19:31:06 -06:00 |
|
Xifan Tang
|
24934aff86
|
update documentation on the depth option for fabric hierarchy writer
|
2020-06-11 19:31:04 -06:00 |
|
Xifan Tang
|
752470c2da
|
update documentation on write hierarchy command and options
|
2020-06-11 19:31:04 -06:00 |
|
Xifan Tang
|
ac378febef
|
update doc about time units in SDC generator
|
2020-06-11 19:31:03 -06:00 |
|
Xifan Tang
|
d18e924a89
|
Update documentation on new fpga_sdc option
|
2020-06-11 19:31:03 -06:00 |
|
Xifan Tang
|
ecdbdcb592
|
update documentation on new SDC options
|
2020-06-11 19:31:02 -06:00 |
|
Xifan Tang
|
52adebacfb
|
update doc for file options in openfpga bitstream
|
2020-04-21 14:40:53 -06:00 |
|
Xifan Tang
|
b4542ea34b
|
minor fix on doc about the global and general purpose port
|
2020-04-09 17:10:04 -06:00 |
|
Xifan Tang
|
d99776b260
|
update documentation on the global I/O ports
|
2020-04-08 18:18:53 -06:00 |
|
Xifan Tang
|
b9ade3fcb6
|
documentation update to introduce new features in script mode of OpenFPGA shell
|
2020-04-08 14:13:28 -06:00 |
|
Xifan Tang
|
55e68896d6
|
doc update for the support on std cell MUX2 and examples
|
2020-04-07 12:01:13 -06:00 |
|
Xifan Tang
|
7a4137fdcf
|
doc update for packable XML syntax in VPR
|
2020-04-06 18:37:05 -06:00 |
|
Xifan Tang
|
1a3a748dd2
|
update documentation with the support on spypads and global I/O ports
|
2020-04-05 20:12:28 -06:00 |
|
Xifan Tang
|
6ce0fe4ef2
|
doc update for FPGA-bitstream to better motivate the different types of bitstream
|
2020-04-01 12:57:28 -06:00 |
|
Xifan Tang
|
fd8248d9dd
|
update documentation: the addon syntax on VPR and configuration protocols
|
2020-04-01 12:35:52 -06:00 |
|
tangxifan
|
78964ce71c
|
update documentation on the through channel
|
2020-03-27 11:34:39 -06:00 |
|
Xifan Tang
|
b4221e94bb
|
add documentation on the tileable routing and thru channel support
|
2020-03-25 16:52:42 -06:00 |
|
Xifan Tang
|
cb6afea07c
|
update documentation on a new option in FPGA-SDC to constrain zero-delay paths
|
2020-03-25 16:00:25 -06:00 |
|
Xifan Tang
|
3a74fb7a04
|
update documentation for the new options
|
2020-03-25 15:23:21 -06:00 |
|
Xifan Tang
|
7e3a8e5794
|
typo fixed in fpga-bitstream documentation
|
2020-03-22 16:27:12 -06:00 |
|
Xifan Tang
|
75dfe6a045
|
update documentation for write_gsb_to_xml functionality
|
2020-03-22 16:21:35 -06:00 |
|
tangxifan
|
1d766d2a70
|
minor format fix on documentation
|
2020-03-11 10:22:30 -06:00 |
|
Xifan Tang
|
b941ac8a4a
|
remove deprecated options
|
2020-03-10 20:58:00 -06:00 |
|
Xifan Tang
|
8037d1ad93
|
Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
|
2020-03-10 20:55:02 -06:00 |
|
Xifan Tang
|
9f743f7f4e
|
add openfpga shell documentation
|
2020-03-10 20:54:42 -06:00 |
|
tangxifan
|
0da6f00af5
|
start reworking the openfpga tool documentation
|
2020-03-10 17:29:35 -06:00 |
|
tangxifan
|
089cc5e86e
|
update documentation on circuit model annotation on VPR architecture
|
2020-03-10 16:51:50 -06:00 |
|
tangxifan
|
7195564455
|
reworked circuit model examples in documentation. Now we are consistent to latest syntax
|
2020-03-10 16:17:20 -06:00 |
|
tangxifan
|
54dfdc0cc1
|
update general documentation on circuit library
|
2020-03-10 12:18:12 -06:00 |
|
tangxifan
|
2a3c5b98a5
|
minor format fix in documentation
|
2020-03-09 21:25:13 -06:00 |
|
Xifan Tang
|
d14fa16905
|
finish documentation update on technology library
|
2020-03-09 21:17:25 -06:00 |
|
Xifan Tang
|
cb7e4a1dfa
|
finish documentation the simulation settings in VPR8 integration
|
2020-03-09 20:03:37 -06:00 |
|
tangxifan
|
751735bf41
|
update documentation in simulation setting syntax
|
2020-03-09 17:40:33 -06:00 |
|
tangxifan
|
3c7fd30e12
|
merged tutorial to online documentation and reworked compilation guidelines
|
2020-03-09 13:58:24 -06:00 |
|
tangxifan
|
af6319a6b0
|
reworked motivation in documentation
|
2020-03-09 11:27:25 -06:00 |
|
tangxifan
|
73da4a1d6e
|
rework motivation for FPGA-Verilog and FPGA-Bitstream in documentation
|
2020-03-09 10:32:03 -06:00 |
|
tangxifan
|
f821e60405
|
clean up deadlinks in doc
|
2020-03-09 10:15:16 -06:00 |
|
tangxifan
|
d61ae5561b
|
start cleanup the documentation for openfpga shell
|
2020-03-09 09:44:19 -06:00 |
|
tangxifan
|
f67981afa8
|
update ducoumentation to explain lib_name XML syntax
|
2020-01-08 14:22:17 -07:00 |
|
tangxifan
|
13f964ea72
|
add bitstream file format introduction
|
2019-12-04 13:41:31 -07:00 |
|
tangxifan
|
40bddd4ed7
|
add FPL'19 paper to documentation reference
|
2019-12-04 12:05:30 -07:00 |
|
tangxifan
|
323c4fdc9a
|
clean up documentation build warnings and add guidelines for port naming
|
2019-12-04 11:59:10 -07:00 |
AurelienUoU
|
36f7624b95
|
Point to point truth table typo fix
|
2019-10-01 13:07:27 -06:00 |
|
AurelienUoU
|
e2867019e1
|
Typo fixing
|
2019-09-30 10:38:02 -06:00 |
|
AurelienUoU
|
74f7a3cfb2
|
Doc fixing
|
2019-09-30 10:29:42 -06:00 |
|
AurelienUoU
|
5ac79f4805
|
Point to point documentation
|
2019-09-30 10:00:46 -06:00 |
Ganesh Gore
|
48ec1eefcd
|
Added fpga_task cmd options in doc [ci skip]
|
2019-09-02 02:45:05 -06:00 |
|
Ganesh Gore
|
241b001282
|
Added openfpga_task doc
|
2019-09-01 22:15:53 -06:00 |
|
Ganesh Gore
|
32d47d6b8b
|
Update document + Travis cache check
|
2019-08-31 16:13:47 -06:00 |
|
Ganesh Gore
|
06c0dbb328
|
Added docuementation for fpga_flow
|
2019-08-31 15:19:34 -06:00 |
|
tangxifan
|
42b528be57
|
doc updates
|
2019-08-21 15:11:25 -06:00 |
|
tangxifan
|
9c43b1b753
|
complete refacotriing the inv and buf part in submodules
|
2019-08-21 14:54:05 -06:00 |
|
tangxifan
|
b207050b03
|
minor fix in documentation
|
2019-08-06 14:17:57 -06:00 |
|
tangxifan
|
fc93a4941a
|
update documentation
|
2019-08-06 14:17:56 -06:00 |
|
tangxifan
|
7603850d72
|
complete documentation for new features
|
2019-08-06 14:17:56 -06:00 |
|
tangxifan
|
8a046394f8
|
add documentation for multi-mode configurable block support
|
2019-07-30 16:47:41 -06:00 |
|
Xifan Tang
|
afd78604c9
|
Merge branch 'dev' into documentation: resolved conflicts and add logo files
|
2019-07-17 17:50:11 -04:00 |
|
Xifan Tang
|
e7b40f06b0
|
Add documentation for fracturable LUTs
|
2019-07-17 15:21:07 -04:00 |
|
AurelienUoU
|
1cf4e78502
|
Update documentation and help
|
2019-07-15 21:16:15 -06:00 |
|
AurelienUoU
|
df53f6da2c
|
Updates FPGA-Verilog command lines
|
2019-07-05 13:41:34 -06:00 |
|
AurelienUoU
|
9e99048815
|
Update documentation
Merge branch 'heterogeneous' of https://github.com/LNIS-Projects/OpenFPGA into heterogeneous
|
2019-07-05 11:56:02 -06:00 |
|
AurelienUoU
|
27dbc527a0
|
Update Readme
|
2019-07-05 11:06:55 -06:00 |
|
AurelienUoU
|
f56adc6815
|
Update documentation
|
2019-07-05 10:20:16 -06:00 |
BaudouinChauviere
|
cb34ac0243
|
Update sc_flow.rst
|
2019-04-01 16:30:31 -06:00 |
|
BaudouinChauviere
|
361bbc13e3
|
Update func_verify.rst
|
2019-04-01 16:29:42 -06:00 |
|
BaudouinChauviere
|
a176bf3a19
|
Update file_organization.rst
|
2019-04-01 16:28:48 -06:00 |
|
BaudouinChauviere
|
01371ce54d
|
Update customize_subckt.rst
|
2019-04-01 16:27:06 -06:00 |
|
BaudouinChauviere
|
1ea7ec3265
|
Update spice_simulation.rst
|
2019-04-01 16:26:02 -06:00 |
|
BaudouinChauviere
|
cfdc072164
|
Update file_organization.rst
|
2019-04-01 16:25:09 -06:00 |
|
BaudouinChauviere
|
fcc3bf0967
|
Update command_line_usage.rst
|
2019-04-01 16:23:24 -06:00 |
|
BaudouinChauviere
|
f4b72bd4e1
|
Update link_circuit_modules.rst
|
2019-04-01 16:21:59 -06:00 |
|
BaudouinChauviere
|
ce300c196c
|
Update circuit_modules.rst
|
2019-04-01 16:13:23 -06:00 |
|
BaudouinChauviere
|
6e065ef3b3
|
Update tech_lib.rst
|
2019-04-01 16:09:31 -06:00 |
|
BaudouinChauviere
|
aed779ca3d
|
Update spice_sim_setting.rst
|
2019-04-01 16:08:00 -06:00 |
|
BaudouinChauviere
|
4900caaed9
|
Update generality.rst
|
2019-04-01 16:04:17 -06:00 |
|
BaudouinChauviere
|
33df25366c
|
Update eda_flow.rst
Correction fix
|
2019-04-01 16:02:47 -06:00 |
|
BaudouinChauviere
|
d6261f1f59
|
Update motivation.rst
Typo and better explanations correction
|
2019-04-01 15:57:04 -06:00 |
Baudouin Chauviere
|
39f7b0b9a2
|
Update of the doc for better fit with the current version
|
2019-04-01 11:55:28 -06:00 |
|
BaudouinChauviere
|
5dbcfa6d70
|
Repair broken link
|
2019-01-03 18:26:30 +01:00 |
|
BaudouinChauviere
|
28010f6c91
|
Testing another link method
|
2019-01-03 18:24:06 +01:00 |
Laboratory for Nano Integrated Systems (LNIS)
|
30f2ada557
|
Repaired broken links
|
2019-01-03 18:18:03 +01:00 |
|
LNIS-Projects
|
77dd7f3e04
|
correction of the name of the figure
|
2018-12-29 01:45:45 +01:00 |
|
LNIS-Projects
|
0f6ac32f43
|
Further resizing
|
2018-12-29 01:44:24 +01:00 |
|
LNIS-Projects
|
38a3b01520
|
Resize the images
|
2018-12-29 01:42:43 +01:00 |
|
Baudouin Chauviere
|
9ee50de26a
|
Adding information on the layout
|
2018-12-29 01:14:26 +01:00 |
|
Baudouin Chauviere
|
0a5391c14f
|
Addition of some illustrations
|
2018-12-26 18:16:16 +01:00 |
|
LNIS-Projects
|
de7d646fa0
|
Update func_verify.rst
Functional Verification documentation
|
2018-12-26 18:05:24 +01:00 |
|
LNIS-Projects
|
c0626e9a1c
|
Adding the Verification Step from ModelSim
|
2018-12-26 18:00:03 +01:00 |
|
LNIS-Projects
|
c506e16d33
|
Update command_line_usage.rst
Small fix
|
2018-12-22 14:46:15 +01:00 |
|
LNIS-Projects
|
ba303450e2
|
Update file_organization.rst
|
2018-12-22 14:45:00 +01:00 |
|
LNIS-Projects
|
5fa6c84087
|
New fpga_verilog commands documented
|
2018-12-22 14:39:51 +01:00 |
|
LNIS-Projects
|
55459f7906
|
Update index.rst
Reorganization
|
2018-12-10 13:46:38 -07:00 |
|
LNIS-Projects
|
56555fc8a0
|
Update index.rst
Removed abc from the project because included in Yosys
|
2018-12-10 13:46:02 -07:00 |
|
BaudouinChauviere
|
88af64c606
|
Update eda_flow.rst
Distributions compilable added
|
2018-12-05 16:29:07 -07:00 |
|
BaudouinChauviere
|
576feb600f
|
Update eda_flow.rst
Completed with FPGA-Verilog/Bitstream and corrected few errors
|
2018-12-05 16:24:03 -07:00 |
|
BaudouinChauviere
|
0f87fb9c3f
|
Update file_organization.rst
Correction on the routing
|
2018-12-03 14:21:40 -07:00 |
|
BaudouinChauviere
|
e541834bd0
|
Update file_organization.rst
Made similar to the SPICE one
|
2018-12-03 14:20:34 -07:00 |
|
BaudouinChauviere
|
cd301a5bb8
|
Update file_organization.rst
Correction of the hierarchy
|
2018-12-03 14:09:11 -07:00 |
|
BaudouinChauviere
|
9c97125b0d
|
Update spice_simulation.rst
typo
|
2018-12-03 13:42:45 -07:00 |
|
BaudouinChauviere
|
b8f702e16d
|
Update file_organization.rst
Creation of the table for better understanding
|
2018-12-03 13:40:42 -07:00 |
|
BaudouinChauviere
|
10cbd2efef
|
Update index.rst
Commenting the multi mode out until more mature
|
2018-12-03 11:50:13 -07:00 |
|
BaudouinChauviere
|
8e7def7f88
|
Update link_circuit_modules.rst
Correction of typos
|
2018-12-03 11:39:44 -07:00 |
|
BaudouinChauviere
|
f8e801b9d1
|
Merge pull request #1 from LNIS-Projects/Documentation-Update
Update index.rst
|
2018-12-03 11:27:05 -07:00 |
|
BaudouinChauviere
|
a4d29aeb1b
|
Update circuit_model_examples.rst
Typo correction
|
2018-12-03 11:26:04 -07:00 |
|
BaudouinChauviere
|
e39e0219e9
|
Update circuit_modules.rst
Move the examples from this part to their own
|
2018-12-03 10:59:20 -07:00 |
|
BaudouinChauviere
|
7a49ca8ce2
|
Update index.rst
New section in the doc
|
2018-12-03 10:58:50 -07:00 |
|
BaudouinChauviere
|
99769c1510
|
Create circuit_model_examples.rst
Better architecture of the doc
|
2018-12-03 10:58:11 -07:00 |
|
BaudouinChauviere
|
47a214520f
|
Update index.rst
Skip lines
|
2018-12-03 10:32:15 -07:00 |
|
BaudouinChauviere
|
6827549be2
|
Update index.rst
Include the links for the external documentation
|
2018-12-03 10:31:02 -07:00 |
Aurelien Alacchi
|
4a950c6857
|
Flatten_hierarchy_doc
|
2018-10-18 16:28:12 -06:00 |
|
Aurelien Alacchi
|
aa5449c37d
|
Verif_modif_doc_title_2
|
2018-10-17 16:49:55 -06:00 |
|
Aurelien Alacchi
|
6327a4486b
|
Revert "Verif_modif_doc_title"
This reverts commit 8f7f88ebea.
|
2018-10-17 16:47:32 -06:00 |
|
Aurelien Alacchi
|
8f7f88ebea
|
Verif_modif_doc_title
|
2018-10-17 16:45:42 -06:00 |
|
Aurelien Alacchi
|
2cfbe2b997
|
FPGA-Verilog_doc_update
|
2018-10-17 16:38:03 -06:00 |
|
Aurelien Alacchi
|
e96c6e2f02
|
Revert "Bug_correction_fpga-spice_commandLine"
This reverts commit 33e76d0255.
|
2018-10-12 16:09:14 -06:00 |
|
Aurelien Alacchi
|
33e76d0255
|
Bug_correction_fpga-spice_commandLine
|
2018-10-12 16:05:53 -06:00 |
|
Aurelien Alacchi
|
26538cb2bc
|
Correction_file_commandline_fpga-spice
|
2018-10-12 16:03:23 -06:00 |
|
Aurelien Alacchi
|
e0c2fc2c8a
|
Documentation_code&example_update
|
2018-10-12 15:50:09 -06:00 |
Aurelien Alacchi
|
07380ed1fa
|
Minor_bug_fig_name_correction
|
2018-10-09 15:33:30 -06:00 |
|
Aurelien Alacchi
|
a43574e593
|
Update_doc_circuit_level_fig_fixed
|
2018-10-09 15:29:15 -06:00 |
|
Aurelien Alacchi
|
d1c01cd68b
|
Update_bug_fig_doc_CL
|
2018-10-08 17:54:44 -06:00 |
|
Aurelien Alacchi
|
7c51129a33
|
test42docFig
|
2018-10-08 16:20:34 -06:00 |
|
Aurelien Alacchi
|
8723722e99
|
test_correction_bug_fig_doc_CL
|
2018-10-08 16:18:56 -06:00 |
|
Aurelien Alacchi
|
ebd4b282f5
|
test_correction_figure
|
2018-10-08 16:00:21 -06:00 |
|
Aurelien Alacchi
|
a318f8e20e
|
Update_doc_circuit_level_bug_image
|
2018-10-08 15:48:54 -06:00 |
|
Aurelien Alacchi
|
f79913f379
|
Update_doc_circuit_level_bug_image
|
2018-10-08 15:42:19 -06:00 |
|
Aurelien Alacchi
|
44bdca0429
|
Revert "figure_correction_doc_circuit_level"
This reverts commit 046829bd13.
|
2018-10-08 15:30:47 -06:00 |
|
Aurelien Alacchi
|
054a2bb186
|
Revert "bug_correction_fig_circuit_level"
This reverts commit c6cd63462c.
|
2018-10-08 15:30:36 -06:00 |
|
Aurelien Alacchi
|
c6cd63462c
|
bug_correction_fig_circuit_level
|
2018-10-08 15:30:03 -06:00 |