tangxifan
|
068d9943e7
|
update all the templates and regression test cases with simulation settings
|
2020-06-11 19:31:16 -06:00 |
|
tangxifan
|
1842bf51e1
|
deploy read_openfpga_simulation_setting in CI on a single test case
|
2020-06-11 19:31:16 -06:00 |
|
tangxifan
|
cb09896f23
|
add example simulation setting for openfpga flow
|
2020-06-11 19:31:15 -06:00 |
|
tangxifan
|
96b58dfdbb
|
use new simulation setting command in openfpga shell
|
2020-06-11 19:31:15 -06:00 |
|
tangxifan
|
c87dbc4880
|
start using counter benchmark in regression tests
|
2020-06-11 19:31:15 -06:00 |
|
tangxifan
|
f73dfa2bcc
|
bug fixed in k6_n10_40 architecture
|
2020-06-11 19:31:15 -06:00 |
|
tangxifan
|
baa2c6b7ef
|
update arch to support reset signal for SRAm
|
2020-06-11 19:31:14 -06:00 |
|
tangxifan
|
aac2e8c805
|
update openfpga architecture for memory bank usage
|
2020-06-11 19:31:14 -06:00 |
|
tangxifan
|
82b04ae3f0
|
add SRAM verilog for memory bank usage
|
2020-06-11 19:31:14 -06:00 |
|
tangxifan
|
3f9afea3e8
|
add preconfig testbench test case for memory bank configuration protocol
|
2020-06-11 19:31:14 -06:00 |
|
tangxifan
|
288294c23a
|
add fast configuration test case for memory bank configuration protocol
|
2020-06-11 19:31:14 -06:00 |
|
tangxifan
|
73d4c835b7
|
add regression test case for memory bank
|
2020-06-11 19:31:13 -06:00 |
|
tangxifan
|
a1ec6833c2
|
add memory bank example arch xml
|
2020-06-11 19:31:13 -06:00 |
|
tangxifan
|
2def059b5b
|
add standalone configuration protocol to pre config test cases
|
2020-06-11 19:31:12 -06:00 |
|
tangxifan
|
5f6a790eff
|
add new test cases for the standalone memory configuration protocol
|
2020-06-11 19:31:12 -06:00 |
|
tangxifan
|
8b5b221a21
|
add new architecture for standalone memory organization
|
2020-06-11 19:31:12 -06:00 |
|
tangxifan
|
a5138113e4
|
add fast configuration testcase
|
2020-06-11 19:31:12 -06:00 |
|
tangxifan
|
8b3e79766c
|
add fast configuration option to fpga_verilog to speed up full testbench simulation
|
2020-06-11 19:31:12 -06:00 |
|
tangxifan
|
05aa166a9e
|
add preconfig testbench cases to regression tests for different configuration protocols
|
2020-06-11 19:31:11 -06:00 |
|
tangxifan
|
827e2e6713
|
file moving in regression tests
|
2020-06-11 19:31:11 -06:00 |
|
tangxifan
|
b5e5182f52
|
frame-based configuration protocol is working on k4n4 arch now. Spot bugs in iVerilog about negedge flip-flops
|
2020-06-11 19:31:11 -06:00 |
|
tangxifan
|
583c15131b
|
change configuration latch to be triggered at negative edge; Frame-based fabric passed Modelsim verification but failed in iVerilog
|
2020-06-11 19:31:11 -06:00 |
|
tangxifan
|
6a72c66eb8
|
bug fixed for frame-based configuration memory in top-level full testbench
|
2020-06-11 19:31:11 -06:00 |
|
tangxifan
|
f5968fda52
|
add configurable latch Verilog codes
|
2020-06-11 19:31:10 -06:00 |
|
tangxifan
|
1e73fd6def
|
create configuration frame example script
|
2020-06-11 19:31:10 -06:00 |
|
tangxifan
|
3a0d3b4e95
|
fix the broken CI/regression tests due to incorrect file path
|
2020-06-11 19:31:10 -06:00 |
|
tangxifan
|
3fa3b17061
|
start testing the frame-based configuration protocol. To distinguish, rename xml to identify between configuration chain and frame-based. This should not impact the pre-config testbenches.
|
2020-06-11 19:31:10 -06:00 |
|
tangxifan
|
bba476fef4
|
add explicit port mapping support to Verilog testbench generator
|
2020-06-11 19:31:07 -06:00 |
|
tangxifan
|
910be3cadb
|
massively deploy disable_timing for configure ports in CI
|
2020-06-11 19:31:06 -06:00 |
|
tangxifan
|
13f591cacf
|
add new command to disable timing for configure ports of programmable modules
|
2020-06-11 19:31:06 -06:00 |
|
tangxifan
|
fc2b09514e
|
add configuration chain write to regression tests
|
2020-06-11 19:31:06 -06:00 |
|
tangxifan
|
1943929353
|
add write_fabric_hierarchy to regression tests
|
2020-06-11 19:31:04 -06:00 |
|
tangxifan
|
98fbcb5410
|
add time unit test for SDC generation to CI
|
2020-06-11 19:31:04 -06:00 |
|
tangxifan
|
4083fae41a
|
add new test cases about user-defined simulation settings
|
2020-06-11 19:31:03 -06:00 |
|
tangxifan
|
2fbf9c2cfc
|
change to a higher simulation clock speed to accelerate CI verification.
Later, we should place simulation information in another XML so that we can reuse that easily
|
2020-06-11 19:31:03 -06:00 |
|
tangxifan
|
889bc8dbe8
|
add more test cases about LUT design and deploy to CI
|
2020-06-11 19:31:02 -06:00 |
|
tangxifan
|
889f179ce7
|
add local encoder test case
|
2020-06-11 19:31:01 -06:00 |
|
tangxifan
|
98a658a013
|
bug fixed in routing_test.v. Deployed to regression tests
|
2020-06-11 19:31:01 -06:00 |
|
tangxifan
|
6dd8d347e1
|
try to deploy microbenchmark test_mode_low but fail due to .v port mismatch with .blif
|
2020-06-11 19:31:01 -06:00 |
CHARAS SAMY
|
f6cea1e17c
|
Added test_mode_low benchmark
|
2020-06-11 19:31:01 -06:00 |
|
CHARAS SAMY
|
3c781b18d3
|
Added routing benchmark
|
2020-06-11 19:31:01 -06:00 |
|
tangxifan
|
42cede37fa
|
add testcases on generate fabric/testbench only
|
2020-06-11 19:31:01 -06:00 |
|
tangxifan
|
9bf91bd92a
|
start testing mcnc_big20 using OpenFPGA tasks
|
2020-06-11 19:30:55 -06:00 |
ganeshgore
|
c31b20dc91
|
Added support for simulation setting file in the task flow
|
2020-06-11 19:28:13 -06:00 |
|
ganeshgore
|
49edeb119c
|
BugFix : Relative path for refrence benchmark fixed
|
2020-06-11 19:28:13 -06:00 |
|
ganeshgore
|
890ead91b9
|
Fixed modelsim include references
|
2020-06-11 19:28:13 -06:00 |
|
ganeshgore
|
c1b73efa62
|
Added support for simulation setting file in the task flow
|
2020-06-10 23:12:30 -06:00 |
|
ganeshgore
|
a3103f6afe
|
BugFix : Relative path for refrence benchmark fixed
|
2020-04-25 20:16:17 -06:00 |
|
ganeshgore
|
9d1b3d6865
|
Fixed modelsim include references
|
2020-04-24 21:53:57 -06:00 |
|
tangxifan
|
90f608baea
|
changing task mcnc file for debugging (temporarily now) Will be corrected later
|
2020-04-23 18:58:39 -06:00 |
|
tangxifan
|
417d534121
|
fine tune mcnc example script to run Modelsim simulations easily
|
2020-04-23 16:15:45 -06:00 |
|
tangxifan
|
df85175765
|
fine tuning on mcnc example script so that we can run run_modelsim.py --runsim
|
2020-04-22 21:44:52 -06:00 |
|
tangxifan
|
f9fcc6b471
|
tweak mcnc scripts by stop VRP to remove buffers. Now passed mcnc big20 in Verilog/Bitstream generation
|
2020-04-22 18:24:09 -06:00 |
|
tangxifan
|
726185cd5e
|
add test cases using spypad architecture
|
2020-04-22 12:56:57 -06:00 |
|
tangxifan
|
73e9006372
|
add arch file with spy pads
|
2020-04-22 12:56:09 -06:00 |
|
tangxifan
|
9fb8971281
|
add FPGA arch with spypads to portofilo
|
2020-04-22 11:12:28 -06:00 |
|
tangxifan
|
9761d13eef
|
update microbenchmark and2 module name
|
2020-04-20 13:37:39 -06:00 |
|
tangxifan
|
489ca75230
|
adapt benchmark and_latch module name to be different than benchmark and
|
2020-04-20 13:15:05 -06:00 |
|
tangxifan
|
f6b7583a2a
|
add tasks for single mode
|
2020-04-20 12:55:40 -06:00 |
|
tangxifan
|
8b03ec900f
|
fine-tune micro benchmark to fit port mapping in testbenches
|
2020-04-19 17:05:12 -06:00 |
|
tangxifan
|
e10cafe0a5
|
Critical patch on repacking about wire LUT support.
Previously, the wire LUT identification is too naive and does not consider all the cases
|
2020-04-19 16:42:31 -06:00 |
|
tangxifan
|
32ed609238
|
update micro benchmark set and regression tests using them
|
2020-04-19 12:49:07 -06:00 |
|
tangxifan
|
98878f474b
|
light change on arch file to accelerate mcnc big20 run
|
2020-04-19 12:03:31 -06:00 |
|
tangxifan
|
cc163081f5
|
recover mcnc big20 test configuration
|
2020-04-18 21:06:43 -06:00 |
|
tangxifan
|
2e3a811f4f
|
critical bug fixed in repacking. This is due to depop50% local routing where the same net may be mapped to two different pins in the same pb_graph_pin. Now we restrict the pin searching. But in long term, we should sync the pb_route results to post routing results
|
2020-04-18 21:04:46 -06:00 |
|
tangxifan
|
f76a3090c4
|
add mcnc big20 test cases and start debugging
|
2020-04-18 19:25:16 -06:00 |
|
tangxifan
|
95863e996a
|
minor update on arch to use auto layout sizing
|
2020-04-18 18:43:56 -06:00 |
|
tangxifan
|
2f3a36ee81
|
update timing and rename the arch file
|
2020-04-18 18:39:47 -06:00 |
|
tangxifan
|
7ce34be175
|
update sample architecture timing
|
2020-04-17 22:06:06 -06:00 |
|
tangxifan
|
2ea4b8a2a2
|
add more flagship architectures
|
2020-04-17 19:12:27 -06:00 |
|
tangxifan
|
2ffd174e6a
|
fixed a bug in single mode FPGA; add arch to regression test; deploy full testbench verification on Travis CI
|
2020-04-15 15:48:33 -06:00 |
|
tangxifan
|
032ebc29e6
|
Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
|
2020-04-15 12:53:20 -06:00 |
|
tangxifan
|
1e742a3676
|
add test case on auto-check test benches
|
2020-04-15 12:52:52 -06:00 |
|
ganeshgore
|
689c4a3e19
|
BugFix: The filename in the previous commit
|
2020-04-15 12:44:22 -06:00 |
|
tangxifan
|
46fe1e84ce
|
Merge branch 'dev' into ganesh_dev
|
2020-04-15 12:27:51 -06:00 |
|
ganeshgore
|
7f37bf1441
|
Added formal verification support to fpga_flow script
|
2020-04-15 12:24:51 -06:00 |
|
tangxifan
|
7ba3e27371
|
add duplicated_grid_pin test case to Travis CI
|
2020-04-12 20:10:51 -06:00 |
|
tangxifan
|
e78643f108
|
add flatten routing test case to Travis CI
|
2020-04-12 20:06:40 -06:00 |
|
tangxifan
|
59ea0a6ad5
|
add implicit verilog test case to Travis CI
|
2020-04-12 20:00:20 -06:00 |
|
tangxifan
|
23aef96d3a
|
add behavioral verilog test case to Travis CI
|
2020-04-12 19:55:47 -06:00 |
|
tangxifan
|
11e9014542
|
add notes about debugging the aib FPGA
|
2020-04-12 19:07:53 -06:00 |
|
tangxifan
|
a614e5aad9
|
add long adder chain to Travis CI
|
2020-04-12 15:43:19 -06:00 |
|
tangxifan
|
f71a85a1d4
|
add test cases on different routing multiplexer circuit designs to Travis CI
|
2020-04-12 15:39:45 -06:00 |
|
tangxifan
|
214d98fbcd
|
add register chain and scan chain to Travis CI
|
2020-04-12 15:28:22 -06:00 |
|
tangxifan
|
148cc74d6a
|
add io test cases to Travis CI
|
2020-04-12 15:01:47 -06:00 |
|
tangxifan
|
da5af8f0e0
|
try to add aib test case. bug found
|
2020-04-12 14:54:45 -06:00 |
|
tangxifan
|
28cb412359
|
add test case of wide BRAM 16k to Travis CI
|
2020-04-12 14:37:08 -06:00 |
|
tangxifan
|
5d665aa04b
|
reshape bram test case
|
2020-04-12 14:32:09 -06:00 |
|
tangxifan
|
600a48edc7
|
add test case of BRAM to Travis CI
|
2020-04-12 14:27:05 -06:00 |
|
tangxifan
|
2444752de8
|
add untileable test case to Travis CI
|
2020-04-12 14:08:24 -06:00 |
|
tangxifan
|
d806ad3148
|
add testcases using openfpga_shell in openfpga_flow
|
2020-04-12 12:54:21 -06:00 |
|
tangxifan
|
68fd296e14
|
add more test vpr architecture to regression tests
|
2020-04-12 12:49:16 -06:00 |
|
ganeshgore
|
80bdb41df6
|
Updated task file to run formal verification
|
2020-04-11 18:30:21 -06:00 |
|
tangxifan
|
49ddbf98c3
|
add more testing architecture to openfpga_flow
|
2020-04-11 18:01:09 -06:00 |
|
tangxifan
|
130b78ca74
|
update arch in openfpga_flow
|
2020-04-11 18:00:37 -06:00 |
|
ganeshgore
|
f6b3c5854a
|
Bugfix :
+ OpenFPGA template variables update
+ Default path for the verilog netlist
|
2020-04-11 16:45:22 -06:00 |
|
ganeshgore
|
8ea272dc2c
|
Patched the OpenFPGA shell execution bug
|
2020-04-08 21:28:14 -06:00 |
|
ganeshgore
|
583a4d8767
|
Fixed bug in openfpga_flow script
|
2020-04-08 12:04:08 -06:00 |
|
ganeshgore
|
e1db4df744
|
Created task for FPGA shell run
|
2020-04-06 00:35:07 -06:00 |
|
ganeshgore
|
ea4122a8a4
|
Updated openfpga_flow and task file to support sheel run
|
2020-04-06 00:34:36 -06:00 |
|
ganeshgore
|
7f98ecc8a6
|
OpenFPGA shell run test script template
|
2020-04-06 00:32:43 -06:00 |
|
ganeshgore
|
eb3b02277a
|
Added XML and benchmarks for testing
|
2020-04-06 00:32:06 -06:00 |
|
ganeshgore
|
77f7e13ba7
|
Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
|
2020-04-05 20:59:10 -06:00 |
|
ganeshgore
|
d1d3446568
|
backedup partial upgrade for fpga_flow script
|
2020-04-05 11:36:24 -06:00 |
|
tangxifan
|
2f38b5cbc2
|
Merge branch 'refactoring' into dev
|
2020-03-08 16:23:20 -06:00 |
|
tangxifan
|
b219b096ee
|
hotfix on removing dangling inputs from GSB, which are CLB direct output
|
2020-03-08 13:54:49 -06:00 |
AurelienUoU
|
c51001c853
|
Add compilation verification task in openfpga_flow
|
2020-01-23 13:13:23 -07:00 |
|
ganeshgore
|
cd69f1870d
|
Merge remote-tracking branch 'origin/ganesh_dev' into dev
|
2020-01-23 10:07:36 -07:00 |
|
ganeshgore
|
46bb5ef9d0
|
Added disp option in openfpga_flow, Default is --nodisp
|
2020-01-23 10:04:38 -07:00 |
|
AurelienUoU
|
85c9f26a9f
|
Update documentation about cmake version and graphical interface
|
2020-01-22 20:46:49 -07:00 |
|
ganeshgore
|
f0bed1244c
|
Added blif file folding before VPR run
|
2020-01-09 16:50:34 -07:00 |
|
ganeshgore
|
74b650e9e1
|
Added fpga_x2p_duplicate_grid_pin option
|
2019-12-30 12:25:28 -07:00 |
|
ganeshgore
|
d1e260f54f
|
Spice related option added
|
2019-12-30 12:16:04 -07:00 |
|
tangxifan
|
ef9ed2ccbc
|
added duplicate_grid_pin test case
|
2019-12-26 15:08:31 -07:00 |
|
AurelienUoU
|
09fd2afa9c
|
Adding heterogeneous synthesis requirements
|
2019-12-03 16:09:26 -07:00 |
|
AurelienUoU
|
32176eb352
|
Adding EPFL benchmark task for openfpga_flow
|
2019-12-03 14:31:53 -07:00 |
|
AurelienUoU
|
2f14716f13
|
Adding DPRAM behavioural Verilog netlist and its TB
|
2019-12-03 13:58:20 -07:00 |
|
tangxifan
|
96733f9ea8
|
add minor comments in task file for modelsim regression tests
|
2019-11-16 22:34:03 -07:00 |
|
Ganesh Gore
|
3f235a16f9
|
Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
|
2019-11-16 19:14:34 -07:00 |
|
Ganesh Gore
|
6bb11918dc
|
Updated modelsim and collected result
|
2019-11-16 19:10:04 -07:00 |
|
tangxifan
|
a13f406918
|
tweaking mcnc_big20 task run for modelsim
|
2019-11-16 18:00:55 -07:00 |
|
Ganesh Gore
|
00ec36c1af
|
Added Modelsim error check in log
|
2019-11-16 13:18:13 -07:00 |
|
Ganesh Gore
|
373dbe0718
|
First draft for multithreaded Modelsim simulation
|
2019-11-16 01:06:09 -07:00 |
|
Ganesh Gore
|
f05aede868
|
Added task support for modelsim script
|
2019-11-15 23:23:15 -07:00 |
|
Ganesh Gore
|
f52eaef622
|
Updated flow script and skipped travis upload on failure test setup.
|
2019-11-15 14:35:15 -07:00 |
|
tangxifan
|
4df6402241
|
add python script for batch simulations
|
2019-11-15 14:23:03 -07:00 |
|
tangxifan
|
d391983e8c
|
passing regression test on dpram benchmarks
|
2019-11-07 14:57:46 -07:00 |
|
tangxifan
|
56b4ee008e
|
add test for heterogeneous FPGA and fix bugs
|
2019-11-06 17:45:11 -07:00 |
|
tangxifan
|
4ea5756be6
|
bug fixed for std cell MUX2 architecture and add the case to regression tests
|
2019-11-06 16:06:47 -07:00 |
|
tangxifan
|
09eb373a6e
|
bug fixing for autocheck top testbench where clock port is not default names
|
2019-11-06 12:21:20 -07:00 |
|
tangxifan
|
00280b835e
|
reorganize regression tests
|
2019-11-05 16:31:42 -07:00 |
|
tangxifan
|
7952d134b9
|
add tree-like mux test case to regression test
|
2019-11-05 16:24:39 -07:00 |
|
tangxifan
|
a308a13d7c
|
use prefix instead of lib_name when building modules, then use lib_name for standard cell modules
|
2019-11-05 15:41:59 -07:00 |
|
tangxifan
|
0ec465d4e1
|
refactoring auto-check top Verilog testbench
|
2019-11-03 17:41:29 -07:00 |
|
tangxifan
|
dc241e6c03
|
add explicit port mapping support in testbenches; remove dangling ports in benchmarks
|
2019-11-02 23:03:47 -06:00 |
|
Ganesh Gore
|
a880802803
|
Bug Fix: Corrected read VPR stat filename
|
2019-11-01 20:51:05 -06:00 |
|
tangxifan
|
e2b042c61c
|
Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into refactoring
|
2019-11-01 18:27:27 -06:00 |
|
Ganesh Gore
|
370a5ed408
|
Bug Fix: shifter ff.v include path to tcl script
|
2019-11-01 18:22:40 -06:00 |
|
Ganesh Gore
|
595d2d3070
|
Simple argument shuffle
|
2019-11-01 18:21:26 -06:00 |
|
Ganesh Gore
|
27005d6640
|
Added Modelsim Python Script
|
2019-11-01 18:20:40 -06:00 |
|
tangxifan
|
49bfb3223c
|
add compact routing to regression test
|
2019-11-01 10:53:47 -06:00 |
|
tangxifan
|
531cc064fc
|
bug fixing for formal top-level testbench
|
2019-11-01 10:47:40 -06:00 |
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Ganesh Gore
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da0778e813
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Merge remote-tracking branch 'lnis_origin/refactoring' into ganesh_dev
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2019-11-01 00:46:34 -06:00 |
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tangxifan
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d709868463
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adding more regression tests which is quick run but very helpful for debugging
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2019-10-31 20:17:40 -06:00 |
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tangxifan
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a6a3e7c36b
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adding mcnc_big20 to regression test
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2019-10-31 19:31:27 -06:00 |
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Ganesh Gore
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81180939ca
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Bug fix: Missing exit_if_fail flag in fpga_flow script
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2019-10-31 09:56:57 -06:00 |
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tangxifan
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5531422186
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update regression test with no-explicit port mapping cases
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2019-10-30 19:37:06 -06:00 |
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tangxifan
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55fbd72293
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many bugs have been fixed
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2019-10-30 15:50:42 -06:00 |
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tangxifan
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4398cffaaa
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single mode is working, multi-mode is under debugging
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2019-10-29 22:32:36 -06:00 |
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tangxifan
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10491c4291
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bring single mode test case online with bug fixing
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2019-10-28 17:04:10 -06:00 |