92d2d2d849
add fabric bitstream XML writer
2020-07-26 21:00:57 -06:00
a3d22c56e3
bug fix in FPGA-SPICE
2020-07-24 19:51:32 -06:00
fd3e947c6d
update FPGA_SPICE to support max width for transistors and multi-bin
2020-07-24 17:52:31 -06:00
73e2b857a3
add buffer support to FPGA-SPICE
2020-07-24 15:54:18 -06:00
2603836111
split logical tile netlists to keep good Verilog hierarchy
2020-07-24 12:53:21 -06:00
be5966475e
formulate file name, module name and instance name to be consistent
2020-07-24 12:23:27 -06:00
22159531c5
bug fix in power gating support of FPGA-Verilog
2020-07-22 20:21:38 -06:00
a4a38f8156
support multi-bit power gate ports in FPGA-SPICE
2020-07-22 20:04:39 -06:00
f573fa3ee0
move check codes on power gate ports to libarchopenfpga
...
Try to report errors to users as early as possible
2020-07-22 18:47:12 -06:00
97cca72590
add spice support on power gated inverters
2020-07-22 18:21:11 -06:00
b5fd6aa859
add inverter subckt writer to FPGA-SPICE
2020-07-17 13:01:08 -06:00
eb070694b5
fine-tune on fast configuration for configuration chain and test case for tape-out-ish architecture
2020-07-15 17:52:41 -06:00
66a50742fc
use configuration chain in the k4k4 test case to speed up CI
2020-07-15 11:56:11 -06:00
3f14fe62c7
add fast configuration support for configuration chain protocol
2020-07-15 11:44:23 -06:00
1b55dfb441
hotfix on treating the dangling ports in pb_graph for analysis SDC generator
2020-07-09 23:28:42 -06:00
62fd0947f5
using a unified string to replace multi net names to save memory of bitstream database
2020-07-08 16:28:20 -06:00
66e5e141a1
improve fabric key loader to reduce runtime
2020-07-07 10:19:34 -06:00
824b56f14c
fabric key can now accept instance name only; decoders are no longer part of the key
2020-07-06 16:42:33 -06:00
462fc0d04e
add spice transistor wrapper writer
2020-07-05 14:50:29 -06:00
b38ee0e8be
add spice writer functions
2020-07-05 13:58:05 -06:00
81171a8f97
start transplanting FPGA-SPICE
2020-07-05 12:10:12 -06:00
1ad6e8292a
move constants from verilog domain to common so that FPGA-SPICE can share
2020-07-05 11:39:46 -06:00
7c2a0a6ad2
streamline fabric verilog options
2020-07-05 11:28:14 -06:00
83e26adf90
add module usage types for future FPGA-SPICE development
2020-07-04 22:33:54 -06:00
4f8260a7ba
remove obselete codes and update regression tests
2020-07-04 17:31:34 -06:00
033c92c365
precisely reserve memory for child blocks in bitstream manager
2020-07-03 22:47:21 -06:00
46f038c829
bug fix in grid config block allocation
2020-07-03 20:46:04 -06:00
f040fc78a9
now reserve blocks in bitstream manager can accurately capture the size
2020-07-03 20:06:12 -06:00
8067a13346
bug fix for memory bank due to encoding bl/wl addresses in fabric bitstream
2020-07-03 15:56:20 -06:00
2a9377b3f4
use encoded address in storage of fabric bitstream to save memory
2020-07-03 15:12:29 -06:00
1f38e17111
bug fix for naming conflicts in mux local encoder and architecture decoders
2020-07-03 14:12:13 -06:00
70d9678578
reserve child block in bistream manager
2020-07-03 14:04:10 -06:00
2783fda344
use index range instead of vector for block bitstream
2020-07-03 11:42:38 -06:00
6ea857ae6c
use fast method to inquire number of bits and blocks in bitstream databases
2020-07-03 10:55:25 -06:00
7ca1a5bdc1
Fabric bitstream now allocates vectors in conditions for memory efficiency
2020-07-03 10:17:03 -06:00
8a45e48a1c
minor fix
2020-07-02 22:27:48 -06:00
246b4d5ac6
reserve block bits to save memory
2020-07-02 21:52:32 -06:00
dee4be96af
reserve all the input/output net storage in bitstream manager
2020-07-02 19:17:34 -06:00
f97e3bfba6
add timer to openfpga shell
2020-07-02 18:02:33 -06:00
81c9fcb7c0
bug fix when optimizing the fabric bitstream data structure
2020-07-02 16:41:32 -06:00
adee87569d
enable fast bitstream building by creating a frame view of fabric
2020-07-02 16:25:36 -06:00
9608cefa86
remove id vector in fabric bitstream database and replace with more memory efficient implementation
2020-07-02 16:08:50 -06:00
9f19c36a89
use char in fabric bitstream to save memory footprint
2020-07-02 15:56:50 -06:00
405824081b
reserve configuration blocks and bits in bitstream manager builder to be memory efficient
2020-07-02 15:28:52 -06:00
b85af57971
optimizing fabric bitsteream memory footprint
2020-07-02 12:39:18 -06:00
ac22ba28e4
add config protocol type information to simulation ini file
2020-07-02 12:26:59 -06:00
81ecfa3197
add comments to clarify how to select CB ports when connecting to SBs at the top level
2020-07-01 14:44:40 -06:00
0a3c746fb1
now split CB module bus ports into lower/upper parts
2020-07-01 14:37:13 -06:00
cb2baed257
bug fix in simulation ini GPIO width
2020-07-01 13:39:12 -06:00
b74dde919d
add additional information in the simulation ini file for UVM
2020-07-01 13:07:39 -06:00
e688ca1388
update fabric bitstream writer to support various configuration protocols
2020-07-01 11:54:28 -06:00
1015880d0e
use easy-to-access net look up in switch block module builder
2020-06-30 18:15:41 -06:00
05187f8aa4
use typedef to short the module pin information
2020-06-30 18:07:22 -06:00
2e7684b746
adapt bus ports in connection block module builder
2020-06-30 17:50:53 -06:00
2ef083c49d
adapt SB module builder to use bus ports
2020-06-30 16:02:40 -06:00
f023652ac4
keep optimizing memory footprint of module manager by using net terminal storage
2020-06-30 14:18:05 -06:00
f49cabeeda
optimize memory efficiency for module net id storage
2020-06-30 11:33:06 -06:00
23bcad0678
use more robust net builder in inter tile connections
2020-06-30 10:49:17 -06:00
025d4a3599
use efficient net builder in top module connection builder
2020-06-29 23:28:26 -06:00
e7d5736269
add profile time to top module builder for better spot on runtime/memory overhead sources
2020-06-29 23:17:03 -06:00
57e6c84252
add reserve net sources and sinks to module manager
2020-06-29 22:49:11 -06:00
66746f69da
optimizing memory efficiency by reserving nets in module manager
2020-06-29 21:27:43 -06:00
e9937954f2
optimizing the constant writing in Verilog for single bits
2020-06-29 12:29:25 -06:00
9d32a5b81f
add alias name support for fabric key
2020-06-27 14:59:53 -06:00
ebf5636e7b
add verbose output to edge sorting for GSBs
2020-06-26 17:10:51 -06:00
aded675633
rename files in fpga bitstream library to be consistent with conventions
2020-06-21 13:06:39 -06:00
d526f08782
deploy bitstream reader in openfpga shell
2020-06-20 18:48:19 -06:00
675a59ecb8
Move fpga_bitstream to the libopenfpga library and add XML reader
2020-06-20 18:25:17 -06:00
5d79a3f69f
critical bug fixed when annotating the routing results.
...
Add previous node check. This is due to that some loops between SB/CBs may exist
when routing congestion is high, which leads to same nets appear in the inputs
of a routing multiplexer. Actually one of them is driven by the other as a downstream node
Using previous node check can identify which one to pick
2020-06-17 11:17:57 -06:00
4f7e8020a8
minor fix on the format of arch bitstream writer
2020-06-17 00:08:28 -06:00
b91c30191a
add input and output net echo in arch bitstream database
2020-06-17 00:04:55 -06:00
19c0b57df6
ignore invalid nets when decoding bitstream
2020-06-16 22:26:36 -06:00
9d0e002532
echo path in architecture bitstream database
2020-06-16 21:29:45 -06:00
559564c333
Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
2020-06-12 17:31:14 -06:00
a5055e9d26
add support about loading external fabric key
2020-06-12 13:03:11 -06:00
9dbf536306
add shuffled configurable children support for top module
2020-06-12 11:16:53 -06:00
cf9c3b0f44
add write fabric to test cases
2020-06-12 10:50:23 -06:00
3499b4d3e7
add fabric key writer for top-level module
2020-06-12 10:41:34 -06:00
278acee216
bug fix for 'build_fabric' command
2020-06-11 23:59:24 -06:00
9167b288b6
add options for fabric key
2020-06-11 21:50:46 -06:00
8a4ec85c39
add configurable children-related methods to module manager
2020-06-11 21:44:25 -06:00
58807bfcb3
remove simulation settings from openfpga arch data structure
2020-06-11 19:31:16 -06:00
96b58dfdbb
use new simulation setting command in openfpga shell
2020-06-11 19:31:15 -06:00
4a2f6dfae2
add read/write simulation setting commands to openfpga shell
2020-06-11 19:31:15 -06:00
3c10af7f2b
bug fixed in memory bank configuration protocol which is due to the wrong Verilog port merging algorithm
2020-06-11 19:31:14 -06:00
8267dad8ef
add decoder support for Z signals
2020-06-11 19:31:14 -06:00
5368485bd6
keep bug fixing for memory bank configuration protocol. Reduce number of BL/WLs at the top-level
2020-06-11 19:31:14 -06:00
c85ccceac7
try bug fixing in memory bank configuration protocol
2020-06-11 19:31:14 -06:00
0bee70bee6
finish memory bank configuration protocol support.
2020-06-11 19:31:13 -06:00
e14c39e14c
update Verilog full testbench generation to support memory bank configuration protocol
2020-06-11 19:31:13 -06:00
51e1559352
add fabric bitstream support for memory bank configuration protocol
2020-06-11 19:31:13 -06:00
0e16ee1030
add configuration bus nets for memory bank decoders at top module
2020-06-11 19:31:13 -06:00
fa8dfc1fbd
add configuration protocol ports to top module for memory bank organization
2020-06-11 19:31:13 -06:00
ad7422359d
deploy compact constant values in Verilog codes
2020-06-11 19:31:13 -06:00
8ec8ac4118
bug fixed in flatten memory organization. Passed verification
2020-06-11 19:31:12 -06:00
b9aac3cbdf
updated fpga verilog testbench generation to support vanilla (standalone) configuration protocol
2020-06-11 19:31:12 -06:00
fbe05963e0
add configuration bus builder for flatten memory organization (applicable to memory bank and standalone configuration protocol)
2020-06-11 19:31:12 -06:00
d2d443a988
start developing memory bank and standalone configuration protocol
2020-06-11 19:31:12 -06:00
9e176b8d38
add fast configuration stats to log
2020-06-11 19:31:12 -06:00
8b3e79766c
add fast configuration option to fpga_verilog to speed up full testbench simulation
2020-06-11 19:31:12 -06:00
tangxifan
ganeshgore