tangxifan
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46b12611a9
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[OpenFPGA Tool] Bug fix for smart fast configuration
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2020-09-23 22:04:07 -06:00 |
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tangxifan
|
154c9045f6
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[OpoenFPGA Tool] Bug fix for smart fast configuration
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2020-09-23 21:38:42 -06:00 |
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tangxifan
|
c2c37d7555
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[OpenFPGA Tool] Add more print-out for smart fast configuration
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2020-09-23 21:34:23 -06:00 |
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tangxifan
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a3abf81afe
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[OpenFPGA Tool] Support on set signals and smart selection between reset and set signal for fast configuration
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2020-09-23 21:25:06 -06:00 |
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tangxifan
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064678fe32
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[OpenFPGA Tool] Add edge triggered attribute to circuit library definition. Better support for using CCFF in frame-based protocol
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2020-09-23 20:27:52 -06:00 |
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tangxifan
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ad881ea4dc
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[OpenFPGA Tool] Bug fix for Verilog testbench using frame-based /memory bank
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2020-09-23 18:59:25 -06:00 |
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tangxifan
|
9adeb550dc
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[OpenFPGA Tool] Bug fix in fabric builder
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2020-09-23 18:28:00 -06:00 |
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tangxifan
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6480b06a2d
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[OpenFPGA tool] Remove out-of-data test blif, architecture and scripts
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2020-09-23 11:01:53 -06:00 |
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tangxifan
|
26f1a5d9ec
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[OpenFPGA Tool] Bug fix for repacking no local routing architecture
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2020-09-21 22:22:03 -06:00 |
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tangxifan
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c6ac02d210
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[FPGA-SPICE] Add VDD/VSS ports to SPICE subckt instanciation
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2020-09-20 15:21:33 -06:00 |
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tangxifan
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544c44fe46
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[FPGA-SPICE] Add VDD and VSS port to module definition
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2020-09-20 14:58:15 -06:00 |
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tangxifan
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460fef5807
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[FPGA-Verilog] Rename files and functions to distinguish from FPGA-SPICE files and functions
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2020-09-20 12:58:55 -06:00 |
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tangxifan
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222bc86cbf
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[FPGA-SPICE] Add auxiliary SPICE netlist writer
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2020-09-20 12:53:28 -06:00 |
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tangxifan
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06c0073a3e
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[FPGA-SPICE] Add SPICE writer for fpga top module
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2020-09-20 12:43:48 -06:00 |
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tangxifan
|
1dfb3e06cc
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[FPGA-SPICE] add SPICE writer for logic blocks
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2020-09-20 12:38:24 -06:00 |
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tangxifan
|
5e78e91fdf
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[FPGA-SPICE] Add SPICE writer for routing blocks
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2020-09-20 12:27:48 -06:00 |
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tangxifan
|
0f25b52907
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[FPGA-Verilog] code format fix
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2020-09-20 12:18:22 -06:00 |
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tangxifan
|
2fae311c8e
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[FPGA-SPICE] Add SPICE writer for memories
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2020-09-20 12:14:34 -06:00 |
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tangxifan
|
f284f6f8d0
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[OPENFPGA LIBRARY] change method names to be consistent with FPGA-SPICE needs
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2020-09-20 12:03:10 -06:00 |
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tangxifan
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6801d260e9
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[FPGA-SPICE] Add SPICE writer for LUT
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2020-09-20 11:58:11 -06:00 |
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tangxifan
|
0f9fce92b2
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[FPGA-SPICE] Add SPICE writer for routing multiplexers
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2020-09-20 11:49:02 -06:00 |
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tangxifan
|
c7e3d97d1b
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[FPGA-SPICE] Add supply voltage generator
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2020-09-20 11:19:06 -06:00 |
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tangxifan
|
15df9b3893
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[FPGA-SPICE] Add SPICE subcircuit writer
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2020-09-19 23:01:44 -06:00 |
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tangxifan
|
82e137cbe4
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[FPGA-SPICE] Add wire module SPICE writer
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2020-09-19 19:31:16 -06:00 |
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tangxifan
|
1b2762386c
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[FPGA-SPICE] Bug fix for essential gate netlist writing
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2020-09-19 16:52:30 -06:00 |
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tangxifan
|
26a0a769ea
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[FPGA-SPICE] Split essential gate SPICE netlists into separated files
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2020-09-19 16:45:26 -06:00 |
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tangxifan
|
e102e30d19
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[FPGA-SPICE] Add support for AND/OR logic gate
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2020-09-19 16:20:21 -06:00 |
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tangxifan
|
482d90018f
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[FPGA-SPICE] Create generic PMOS/NMOS instanciation function
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2020-09-19 15:33:28 -06:00 |
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tangxifan
|
3262ceb276
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[FPGA-SPICE] Bug fix for pass gate transistor sizing
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2020-09-19 15:24:40 -06:00 |
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tangxifan
|
aa078f079c
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[FPGA-SPICE] Restructured SPICE netlist writers for atom circuits to avoid large cpp files
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2020-09-19 15:20:19 -06:00 |
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tangxifan
|
f5dadca884
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[FPGA-SPICE] Optimize the print-out of SPICE ports
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2020-09-19 15:07:48 -06:00 |
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tangxifan
|
51d423e4db
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[FPGA-SPICE] Add pass-gate SPICE netlist writer
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2020-09-19 14:59:00 -06:00 |
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tangxifan
|
9cfb2f52ef
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[OpenFPGA code] bug fix for fully equivalent outputs of pb_type
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2020-09-16 19:26:46 -06:00 |
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tangxifan
|
fc6bfdc7a2
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[OpenFPGA Code] Patch syntax compatibility for older gcc
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2020-09-14 18:55:21 -06:00 |
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tangxifan
|
04070fd4ca
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[Debug aid] add pb_type full hierarchy path in the error message of architecture binding checker
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2020-09-02 22:16:10 -06:00 |
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tangxifan
|
3eea12ceae
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added a new XML syntax: initial offset for physical mode pin mapping
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2020-08-19 14:43:44 -06:00 |
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tangxifan
|
f631245b2b
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bug fix and enriched debugging info print out
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2020-08-19 13:41:04 -06:00 |
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tangxifan
|
79b6ff3cb0
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relax checking for device annotation as we support multi-port during physical mode pin mapping
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2020-08-19 12:44:51 -06:00 |
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tangxifan
|
2712c354a9
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now physical pb_port binding support multiple ports
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2020-08-18 12:38:56 -06:00 |
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tangxifan
|
5d83abb2cf
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bug fix in read architecture bitstream and regression tests
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2020-07-27 19:37:05 -06:00 |
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tangxifan
|
9a7364c6e6
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bug fix in fabric bitstream XML syntax
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2020-07-27 19:22:36 -06:00 |
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tangxifan
|
35af0dd676
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streamline fabric bitstream file format
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2020-07-27 16:34:43 -06:00 |
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tangxifan
|
8dd26094b8
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add root node to fabric bitstream XML file format
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2020-07-27 15:31:08 -06:00 |
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tangxifan
|
6592db3dfe
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bug fix in calling the wrong function of write_fabric_bitstream
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2020-07-27 14:32:58 -06:00 |
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tangxifan
|
d68e77f322
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Split the writer of build_fabric_bitstream to a separated command so that users will output multiple files in different formats
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2020-07-27 14:16:33 -06:00 |
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tangxifan
|
e09eddab43
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add width syntex to the fabric bitstream file format
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2020-07-27 13:54:23 -06:00 |
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tangxifan
|
80e982fb39
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minor file format fix in fabric bitstream XML
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2020-07-26 21:35:48 -06:00 |
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tangxifan
|
b3ad04fd1e
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minor file format fix in fabric bitstream XML
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2020-07-26 21:33:47 -06:00 |
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tangxifan
|
861e346830
|
minor bug fix in fabric bitstream XML writer
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2020-07-26 21:31:08 -06:00 |
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tangxifan
|
5fb7d9fbdb
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bug fix in fabric bitstream file format writer
|
2020-07-26 21:28:45 -06:00 |