tangxifan
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98a658a013
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bug fixed in routing_test.v. Deployed to regression tests
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2020-06-11 19:31:01 -06:00 |
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tangxifan
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6dd8d347e1
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try to deploy microbenchmark test_mode_low but fail due to .v port mismatch with .blif
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2020-06-11 19:31:01 -06:00 |
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tangxifan
|
42cede37fa
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add testcases on generate fabric/testbench only
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2020-06-11 19:31:01 -06:00 |
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tangxifan
|
9bf91bd92a
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start testing mcnc_big20 using OpenFPGA tasks
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2020-06-11 19:30:55 -06:00 |
ganeshgore
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c31b20dc91
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Added support for simulation setting file in the task flow
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2020-06-11 19:28:13 -06:00 |
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ganeshgore
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c1b73efa62
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Added support for simulation setting file in the task flow
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2020-06-10 23:12:30 -06:00 |
|
tangxifan
|
90f608baea
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changing task mcnc file for debugging (temporarily now) Will be corrected later
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2020-04-23 18:58:39 -06:00 |
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tangxifan
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f9fcc6b471
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tweak mcnc scripts by stop VRP to remove buffers. Now passed mcnc big20 in Verilog/Bitstream generation
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2020-04-22 18:24:09 -06:00 |
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tangxifan
|
726185cd5e
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add test cases using spypad architecture
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2020-04-22 12:56:57 -06:00 |
|
tangxifan
|
9761d13eef
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update microbenchmark and2 module name
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2020-04-20 13:37:39 -06:00 |
|
tangxifan
|
489ca75230
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adapt benchmark and_latch module name to be different than benchmark and
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2020-04-20 13:15:05 -06:00 |
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tangxifan
|
f6b7583a2a
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add tasks for single mode
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2020-04-20 12:55:40 -06:00 |
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tangxifan
|
8b03ec900f
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fine-tune micro benchmark to fit port mapping in testbenches
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2020-04-19 17:05:12 -06:00 |
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tangxifan
|
e10cafe0a5
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Critical patch on repacking about wire LUT support.
Previously, the wire LUT identification is too naive and does not consider all the cases
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2020-04-19 16:42:31 -06:00 |
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tangxifan
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32ed609238
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update micro benchmark set and regression tests using them
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2020-04-19 12:49:07 -06:00 |
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tangxifan
|
cc163081f5
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recover mcnc big20 test configuration
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2020-04-18 21:06:43 -06:00 |
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tangxifan
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2e3a811f4f
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critical bug fixed in repacking. This is due to depop50% local routing where the same net may be mapped to two different pins in the same pb_graph_pin. Now we restrict the pin searching. But in long term, we should sync the pb_route results to post routing results
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2020-04-18 21:04:46 -06:00 |
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tangxifan
|
f76a3090c4
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add mcnc big20 test cases and start debugging
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2020-04-18 19:25:16 -06:00 |
|
tangxifan
|
2ffd174e6a
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fixed a bug in single mode FPGA; add arch to regression test; deploy full testbench verification on Travis CI
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2020-04-15 15:48:33 -06:00 |
|
tangxifan
|
1e742a3676
|
add test case on auto-check test benches
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2020-04-15 12:52:52 -06:00 |
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tangxifan
|
7ba3e27371
|
add duplicated_grid_pin test case to Travis CI
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2020-04-12 20:10:51 -06:00 |
|
tangxifan
|
e78643f108
|
add flatten routing test case to Travis CI
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2020-04-12 20:06:40 -06:00 |
|
tangxifan
|
59ea0a6ad5
|
add implicit verilog test case to Travis CI
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2020-04-12 20:00:20 -06:00 |
|
tangxifan
|
23aef96d3a
|
add behavioral verilog test case to Travis CI
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2020-04-12 19:55:47 -06:00 |
|
tangxifan
|
11e9014542
|
add notes about debugging the aib FPGA
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2020-04-12 19:07:53 -06:00 |
|
tangxifan
|
a614e5aad9
|
add long adder chain to Travis CI
|
2020-04-12 15:43:19 -06:00 |
|
tangxifan
|
f71a85a1d4
|
add test cases on different routing multiplexer circuit designs to Travis CI
|
2020-04-12 15:39:45 -06:00 |
|
tangxifan
|
214d98fbcd
|
add register chain and scan chain to Travis CI
|
2020-04-12 15:28:22 -06:00 |
|
tangxifan
|
148cc74d6a
|
add io test cases to Travis CI
|
2020-04-12 15:01:47 -06:00 |
|
tangxifan
|
da5af8f0e0
|
try to add aib test case. bug found
|
2020-04-12 14:54:45 -06:00 |
|
tangxifan
|
28cb412359
|
add test case of wide BRAM 16k to Travis CI
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2020-04-12 14:37:08 -06:00 |
|
tangxifan
|
5d665aa04b
|
reshape bram test case
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2020-04-12 14:32:09 -06:00 |
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tangxifan
|
600a48edc7
|
add test case of BRAM to Travis CI
|
2020-04-12 14:27:05 -06:00 |
|
tangxifan
|
2444752de8
|
add untileable test case to Travis CI
|
2020-04-12 14:08:24 -06:00 |
|
tangxifan
|
d806ad3148
|
add testcases using openfpga_shell in openfpga_flow
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2020-04-12 12:54:21 -06:00 |
|
ganeshgore
|
80bdb41df6
|
Updated task file to run formal verification
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2020-04-11 18:30:21 -06:00 |
|
tangxifan
|
130b78ca74
|
update arch in openfpga_flow
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2020-04-11 18:00:37 -06:00 |
|
ganeshgore
|
f6b3c5854a
|
Bugfix :
+ OpenFPGA template variables update
+ Default path for the verilog netlist
|
2020-04-11 16:45:22 -06:00 |
|
ganeshgore
|
e1db4df744
|
Created task for FPGA shell run
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2020-04-06 00:35:07 -06:00 |
AurelienUoU
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c51001c853
|
Add compilation verification task in openfpga_flow
|
2020-01-23 13:13:23 -07:00 |
|
AurelienUoU
|
85c9f26a9f
|
Update documentation about cmake version and graphical interface
|
2020-01-22 20:46:49 -07:00 |
|
tangxifan
|
ef9ed2ccbc
|
added duplicate_grid_pin test case
|
2019-12-26 15:08:31 -07:00 |
|
AurelienUoU
|
32176eb352
|
Adding EPFL benchmark task for openfpga_flow
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2019-12-03 14:31:53 -07:00 |
|
tangxifan
|
96733f9ea8
|
add minor comments in task file for modelsim regression tests
|
2019-11-16 22:34:03 -07:00 |
|
tangxifan
|
a13f406918
|
tweaking mcnc_big20 task run for modelsim
|
2019-11-16 18:00:55 -07:00 |
|
tangxifan
|
4df6402241
|
add python script for batch simulations
|
2019-11-15 14:23:03 -07:00 |
|
tangxifan
|
56b4ee008e
|
add test for heterogeneous FPGA and fix bugs
|
2019-11-06 17:45:11 -07:00 |
|
tangxifan
|
4ea5756be6
|
bug fixed for std cell MUX2 architecture and add the case to regression tests
|
2019-11-06 16:06:47 -07:00 |
|
tangxifan
|
00280b835e
|
reorganize regression tests
|
2019-11-05 16:31:42 -07:00 |
|
tangxifan
|
7952d134b9
|
add tree-like mux test case to regression test
|
2019-11-05 16:24:39 -07:00 |
|
tangxifan
|
0ec465d4e1
|
refactoring auto-check top Verilog testbench
|
2019-11-03 17:41:29 -07:00 |
|
tangxifan
|
dc241e6c03
|
add explicit port mapping support in testbenches; remove dangling ports in benchmarks
|
2019-11-02 23:03:47 -06:00 |
|
tangxifan
|
49bfb3223c
|
add compact routing to regression test
|
2019-11-01 10:53:47 -06:00 |
|
tangxifan
|
531cc064fc
|
bug fixing for formal top-level testbench
|
2019-11-01 10:47:40 -06:00 |
|
tangxifan
|
d709868463
|
adding more regression tests which is quick run but very helpful for debugging
|
2019-10-31 20:17:40 -06:00 |
|
tangxifan
|
a6a3e7c36b
|
adding mcnc_big20 to regression test
|
2019-10-31 19:31:27 -06:00 |
|
tangxifan
|
5531422186
|
update regression test with no-explicit port mapping cases
|
2019-10-30 19:37:06 -06:00 |
|
tangxifan
|
55fbd72293
|
many bugs have been fixed
|
2019-10-30 15:50:42 -06:00 |
|
tangxifan
|
10491c4291
|
bring single mode test case online with bug fixing
|
2019-10-28 17:04:10 -06:00 |
|
tangxifan
|
5cb3717433
|
add single mode test case to regression test. debugging now
|
2019-10-28 15:57:17 -06:00 |
Baudouin Chauviere
|
027272c976
|
Faster regression test
|
2019-10-05 12:10:55 -06:00 |
|
Baudouin Chauviere
|
db059af8b8
|
Lighten the regression test
|
2019-10-03 13:33:28 -06:00 |
|
Baudouin Chauviere
|
c7e1f7d90b
|
Added explicit_verilog to regression test in a clean way
|
2019-10-03 10:17:04 -06:00 |
|
Baudouin Chauviere
|
33e50bbc8c
|
fix
|
2019-10-01 16:54:16 -06:00 |
|
Baudouin Chauviere
|
7c3ab38410
|
Hot fix
|
2019-10-01 16:40:16 -06:00 |
|
AurelienUoU
|
feddcbcb21
|
Merge remote-tracking branch 'origin/dev' into heterogeneous
|
2019-09-23 11:41:38 -06:00 |
|
tangxifan
|
5efea159c5
|
Simplify part of regression test to min_route_chan_width
|
2019-09-22 11:14:33 -06:00 |
|
AurelienUoU
|
cc0bfdd548
|
Add testcase in regression test for architecture with 1 IO cell/IO block
|
2019-09-20 10:27:26 -06:00 |
|
tangxifan
|
4e7af5cdc5
|
update tileable_routing test
|
2019-09-18 15:59:32 -06:00 |
|
tangxifan
|
0f0d06aad7
|
add non-LUT intermediate buffer to test and apply minor bug fix
|
2019-09-18 15:04:51 -06:00 |
|
tangxifan
|
d7ac7d3649
|
start refactoring the switch block verilog generation
|
2019-09-17 20:40:26 -06:00 |
|
tangxifan
|
5abbfd6a0f
|
add tileable routing to regression test
|
2019-09-16 20:45:02 -06:00 |
|
tangxifan
|
f04565386f
|
refactored behavioral mux branch verilog generation
|
2019-08-27 18:39:25 -06:00 |
|
tangxifan
|
de8a6bc833
|
update regression tests
|
2019-08-26 21:00:15 -06:00 |
|
Ganesh Gore
|
7a3ff94116
|
Added blif task in travis script
|
2019-08-25 01:28:21 -06:00 |
|
Ganesh Gore
|
937ebd1b85
|
Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
|
2019-08-25 00:53:18 -06:00 |
|
Ganesh Gore
|
f558437ae1
|
Added task for vpr_blif flow
|
2019-08-25 00:23:39 -06:00 |
|
Ganesh Gore
|
89589ddc1c
|
Merge remote-tracking branch 'origin/ganesh_dev' into dev
|
2019-08-22 18:46:51 -06:00 |
|
Ganesh Gore
|
2f0acfad23
|
Updated travis to run regression task
|
2019-08-21 11:09:53 -06:00 |
|
tangxifan
|
59f1ac7310
|
add missing files and try to refactor submodule essential
|
2019-08-20 20:49:26 -06:00 |
|
tangxifan
|
5f55fc7b49
|
add missing files and developing essential gates
|
2019-08-20 20:43:46 -06:00 |
|
tangxifan
|
60e8d2b29f
|
add missing files and try to refactor submodule essential
|
2019-08-20 16:13:08 -06:00 |
|
Ganesh Gore
|
8d0153d34e
|
Added gitignore to skip run directory tracking
|
2019-08-19 19:06:01 -06:00 |
|
Ganesh Gore
|
901932a4fc
|
First draft: Working openfpga task flow
|
2019-08-16 09:44:50 -06:00 |
|
Ganesh Gore
|
b82369dd96
|
Added first draft of fpga_task script
|
2019-08-09 00:17:06 -06:00 |