tangxifan
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cadf29022e
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add README to explain the organization of regression tests
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2020-07-28 13:44:06 -06:00 |
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tangxifan
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f33422d4d7
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add regression test to track runtime on big fpga devices using practical benchmarks
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2020-07-28 12:38:42 -06:00 |
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tangxifan
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a156807559
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enrich basic regression tests to cover more critical microbenchmarks
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2020-07-27 19:47:43 -06:00 |
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tangxifan
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5d83abb2cf
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bug fix in read architecture bitstream and regression tests
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2020-07-27 19:37:05 -06:00 |
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tangxifan
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50cc4dfba3
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classify regression test to dedicated categories
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2020-07-27 17:18:59 -06:00 |
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tangxifan
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5595ee9052
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refine the test case for load external arch bitstream
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2020-07-27 16:53:29 -06:00 |
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tangxifan
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cec6bf0b6f
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add or2 microbenchmark for testing external arch bitstream
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2020-07-27 15:59:03 -06:00 |
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tangxifan
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4174fbf77d
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add load architecture bitstream test case and reorganize regression tests in category of openfpga tools
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2020-07-27 15:54:46 -06:00 |
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tangxifan
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a3eba8acbe
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update task files using the new syntax on SHELL variables
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2020-07-27 15:25:49 -06:00 |
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tangxifan
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c87f6b75b9
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add test case for FPGA-SPICE
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2020-07-24 19:12:35 -06:00 |
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tangxifan
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020154b0cd
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add depopulate crossbar test case
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2020-07-24 18:06:02 -06:00 |
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tangxifan
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ca867ea6fa
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add power gate inverter test case (full testbench)
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2020-07-22 20:09:52 -06:00 |
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tangxifan
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1a1c3885e7
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use k6 n10 in mux designs to speed up CI
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2020-07-22 13:54:09 -06:00 |
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tangxifan
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95c1fe61e1
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use k6 n8 in mux design to speed up CI
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2020-07-22 13:49:03 -06:00 |
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tangxifan
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f754c8af06
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use k6_n10 architecture to reduce CI runtime
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2020-07-22 13:45:55 -06:00 |
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tangxifan
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92c3449999
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bug fix in the regression test due to benchmark changes
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2020-07-22 13:17:05 -06:00 |
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tangxifan
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05dccadf21
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bug fix in the testcases using yosys_vpr flow
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2020-07-22 12:44:19 -06:00 |
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tangxifan
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1d36de817f
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adapt generate bitstream testcase to use yosys vpr flow
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2020-07-22 12:24:34 -06:00 |
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tangxifan
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b96cdbf857
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adapt preconfig test cases to use yosys_vpr flow
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2020-07-22 12:23:39 -06:00 |
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tangxifan
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d8804f4ec1
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deploy yosys_vpr flow to basic regression tests
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2020-07-22 12:21:59 -06:00 |
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tangxifan
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eb070694b5
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fine-tune on fast configuration for configuration chain and test case for tape-out-ish architecture
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2020-07-15 17:52:41 -06:00 |
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tangxifan
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ca90f337a7
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add fast configuration chain test case
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2020-07-15 11:56:47 -06:00 |
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tangxifan
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1e6955aaa4
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rename arch directory to be clear for its usage
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2020-07-04 19:13:28 -06:00 |
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tangxifan
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f9a2bb0490
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Reorganize task directory
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2020-07-04 19:06:41 -06:00 |
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tangxifan
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4f8260a7ba
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remove obselete codes and update regression tests
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2020-07-04 17:31:34 -06:00 |
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tangxifan
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1c634e4600
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add missing task file for generate bitstream test case
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2020-07-02 17:24:51 -06:00 |
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tangxifan
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0d81f60fd8
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add new options to openfpga task configuration files
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2020-06-12 19:48:39 -06:00 |
ganeshgore
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559564c333
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Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
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2020-06-12 17:31:14 -06:00 |
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tangxifan
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2d35848cfa
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add external key test cases
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2020-06-12 13:11:21 -06:00 |
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tangxifan
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65b387a589
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develop test cases for fabric keys
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2020-06-12 11:32:52 -06:00 |
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tangxifan
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068d9943e7
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update all the templates and regression test cases with simulation settings
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2020-06-11 19:31:16 -06:00 |
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tangxifan
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1842bf51e1
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deploy read_openfpga_simulation_setting in CI on a single test case
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2020-06-11 19:31:16 -06:00 |
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tangxifan
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c87dbc4880
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start using counter benchmark in regression tests
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2020-06-11 19:31:15 -06:00 |
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tangxifan
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3f9afea3e8
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add preconfig testbench test case for memory bank configuration protocol
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2020-06-11 19:31:14 -06:00 |
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tangxifan
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288294c23a
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add fast configuration test case for memory bank configuration protocol
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2020-06-11 19:31:14 -06:00 |
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tangxifan
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73d4c835b7
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add regression test case for memory bank
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2020-06-11 19:31:13 -06:00 |
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tangxifan
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2def059b5b
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add standalone configuration protocol to pre config test cases
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2020-06-11 19:31:12 -06:00 |
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tangxifan
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5f6a790eff
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add new test cases for the standalone memory configuration protocol
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2020-06-11 19:31:12 -06:00 |
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tangxifan
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a5138113e4
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add fast configuration testcase
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2020-06-11 19:31:12 -06:00 |
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tangxifan
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8b3e79766c
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add fast configuration option to fpga_verilog to speed up full testbench simulation
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2020-06-11 19:31:12 -06:00 |
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tangxifan
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05aa166a9e
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add preconfig testbench cases to regression tests for different configuration protocols
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2020-06-11 19:31:11 -06:00 |
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tangxifan
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827e2e6713
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file moving in regression tests
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2020-06-11 19:31:11 -06:00 |
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tangxifan
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1e73fd6def
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create configuration frame example script
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2020-06-11 19:31:10 -06:00 |
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tangxifan
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3a0d3b4e95
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fix the broken CI/regression tests due to incorrect file path
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2020-06-11 19:31:10 -06:00 |
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tangxifan
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3fa3b17061
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start testing the frame-based configuration protocol. To distinguish, rename xml to identify between configuration chain and frame-based. This should not impact the pre-config testbenches.
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2020-06-11 19:31:10 -06:00 |
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tangxifan
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fc2b09514e
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add configuration chain write to regression tests
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2020-06-11 19:31:06 -06:00 |
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tangxifan
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98fbcb5410
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add time unit test for SDC generation to CI
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2020-06-11 19:31:04 -06:00 |
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tangxifan
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4083fae41a
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add new test cases about user-defined simulation settings
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2020-06-11 19:31:03 -06:00 |
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tangxifan
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889bc8dbe8
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add more test cases about LUT design and deploy to CI
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2020-06-11 19:31:02 -06:00 |
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tangxifan
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889f179ce7
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add local encoder test case
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2020-06-11 19:31:01 -06:00 |