Commit Graph

592 Commits

Author SHA1 Message Date
tangxifan 227fb9a1a5 clean up the support for std cells 2019-11-05 17:32:05 -07:00
tangxifan aa56d95073 bug fixed for using standard cells 2019-11-05 17:19:57 -07:00
tangxifan 696d4a9522 remove useless channel wire module generation 2019-11-05 16:10:00 -07:00
tangxifan a308a13d7c use prefix instead of lib_name when building modules, then use lib_name for standard cell modules 2019-11-05 15:41:59 -07:00
tangxifan 2fbb88d25b remove legacy codes 2019-11-05 13:52:42 -07:00
tangxifan 66047e4a45 refactoring Verilog simulation flag generations 2019-11-05 13:45:11 -07:00
tangxifan 13f2d33d37 refactored fpga_define.v generation
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2019-11-05 12:41:43 -07:00
tangxifan 8ef9e994d8 rename source files to be what they are actually doing 2019-11-05 12:18:23 -07:00
tangxifan aaaf7a0d19 remove legacy codes in writing include netlists 2019-11-04 21:06:14 -07:00
tangxifan ebab0e91ef refactored include netlist writer 2019-11-04 20:55:30 -07:00
tangxifan 5d507ae8ee bug fixing in memory module generation; some work should be done to merge nets and uniquifying nets!!! 2019-11-04 18:05:50 -07:00
tangxifan 69bc858e62 bring autocheck top testbench back to simulation deck, start testing 2019-11-04 15:35:04 -07:00
tangxifan 3274a49779 fine tuning top testbench and getting ready for testing 2019-11-04 12:08:36 -07:00
tangxifan d7bbae76a4 adding stimuli to benchmark inputs in top-level testbench 2019-11-03 20:20:14 -07:00
tangxifan 3e9968d2f0 keep refactoring top-level testbench with auto-check features 2019-11-03 18:59:54 -07:00
tangxifan 1fb29df1e2 cleaning verilog file lines 2019-11-03 17:58:18 -07:00
tangxifan 0ec465d4e1 refactoring auto-check top Verilog testbench 2019-11-03 17:41:29 -07:00
tangxifan dc241e6c03 add explicit port mapping support in testbenches; remove dangling ports in benchmarks 2019-11-02 23:03:47 -06:00
tangxifan 05a830de1b bring ini writer for formality scripts back 2019-11-02 18:56:54 -06:00
tangxifan c681726124 try to enlarge write buffers in ini writer, but these codes should be fully reworked 2019-11-02 18:33:05 -06:00
tangxifan 3ad2a93539 start bring back ini writer bit by bit 2019-11-02 18:20:25 -06:00
tangxifan cb74d120e7 shadow ini writer to help debugging 2019-11-02 17:31:05 -06:00
tangxifan fc164abd49 remove unused variable in sim info writer 2019-11-02 16:35:32 -06:00
tangxifan e1a7a2895a simulation ini file name can be customizable 2019-11-02 09:59:34 -06:00
tangxifan d5d7450ce7 make simulation ini writing as an option 2019-11-02 09:46:12 -06:00
tangxifan c3db880599 adding explicit file path to simulation info writer 2019-11-02 09:21:02 -06:00
tangxifan 358e9892ac reduce some error message to warnings 2019-11-02 00:09:13 -06:00
tangxifan f70f387f9f minor tuning on ini compilation 2019-11-01 20:51:49 -06:00
tangxifan 3669a47d3b reworked the ini writer 2019-11-01 20:25:01 -06:00
tangxifan dab66b8be7 start adding auto check cpp files 2019-11-01 19:49:50 -06:00
tangxifan e2b042c61c Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into refactoring 2019-11-01 18:27:27 -06:00
Ganesh Gore a0512e40b1 Created intermidiate file for modelsim simulation 2019-11-01 18:20:00 -06:00
tangxifan 3ae841b80f start refactoring auto-check top testbench generation 2019-11-01 16:33:12 -06:00
tangxifan 531cc064fc bug fixing for formal top-level testbench 2019-11-01 10:47:40 -06:00
Ganesh Gore da0778e813 Merge remote-tracking branch 'lnis_origin/refactoring' into ganesh_dev 2019-11-01 00:46:34 -06:00
tangxifan 2dff779005 critical bug fixed for bitstream generation for offset truth tables 2019-10-31 20:16:08 -06:00
tangxifan a6a3e7c36b adding mcnc_big20 to regression test 2019-10-31 19:31:27 -06:00
tangxifan 858c1aefce try use force for Icarus 2019-10-30 19:50:34 -06:00
tangxifan 7460dc8cab pass current regression tests 2019-10-30 19:10:36 -06:00
tangxifan 55fbd72293 many bugs have been fixed 2019-10-30 15:50:42 -06:00
tangxifan 4398cffaaa single mode is working, multi-mode is under debugging 2019-10-29 22:32:36 -06:00
tangxifan 1faacfa3cf keep autocheck testbenches underwater now, bring them back when refactored. Start plugging in the new engine 2019-10-29 14:23:09 -06:00
tangxifan 7c116aac2f added Verilog generation for preconfig top module 2019-10-29 13:54:35 -06:00
tangxifan 10491c4291 bring single mode test case online with bug fixing 2019-10-28 17:04:10 -06:00
tangxifan fe005f1f56 remove legacy codes for Verilog formal verification testbench generation 2019-10-28 15:21:14 -06:00
tangxifan c047fd3cb2 plugged in the refactored formal verification Verilog testbench using random vectors 2019-10-28 15:10:29 -06:00
tangxifan ccabe4ce2a refactoring Verilog formal verification top testbench using random vectors 2019-10-28 14:45:51 -06:00
tangxifan 55eea6c4d5 rename files to be clear 2019-10-27 20:12:48 -06:00
tangxifan 35073f48cf add runtime profiling to module graph builders 2019-10-27 19:10:21 -06:00
tangxifan 2b06cfc3cf added fabric bitstream generator and fixed critical bugs in top module graph 2019-10-27 18:47:33 -06:00
tangxifan f116351831 add instance name for each pb graph node 2019-10-26 17:25:45 -06:00
tangxifan 7649d9228e fixed bugs in refactored bitstream generation 2019-10-26 16:40:14 -06:00
tangxifan 0a9c89be0b add bitstream writers and start debugging 2019-10-26 12:41:23 -06:00
tangxifan 3310bac65b refactored grid bitstream generation 2019-10-25 21:49:47 -06:00
tangxifan 4b7a9dfa63 add instance name correlation between module and bitstream generation 2019-10-25 13:06:48 -06:00
tangxifan 0b687669c8 affliate configuration bitstream to sb blocks 2019-10-25 10:42:12 -06:00
tangxifan c38513c838 add local encoder support in bitstream generation refactoring 2019-10-24 22:49:24 -06:00
tangxifan 97193794c4 correct bugs in organizing child modules in top-level module 2019-10-24 21:27:42 -06:00
tangxifan 838173f3c4 start refactoring bitstream generator 2019-10-24 21:01:11 -06:00
tangxifan 13c62fdcf8 add more methods to bitstream manager (renamed from bitstream context) 2019-10-24 15:43:29 -06:00
tangxifan f26dbfe080 add instance name for top-level modules to ease readability 2019-10-23 20:24:52 -06:00
tangxifan 2787a07f0d start refactoring bitstream generation 2019-10-23 17:34:21 -06:00
tangxifan a18f1305cd add configurable child list to module manager 2019-10-23 15:44:13 -06:00
tangxifan 12162a02bc critical bug fixing for compact routing hierarchy and top module generation 2019-10-23 14:20:04 -06:00
tangxifan fb2f003d5b add top module generation and refactored verilog generation for top module 2019-10-23 12:16:58 -06:00
tangxifan dafab3907e refactored routing module generation and verilog writing 2019-10-23 11:46:55 -06:00
tangxifan 89c8d089a3 add grid module generation 2019-10-22 16:14:11 -06:00
tangxifan 9cf8683acd add module generation for memories 2019-10-22 15:31:08 -06:00
tangxifan 3cf7950bc1 add wire module generation and simplify Verilog generation for wires 2019-10-21 20:20:34 -06:00
tangxifan c076da9bab remove redundant codes 2019-10-21 18:48:34 -06:00
tangxifan 81093f0db6 add lut module generation and simplify Verilog generation codes 2019-10-21 17:54:15 -06:00
tangxifan f002f7e30f add const 0 and 1 module Verilog generation 2019-10-21 14:17:09 -06:00
tangxifan bd37f0d542 correct bugs in decoder data port alignment to memory ports of multiplexing structure 2019-10-21 13:16:15 -06:00
tangxifan fe433f3e50 bug fixed for local encoders and module nets creation 2019-10-21 12:23:00 -06:00
tangxifan b2f57ecf81 plug in MUX module graph generation, still local encoders contain dangling net, bug fixing 2019-10-21 00:00:30 -06:00
tangxifan 520e145af2 move mux_lib to fpga_x2p_setup 2019-10-19 19:13:52 -06:00
tangxifan 04f0fbebf7 plug in module graph to feed verilog writers 2019-10-18 21:59:22 -06:00
tangxifan b1cafcdbde add missing files 2019-10-18 21:04:35 -06:00
tangxifan fbe56a06c4 add decoder module builders 2019-10-18 21:01:10 -06:00
tangxifan 7c1bce4b59 add module builders for essential gates 2019-10-18 20:41:05 -06:00
tangxifan 3b82d62d03 start developing module graph builders 2019-10-18 20:02:02 -06:00
tangxifan db38f21412 add netlist manager class 2019-10-18 17:59:03 -06:00
tangxifan 8c1158fc5c refactor memory organization at the top-level module 2019-10-18 15:33:25 -06:00
tangxifan cfec8d70ab improved refactoring on clb2clb connection by considering flexible arch 2019-10-18 11:20:09 -06:00
tangxifan 4171a674b1 refactored clb2clb direct connects for cross-column/row 2019-10-17 23:06:59 -06:00
tangxifan 190449c06f refactoring top-level module with clb2clb direct connection 2019-10-17 17:29:04 -06:00
tangxifan 945e138e62 debugged the gsb-grid connection in top module. 2019-10-15 22:02:25 -06:00
tangxifan c9d8311a93 bug fixing for grid-gsb connections in top module when using compact routing 2019-10-15 18:00:55 -06:00
tangxifan 6a13120208 rename grid modules to be clear 2019-10-15 16:28:46 -06:00
tangxifan 071757dc52 add module nets to connect grids and sbs 2019-10-15 16:08:51 -06:00
tangxifan 4b56b755f2 refactored instanciation of routing modules in top module 2019-10-14 21:06:10 -06:00
tangxifan bd6a0c6a55 refactored grid instance addition to top module 2019-10-14 17:47:10 -06:00
tangxifan f779ad7ecf bug fixing for global and gpio port wiring; start refactoring top-level module 2019-10-14 15:53:04 -06:00
tangxifan 6793c67c8d refactored pb_type and grid Verilog generation 2019-10-13 21:07:30 -06:00
tangxifan b581399761 add memory ports and nets to intermediate pb_types 2019-10-13 17:45:32 -06:00
tangxifan cab4bd6807 add gpio ports to pb_type modules 2019-10-13 16:23:22 -06:00
tangxifan 0f50251b3b add mux and associated memory modules in refactoring Verilog generation for pb_types 2019-10-13 11:11:19 -06:00
tangxifan 85644d07ae refactoring pb interc Verilog generation 2019-10-12 21:55:53 -06:00
tangxifan d1948c82eb Refactoring Verilog generation intermediate level of pb_types and SRAM port generation 2019-10-11 21:43:47 -06:00
tangxifan b3ca0d32a4 remove configuration bus naming dependency on SRAM circuit models 2019-10-11 19:47:36 -06:00