remove legacy codes
This commit is contained in:
parent
66047e4a45
commit
2fbb88d25b
|
@ -164,71 +164,6 @@ void dump_verilog_file_header(FILE* fp,
|
|||
return;
|
||||
}
|
||||
|
||||
void dump_simulation_preproc(FILE* fp,
|
||||
t_syn_verilog_opts fpga_verilog_opts,
|
||||
enum e_verilog_tb_type verilog_tb_type) {
|
||||
|
||||
if (NULL == fp) {
|
||||
vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s, LINE[%d]) FileHandle is NULL!\n",__FILE__,__LINE__);
|
||||
exit(1);
|
||||
}
|
||||
|
||||
/* To enable manualy checked simulation */
|
||||
if (TRUE == fpga_verilog_opts.print_top_testbench) {
|
||||
fprintf(fp, "`define %s 1\n", initial_simulation_flag);
|
||||
fprintf(fp, "\n");
|
||||
}
|
||||
|
||||
/* To enable auto-checked simulation */
|
||||
if (TRUE == fpga_verilog_opts.print_autocheck_top_testbench) {
|
||||
fprintf(fp, "`define %s 1\n", autochecked_simulation_flag);
|
||||
fprintf(fp, "\n");
|
||||
}
|
||||
|
||||
/* To enable pre-configured FPGA simulation */
|
||||
if (TRUE == fpga_verilog_opts.print_formal_verification_top_netlist) {
|
||||
fprintf(fp, "`define %s 1\n", formal_simulation_flag);
|
||||
fprintf(fp, "\n");
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
void dump_verilog_simulation_preproc(char* subckt_dir,
|
||||
t_syn_verilog_opts fpga_verilog_opts) {
|
||||
/* Create a file handler */
|
||||
FILE* fp = NULL;
|
||||
char* file_description = NULL;
|
||||
char* fname = NULL;
|
||||
|
||||
fname = my_strcat(subckt_dir,
|
||||
defines_verilog_simulation_file_name);
|
||||
|
||||
/* Create a file*/
|
||||
fp = fopen(fname, "w");
|
||||
|
||||
if (NULL == fp) {
|
||||
vpr_printf(TIO_MESSAGE_ERROR,
|
||||
"(FILE:%s,LINE[%d])Failure in create Verilog netlist %s",
|
||||
__FILE__, __LINE__, fname);
|
||||
exit(1);
|
||||
}
|
||||
|
||||
/* Generate the descriptions*/
|
||||
file_description = "Simulation Flags";
|
||||
dump_verilog_file_header(fp, file_description);
|
||||
|
||||
/* Dump the defines preproc flags*/
|
||||
dump_simulation_preproc(fp, fpga_verilog_opts, VERILOG_TB_TOP);
|
||||
|
||||
fclose(fp);
|
||||
|
||||
/* Free */
|
||||
my_free(fname);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
void verilog_include_defines_preproc_file(FILE* fp,
|
||||
char* verilog_dir) {
|
||||
char* temp_include_file_path = NULL;
|
||||
|
|
|
@ -15,16 +15,6 @@ void dump_verilog_preproc(FILE* fp,
|
|||
t_syn_verilog_opts fpga_verilog_opts,
|
||||
enum e_verilog_tb_type verilog_tb_type);
|
||||
|
||||
void dump_simulation_preproc(FILE* fp,
|
||||
t_syn_verilog_opts fpga_verilog_opts,
|
||||
enum e_verilog_tb_type verilog_tb_type);
|
||||
|
||||
void dump_verilog_simulation_preproc(char* subckt_dir,
|
||||
t_syn_verilog_opts fpga_verilog_opts);
|
||||
|
||||
void verilog_include_simulation_defines_file(FILE* fp,
|
||||
char* formatted_verilog_dir);
|
||||
|
||||
void verilog_include_defines_preproc_file(FILE* fp,
|
||||
char* formatted_verilog_dir);
|
||||
|
||||
|
|
Loading…
Reference in New Issue