From 2fbb88d25b355a48a9d7398eb7e2d3826085b07d Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 5 Nov 2019 13:52:42 -0700
Subject: [PATCH] remove legacy codes

---
 .../vpr/SRC/fpga_x2p/verilog/verilog_utils.c  | 65 -------------------
 .../vpr/SRC/fpga_x2p/verilog/verilog_utils.h  | 10 ---
 2 files changed, 75 deletions(-)

diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c
index 319c5447b..7fe8eedbe 100644
--- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c
+++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c
@@ -164,71 +164,6 @@ void dump_verilog_file_header(FILE* fp,
   return;
 }
 
-void dump_simulation_preproc(FILE* fp, 
-                             t_syn_verilog_opts fpga_verilog_opts,
-                             enum e_verilog_tb_type verilog_tb_type) {
-
-  if (NULL == fp) {
-    vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s, LINE[%d]) FileHandle is NULL!\n",__FILE__,__LINE__); 
-    exit(1);
-  } 
-
-  /* To enable manualy checked simulation */
-  if (TRUE == fpga_verilog_opts.print_top_testbench) {
-    fprintf(fp, "`define %s 1\n", initial_simulation_flag);
-    fprintf(fp, "\n");
-  } 
-
-  /* To enable auto-checked simulation */
-  if (TRUE == fpga_verilog_opts.print_autocheck_top_testbench) {
-    fprintf(fp, "`define %s 1\n", autochecked_simulation_flag);
-    fprintf(fp, "\n");
-  } 
-
-  /* To enable pre-configured FPGA simulation */
-  if (TRUE == fpga_verilog_opts.print_formal_verification_top_netlist) {
-    fprintf(fp, "`define %s 1\n", formal_simulation_flag); 
-    fprintf(fp, "\n");
-  } 
-
-  return;
-}
-
-void dump_verilog_simulation_preproc(char* subckt_dir,
-                                 t_syn_verilog_opts fpga_verilog_opts) {
-  /* Create a file handler */
-  FILE* fp = NULL;
-  char* file_description = NULL;
-  char* fname = NULL;
-
-  fname = my_strcat(subckt_dir, 
-                    defines_verilog_simulation_file_name);
-
-  /* Create a file*/
-  fp = fopen(fname, "w");
-
-  if (NULL == fp) {
-    vpr_printf(TIO_MESSAGE_ERROR,
-               "(FILE:%s,LINE[%d])Failure in create Verilog netlist %s",
-               __FILE__, __LINE__, fname); 
-    exit(1);
-  } 
-
-  /* Generate the descriptions*/
-  file_description = "Simulation Flags";
-  dump_verilog_file_header(fp, file_description);
-
-  /* Dump the defines preproc flags*/
-  dump_simulation_preproc(fp, fpga_verilog_opts, VERILOG_TB_TOP); 
-
-  fclose(fp);
-
-  /* Free */
-  my_free(fname);
-
-  return;
-}
-
 void verilog_include_defines_preproc_file(FILE* fp, 
                                           char* verilog_dir) {
   char* temp_include_file_path = NULL;
diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h
index 2e5ec3e9c..30a4d8863 100644
--- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h
+++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h
@@ -15,16 +15,6 @@ void dump_verilog_preproc(FILE* fp,
                           t_syn_verilog_opts fpga_verilog_opts,
                           enum e_verilog_tb_type verilog_tb_type);
 
-void dump_simulation_preproc(FILE* fp, 
-                          t_syn_verilog_opts fpga_verilog_opts,
-                          enum e_verilog_tb_type verilog_tb_type);
-
-void dump_verilog_simulation_preproc(char* subckt_dir,
-                                     t_syn_verilog_opts fpga_verilog_opts);
-
-void verilog_include_simulation_defines_file(FILE* fp, 
-                                             char* formatted_verilog_dir);
-
 void verilog_include_defines_preproc_file(FILE* fp, 
                                           char* formatted_verilog_dir);