refactored fpga_define.v generation

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vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c

@@ -264,8 +264,14 @@ void vpr_fpga_verilog(ModuleManager& module_manager,
   init_pb_types_num_iopads();
   /* init_grids_num_mode_bits(); */
 
+  /* TODO: This is the old function, which will be deprecated when refactoring is done */
+  /*
   dump_verilog_defines_preproc(src_dir_path,
                                vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts);
+   */
+
+  print_verilog_preprocessing_flags_netlist(std::string(src_dir_path),
+                                            vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts);
 
   dump_verilog_simulation_preproc(src_dir_path,
                                vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts);

vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_auxiliary_netlists.cpp

@@ -12,6 +12,7 @@
 #include "fpga_x2p_utils.h"
 #include "fpga_x2p_naming.h"
 
+#include "verilog_global.h"
 #include "verilog_writer_utils.h"
 #include "verilog_auxiliary_netlists.h"
 
@@ -104,3 +105,51 @@ void print_include_netlists(const std::string& src_dir,
   /* Close the file stream */
   fp.close();
 }
+
+/********************************************************************
+ * Print a Verilog file containing preprocessing flags
+ * which are used enable/disable some features in FPGA Verilog modules
+ *******************************************************************/
+void print_verilog_preprocessing_flags_netlist(const std::string& src_dir,
+                                               const t_syn_verilog_opts& fpga_verilog_opts) {
+
+  std::string verilog_fname = src_dir + std::string(defines_verilog_file_name);
+
+  /* Create the file stream */
+  std::fstream fp;
+  fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
+
+  /* Validate the file stream */
+  check_file_handler(fp);
+
+  /* Print the title */
+  print_verilog_file_header(fp, std::string("Preprocessing flags to enable/disable features in FPGA Verilog modules")); 
+
+  /* To enable timing */
+  if (TRUE == fpga_verilog_opts.include_timing) {
+    print_verilog_define_flag(fp, std::string(verilog_timing_preproc_flag), 1);
+    fp << std::endl;
+  } 
+
+  /* To enable timing */
+  if (TRUE == fpga_verilog_opts.include_signal_init) {
+    print_verilog_define_flag(fp, std::string(verilog_signal_init_preproc_flag), 1);
+    fp << std::endl;
+  } 
+
+  /* To enable formal verfication flag */
+  if (TRUE == fpga_verilog_opts.print_formal_verification_top_netlist) {
+    print_verilog_define_flag(fp, std::string(verilog_formal_verification_preproc_flag), 1);
+    fp << std::endl;
+  } 
+
+  /* To enable functional verfication with Icarus */
+  if (TRUE == fpga_verilog_opts.include_icarus_simulator) {
+    print_verilog_define_flag(fp, std::string(icarus_simulator_flag), 1);
+    fp << std::endl;
+  } 
+
+  /* Close the file stream */
+  fp.close();
+}
+

vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_auxiliary_netlists.h

@@ -3,10 +3,14 @@
 
 #include <string>
 #include "circuit_library.h"
+#include "vpr_types.h"
 
 void print_include_netlists(const std::string& src_dir,
                             const std::string& circuit_name,
                             const std::string& reference_benchmark_file,
                             const CircuitLibrary& circuit_lib);
 
+void print_verilog_preprocessing_flags_netlist(const std::string& src_dir,
+                                               const t_syn_verilog_opts& fpga_verilog_opts);
+
 #endif 

vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp

@@ -55,6 +55,17 @@ void print_verilog_include_netlist(std::fstream& fp,
   fp << "`include \"" << netlist_name << "\"" << std::endl; 
 }
 
+/********************************************************************
+ * Print Verilog codes to define a preprocessing flag
+ *******************************************************************/
+void print_verilog_define_flag(std::fstream& fp, 
+                               const std::string& flag_name,
+                               const int& flag_value) {
+  check_file_handler(fp);
+
+  fp << "`define " << flag_name << " " << flag_value << std::endl; 
+}
+
 /************************************************
  * Generate include files for a Verilog netlist
  ***********************************************/

vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h

@@ -26,6 +26,10 @@ void print_verilog_file_header(std::fstream& fp,
 void print_verilog_include_netlist(std::fstream& fp, 
                                    const std::string& netlist_name);
 
+void print_verilog_define_flag(std::fstream& fp, 
+                               const std::string& flag_name,
+                               const int& flag_value);
+
 void print_verilog_include_defines_preproc_file(std::fstream& fp, 
                                                 const std::string& verilog_dir);