rename source files to be what they are actually doing

This commit is contained in:
tangxifan 2019-11-05 12:18:23 -07:00
parent aaaf7a0d19
commit 8ef9e994d8
4 changed files with 5 additions and 5 deletions

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@ -61,7 +61,7 @@
#include "verilog_sdc.h"
#include "verilog_formality_autodeck.h"
#include "verilog_sdc_pb_types.h"
#include "verilog_include_netlists.h"
#include "verilog_auxiliary_netlists.h"
#include "simulation_info_writer.h"
#include "verilog_api.h"

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@ -13,7 +13,7 @@
#include "fpga_x2p_naming.h"
#include "verilog_writer_utils.h"
#include "verilog_include_netlists.h"
#include "verilog_auxiliary_netlists.h"
/********************************************************************
* Local constant variables

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@ -1,5 +1,5 @@
#ifndef VERILOG_INCLUDE_NETLISTS_H
#define VERILOG_INCLUDE_NETLISTS_H
#ifndef VERILOG_AUXILIARY_NETLISTS_H
#define VERILOG_AUXILIARY_NETLISTS_H
#include <string>
#include "circuit_library.h"

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@ -283,7 +283,7 @@ void dump_verilog_defines_preproc(char* subckt_dir,
if (NULL == fp) {
vpr_printf(TIO_MESSAGE_ERROR,
"(FILE:%s,LINE[%d])Failure in create Verilog netlist %s",
"(FILE:%s,LINE[%d]) Failure in create Verilog netlist %s",
__FILE__, __LINE__, fname);
exit(1);
}