remove legacy codes in writing include netlists
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ebab0e91ef
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@ -505,14 +505,7 @@ void vpr_fpga_verilog(ModuleManager& module_manager,
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sram_verilog_orgz_info->type);
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}
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/* TODO: this is an old function, to be shadowed */
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/*
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write_include_netlists(src_dir_path,
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chomped_circuit_name,
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*(Arch.spice) );
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*/
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/* TODO: new function: to be tested */
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/* Print a Verilog file including all the netlists that have been generated */
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print_include_netlists(std::string(src_dir_path),
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std::string(chomped_circuit_name),
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std::string(vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.reference_verilog_benchmark_file),
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@ -1,141 +0,0 @@
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// Formality runsim
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// Need to declare formality_script_name_postfix = "formality_script.tcl";
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <math.h>
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#include <time.h>
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#include <assert.h>
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#include <sys/stat.h>
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#include <unistd.h>
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/* Include vpr structs*/
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#include "util.h"
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#include "physical_types.h"
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#include "vpr_types.h"
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#include "globals.h"
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#include "rr_graph.h"
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#include "vpr_utils.h"
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#include "path_delay.h"
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#include "stats.h"
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/* Include FPGA-SPICE utils */
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#include "linkedlist.h"
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#include "fpga_x2p_utils.h"
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#include "fpga_x2p_globals.h"
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#include "fpga_x2p_naming.h"
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/* Include verilog utils */
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#include "verilog_global.h"
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#include "verilog_utils.h"
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#include "verilog_include_netlists.h"
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static
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void include_netlists_include_user_defined_verilog_netlists(FILE* fp,
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t_spice spice) {
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int i;
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/* A valid file handler*/
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if (NULL == fp) {
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vpr_printf(TIO_MESSAGE_ERROR,
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"(File:%s, [LINE%d])Invalid File Handler!\n",
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__FILE__, __LINE__);
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exit(1);
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}
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/* Include user-defined sub-circuit netlist */
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for (i = 0; i < spice.num_include_netlist; i++) {
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if (0 == spice.include_netlists[i].included) {
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assert(NULL != spice.include_netlists[i].path);
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fprintf(fp, "`include \"%s\"\n", spice.include_netlists[i].path);
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spice.include_netlists[i].included = 1;
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} else {
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assert(1 == spice.include_netlists[i].included);
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}
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}
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return;
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}
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void write_include_netlists (char* src_dir_formatted,
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char* chomped_circuit_name,
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t_spice spice){
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char* include_netlists_file_name = NULL;
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/* int output_length; */
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/* int pos; */
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FILE* fp = NULL;
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include_netlists_file_name = my_strcat(src_dir_formatted, my_strcat(chomped_circuit_name, "_include_netlists.v"));
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fp = fopen(include_netlists_file_name, "w");
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if (NULL == fp) {
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vpr_printf(TIO_MESSAGE_ERROR,
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"(FILE:%s,LINE[%d])Failure in create formality script %s",
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__FILE__, __LINE__, include_netlists_file_name);
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exit(1);
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}
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/* Print the title */
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dump_verilog_file_header(fp, "Netlists Summary");
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/* Print preprocessing flags */
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verilog_include_defines_preproc_file(fp, src_dir_formatted);
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verilog_include_simulation_defines_file(fp, src_dir_formatted);
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/*
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fprintf(fp, "`include \"%s%s%s\"\n", src_dir_formatted,
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chomped_circuit_name,
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verilog_top_postfix);
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*/
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fprintf(fp, "`include \"%s%s\"\n", src_dir_formatted,
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generate_fpga_top_netlist_name(std::string(verilog_netlist_file_postfix)).c_str());
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fprintf(fp, "\n");
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fprintf(fp, "`ifdef %s\n", verilog_formal_verification_preproc_flag);
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fprintf(fp, "\t`include \"%s%s%s\"\n", src_dir_formatted,
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chomped_circuit_name,
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formal_verification_verilog_file_postfix);
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fprintf(fp, "\t`ifdef %s\n", formal_simulation_flag);
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fprintf(fp, "\t\t`include \"%s%s%s\"\n", src_dir_formatted,
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chomped_circuit_name,
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random_top_testbench_verilog_file_postfix);
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fprintf(fp, " \t`endif\n");
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fprintf(fp, "`endif\n");
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fprintf(fp, "\n");
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fprintf(fp, "`ifdef %s\n", autochecked_simulation_flag);
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/* TODO: bring these testbench onboard when it is ready
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fprintf(fp, "`include \"%s%s%s\"\n", src_dir_formatted,
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chomped_circuit_name,
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top_testbench_verilog_file_postfix);
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fprintf(fp, "`elsif %s\n", autochecked_simulation_flag);
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*/
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fprintf(fp, "\t`include \"%s%s%s\"\n", src_dir_formatted,
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chomped_circuit_name,
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autocheck_top_testbench_verilog_file_postfix);
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fprintf(fp, "`endif\n");
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fprintf(fp, "\n");
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fprintf(fp, "`include \"%s%s%s\"\n", src_dir_formatted,
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default_rr_dir_name,
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routing_verilog_file_name);
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fprintf(fp, "`include \"%s%s%s\"\n", src_dir_formatted,
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default_lb_dir_name,
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logic_block_verilog_file_name);
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fprintf(fp, "`include \"%s%s%s\"\n", src_dir_formatted,
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default_submodule_dir_name,
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submodule_verilog_file_name);
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fprintf(fp, "`include \"%s%s%s\"\n", src_dir_formatted,
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default_submodule_dir_name,
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config_peripheral_verilog_file_name);
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init_include_user_defined_verilog_netlists(spice);
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include_netlists_include_user_defined_verilog_netlists(fp, spice);
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fclose(fp);
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return;
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}
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@ -9,8 +9,4 @@ void print_include_netlists(const std::string& src_dir,
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const std::string& reference_benchmark_file,
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const CircuitLibrary& circuit_lib);
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void write_include_netlists (char* src_dir_formatted,
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char* chomped_circuit_name,
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t_spice spice);
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#endif
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