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make simulation ini writing as an option

This commit is contained in:
tangxifan 2019-11-02 09:46:12 -06:00
parent c3db880599
commit d5d7450ce7
7 changed files with 13 additions and 0 deletions
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1
vpr7_x2p/vpr/SRC/base/OptionTokens.c
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@ -100,6 +100,7 @@ struct s_TokenPair OptionBaseTokenList[] = {
{ "fpga_verilog_report_timing_rpt_path", OT_FPGA_VERILOG_SYN_REPORT_TIMING_RPT_PATH }, /* Specify the simulator path for Verilog netlists */
{ "fpga_verilog_print_sdc_pnr", OT_FPGA_VERILOG_SYN_PRINT_SDC_PNR }, /* Specify the simulator path for Verilog netlists */
{ "fpga_verilog_print_sdc_analysis", OT_FPGA_VERILOG_SYN_PRINT_SDC_ANALYSIS }, /* Specify the simulator path for Verilog netlists */
{ "fpga_verilog_print_simulation_ini", OT_FPGA_VERILOG_SYN_PRINT_SIMULATION_INI }, /* Specify the simulator path for Verilog netlists */
/* Xifan Tang: Bitstream generator */
{ "fpga_bitstream_generator", OT_FPGA_BITSTREAM_GENERATOR }, /* turn on bitstream generator, and specify the output file */
// { "fpga_bitstream_output_file", OT_FPGA_BITSTREAM_OUTPUT_FILE }, /* turn on bitstream generator, and specify the output file */ // AA: temporarily deprecated

1
vpr7_x2p/vpr/SRC/base/OptionTokens.h
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@ -117,6 +117,7 @@ enum e_OptionBaseToken {
OT_FPGA_VERILOG_SYN_REPORT_TIMING_RPT_PATH,
OT_FPGA_VERILOG_SYN_PRINT_SDC_PNR,
OT_FPGA_VERILOG_SYN_PRINT_SDC_ANALYSIS,
OT_FPGA_VERILOG_SYN_PRINT_SIMULATION_INI,
/* Xifan Tang: Bitstream generator */
OT_FPGA_BITSTREAM_GENERATOR,
OT_FPGA_BITSTREAM_OUTPUT_FILE,

2
vpr7_x2p/vpr/SRC/base/ReadOptions.c
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@ -559,6 +559,8 @@ ProcessOption(INP char **Args, INOUTP t_options * Options) {
return Args;
case OT_FPGA_VERILOG_SYN_PRINT_SDC_ANALYSIS:
return Args;
case OT_FPGA_VERILOG_SYN_PRINT_SIMULATION_INI:
return Args;
/* Xifan TANG: Bitstream generator */
case OT_FPGA_BITSTREAM_GENERATOR:
return Args;

5
vpr7_x2p/vpr/SRC/base/SetupVPR.c
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@ -1113,6 +1113,7 @@ static void SetupSynVerilogOpts(t_options Options,
syn_verilog_opts->print_sdc_pnr = FALSE;
syn_verilog_opts->print_sdc_analysis = FALSE;
syn_verilog_opts->include_icarus_simulator = FALSE;
syn_verilog_opts->print_simulation_ini = FALSE;
/* Turn on Syn_verilog options */
if (Options.Count[OT_FPGA_VERILOG_SYN]) {
@ -1183,6 +1184,10 @@ static void SetupSynVerilogOpts(t_options Options,
syn_verilog_opts->print_sdc_analysis = TRUE;
}
if (Options.Count[OT_FPGA_VERILOG_SYN_PRINT_SIMULATION_INI]) {
syn_verilog_opts->print_simulation_ini = TRUE;
}
/* SynVerilog needs the input from spice modeling */
if (FALSE == arch->read_xml_spice) {
arch->read_xml_spice = syn_verilog_opts->dump_syn_verilog;

1
vpr7_x2p/vpr/SRC/base/vpr_api.c
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@ -211,6 +211,7 @@ void vpr_print_usage(void) {
vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_report_timing_rpt_path <path_to_generate_reports>\n");
vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_print_sdc_pnr\n");
vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_print_sdc_analysis\n");
vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_print_simulation_ini\n");
/* Xifan Tang: Bitstream generator */
vpr_printf(TIO_MESSAGE_INFO, "Bitstream Generator Options:\n");
vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_bitstream_generator\n");

1
vpr7_x2p/vpr/SRC/base/vpr_types.h
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@ -1281,6 +1281,7 @@ struct s_syn_verilog_opts {
boolean print_report_timing_tcl;
boolean print_sdc_pnr;
boolean print_sdc_analysis;
boolean print_simulation_ini;
};
/* Xifan TANG: bitstream generator */

2
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c
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@ -431,7 +431,9 @@ void vpr_fpga_verilog(ModuleManager& module_manager,
print_verilog_random_top_testbench(std::string(chomped_circuit_name), random_top_testbench_file_path,
std::string(src_dir_path), L_logical_blocks,
vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts, Arch.spice->spice_params);
}
if (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_simulation_ini) {
/* Print exchangeable files which contains simulation settings */
print_verilog_simulation_info(Arch.spice->spice_params.meas_params.sim_num_clock_cycle,
std::string(format_dir_path(chomped_parent_dir)),