From d5d7450ce7b0433a7ba4a4994b41caf945b56eb7 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 2 Nov 2019 09:46:12 -0600 Subject: [PATCH] make simulation ini writing as an option --- vpr7_x2p/vpr/SRC/base/OptionTokens.c | 1 + vpr7_x2p/vpr/SRC/base/OptionTokens.h | 1 + vpr7_x2p/vpr/SRC/base/ReadOptions.c | 2 ++ vpr7_x2p/vpr/SRC/base/SetupVPR.c | 5 +++++ vpr7_x2p/vpr/SRC/base/vpr_api.c | 1 + vpr7_x2p/vpr/SRC/base/vpr_types.h | 1 + vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c | 2 ++ 7 files changed, 13 insertions(+) diff --git a/vpr7_x2p/vpr/SRC/base/OptionTokens.c b/vpr7_x2p/vpr/SRC/base/OptionTokens.c index 78b956ce3..cdf5eef91 100644 --- a/vpr7_x2p/vpr/SRC/base/OptionTokens.c +++ b/vpr7_x2p/vpr/SRC/base/OptionTokens.c @@ -100,6 +100,7 @@ struct s_TokenPair OptionBaseTokenList[] = { { "fpga_verilog_report_timing_rpt_path", OT_FPGA_VERILOG_SYN_REPORT_TIMING_RPT_PATH }, /* Specify the simulator path for Verilog netlists */ { "fpga_verilog_print_sdc_pnr", OT_FPGA_VERILOG_SYN_PRINT_SDC_PNR }, /* Specify the simulator path for Verilog netlists */ { "fpga_verilog_print_sdc_analysis", OT_FPGA_VERILOG_SYN_PRINT_SDC_ANALYSIS }, /* Specify the simulator path for Verilog netlists */ + { "fpga_verilog_print_simulation_ini", OT_FPGA_VERILOG_SYN_PRINT_SIMULATION_INI }, /* Specify the simulator path for Verilog netlists */ /* Xifan Tang: Bitstream generator */ { "fpga_bitstream_generator", OT_FPGA_BITSTREAM_GENERATOR }, /* turn on bitstream generator, and specify the output file */ // { "fpga_bitstream_output_file", OT_FPGA_BITSTREAM_OUTPUT_FILE }, /* turn on bitstream generator, and specify the output file */ // AA: temporarily deprecated diff --git a/vpr7_x2p/vpr/SRC/base/OptionTokens.h b/vpr7_x2p/vpr/SRC/base/OptionTokens.h index 46a44ac05..706a81b24 100644 --- a/vpr7_x2p/vpr/SRC/base/OptionTokens.h +++ b/vpr7_x2p/vpr/SRC/base/OptionTokens.h @@ -117,6 +117,7 @@ enum e_OptionBaseToken { OT_FPGA_VERILOG_SYN_REPORT_TIMING_RPT_PATH, OT_FPGA_VERILOG_SYN_PRINT_SDC_PNR, OT_FPGA_VERILOG_SYN_PRINT_SDC_ANALYSIS, + OT_FPGA_VERILOG_SYN_PRINT_SIMULATION_INI, /* Xifan Tang: Bitstream generator */ OT_FPGA_BITSTREAM_GENERATOR, OT_FPGA_BITSTREAM_OUTPUT_FILE, diff --git a/vpr7_x2p/vpr/SRC/base/ReadOptions.c b/vpr7_x2p/vpr/SRC/base/ReadOptions.c index 108e9d355..54c323f9c 100644 --- a/vpr7_x2p/vpr/SRC/base/ReadOptions.c +++ b/vpr7_x2p/vpr/SRC/base/ReadOptions.c @@ -559,6 +559,8 @@ ProcessOption(INP char **Args, INOUTP t_options * Options) { return Args; case OT_FPGA_VERILOG_SYN_PRINT_SDC_ANALYSIS: return Args; + case OT_FPGA_VERILOG_SYN_PRINT_SIMULATION_INI: + return Args; /* Xifan TANG: Bitstream generator */ case OT_FPGA_BITSTREAM_GENERATOR: return Args; diff --git a/vpr7_x2p/vpr/SRC/base/SetupVPR.c b/vpr7_x2p/vpr/SRC/base/SetupVPR.c index 5b0e90004..1cb3fba67 100644 --- a/vpr7_x2p/vpr/SRC/base/SetupVPR.c +++ b/vpr7_x2p/vpr/SRC/base/SetupVPR.c @@ -1113,6 +1113,7 @@ static void SetupSynVerilogOpts(t_options Options, syn_verilog_opts->print_sdc_pnr = FALSE; syn_verilog_opts->print_sdc_analysis = FALSE; syn_verilog_opts->include_icarus_simulator = FALSE; + syn_verilog_opts->print_simulation_ini = FALSE; /* Turn on Syn_verilog options */ if (Options.Count[OT_FPGA_VERILOG_SYN]) { @@ -1183,6 +1184,10 @@ static void SetupSynVerilogOpts(t_options Options, syn_verilog_opts->print_sdc_analysis = TRUE; } + if (Options.Count[OT_FPGA_VERILOG_SYN_PRINT_SIMULATION_INI]) { + syn_verilog_opts->print_simulation_ini = TRUE; + } + /* SynVerilog needs the input from spice modeling */ if (FALSE == arch->read_xml_spice) { arch->read_xml_spice = syn_verilog_opts->dump_syn_verilog; diff --git a/vpr7_x2p/vpr/SRC/base/vpr_api.c b/vpr7_x2p/vpr/SRC/base/vpr_api.c index 7d1730883..5148daa23 100644 --- a/vpr7_x2p/vpr/SRC/base/vpr_api.c +++ b/vpr7_x2p/vpr/SRC/base/vpr_api.c @@ -211,6 +211,7 @@ void vpr_print_usage(void) { vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_report_timing_rpt_path \n"); vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_print_sdc_pnr\n"); vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_print_sdc_analysis\n"); + vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_print_simulation_ini\n"); /* Xifan Tang: Bitstream generator */ vpr_printf(TIO_MESSAGE_INFO, "Bitstream Generator Options:\n"); vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_bitstream_generator\n"); diff --git a/vpr7_x2p/vpr/SRC/base/vpr_types.h b/vpr7_x2p/vpr/SRC/base/vpr_types.h index 7b87d664a..95ae3784c 100755 --- a/vpr7_x2p/vpr/SRC/base/vpr_types.h +++ b/vpr7_x2p/vpr/SRC/base/vpr_types.h @@ -1281,6 +1281,7 @@ struct s_syn_verilog_opts { boolean print_report_timing_tcl; boolean print_sdc_pnr; boolean print_sdc_analysis; + boolean print_simulation_ini; }; /* Xifan TANG: bitstream generator */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index 74a680d6c..192e3dc63 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -431,7 +431,9 @@ void vpr_fpga_verilog(ModuleManager& module_manager, print_verilog_random_top_testbench(std::string(chomped_circuit_name), random_top_testbench_file_path, std::string(src_dir_path), L_logical_blocks, vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts, Arch.spice->spice_params); + } + if (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_simulation_ini) { /* Print exchangeable files which contains simulation settings */ print_verilog_simulation_info(Arch.spice->spice_params.meas_params.sim_num_clock_cycle, std::string(format_dir_path(chomped_parent_dir)),