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OpenFPGA
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keep autocheck testbenches underwater now, bring them back when refactored. Start plugging in the new engine

This commit is contained in:
tangxifan 2019-10-29 14:23:09 -06:00
parent 7c116aac2f
commit 1faacfa3cf
1 changed files with 2 additions and 0 deletions
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2
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_include_netlists.c
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@ -95,6 +95,7 @@ void write_include_netlists (char* src_dir_formatted,
chomped_circuit_name,
random_top_testbench_verilog_file_postfix);
fprintf(fp, " `endif\n");
/* TODO: bring these testbench onboard when it is ready
fprintf(fp, "`elsif %s\n", initial_simulation_flag);
fprintf(fp, "`include \"%s%s%s\"\n", src_dir_formatted,
chomped_circuit_name,
@ -104,6 +105,7 @@ void write_include_netlists (char* src_dir_formatted,
chomped_circuit_name,
autocheck_top_testbench_verilog_file_postfix);
fprintf(fp, "`endif\n");
*/
fprintf(fp, "`include \"%s%s%s\"\n", src_dir_formatted,
default_rr_dir_name,
routing_verilog_file_name);