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OpenFPGA
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try use force for Icarus

This commit is contained in:
tangxifan 2019-10-30 19:50:34 -06:00
parent 5531422186
commit 858c1aefce
1 changed files with 3 additions and 1 deletions
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4
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_preconfig_top_module.cpp
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@ -278,6 +278,7 @@ void print_verilog_preconfig_top_module_assign_bitstream(std::fstream& fp,
check_file_handler(fp);
print_verilog_comment(fp, std::string("----- Begin assign bitstream to configuration memories -----"));
fp << "initial begin" << std::endl;
for (const ConfigBlockId& config_block_id : bitstream_manager.blocks()) {
/* We only cares blocks with configuration bits */
@ -307,8 +308,9 @@ void print_verilog_preconfig_top_module_assign_bitstream(std::fstream& fp,
for (const ConfigBitId config_bit : bitstream_manager.block_bits(config_block_id)) {
config_data_values.push_back(bitstream_manager.bit_value(config_bit));
}
print_verilog_wire_constant_values(fp, config_data_port, config_data_values);
print_verilog_force_wire_constant_values(fp, config_data_port, config_data_values);
}
fp << "end" << std::endl;
fp << "initial begin" << std::endl;