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reworked the ini writer

This commit is contained in:
tangxifan 2019-11-01 20:25:01 -06:00
parent dab66b8be7
commit 3669a47d3b
7 changed files with 91 additions and 69 deletions
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12
libs/external/libini/src/ini.h vendored
View File

@ -126,7 +126,7 @@ const std::string endl = "\r\n";
#else
const std::string endl = "\n";
#endif
}; // namespace INIStringUtil
} // namespace INIStringUtil
template <typename T>
class INIMap
@ -321,7 +321,7 @@ inline PDataType parseLine(std::string line, T_ParseValues &parseData)
}
return PDataType::PDATA_UNKNOWN;
}
}; // namespace INIParser
} // namespace INIParser
class INIReader
{
@ -650,8 +650,8 @@ private:
public:
bool prettyPrint = false;
INIWriter(std::string const &filename)
: filename(filename)
INIWriter(std::string const &file_name)
: filename(file_name)
{
}
~INIWriter() {}
@ -709,8 +709,8 @@ private:
std::string filename;
public:
INIFile(std::string const &filename)
: filename(filename)
INIFile(std::string const &file_name)
: filename(file_name)
{
}

42
vpr7_x2p/vpr/SRC/fpga_x2p/base/simulation_utils.cpp Normal file
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@ -0,0 +1,42 @@
/********************************************************************
* This file include most utilized functions in generating simulations
* Note: function placed here MUST be generic enough for both SPICE
* and Verilog simulations!
*******************************************************************/
#include <cmath>
#include "simulation_utils.h"
/********************************************************************
* Compute the time period for the simulation
*******************************************************************/
int find_operating_phase_simulation_time(const int& factor,
const int& num_op_clock_cycles,
const float& op_clock_period,
const float& timescale) {
/* Take into account the prog_reset and reset cycles
* 1e9 is to change the unit to ns rather than second
*/
return (factor * num_op_clock_cycles * op_clock_period) / timescale;
}
/********************************************************************
* Find the the full time period of a simulation, including
* both the programming time and operating time
* This is a generic function that can be used to generate simulation
* time period for SPICE/Verilog simulators
*******************************************************************/
float find_simulation_time_period(const float &time_unit,
const int &num_prog_clock_cycles,
const float &prog_clock_period,
const int &num_op_clock_cycles,
const float &op_clock_period) {
float total_time_period = 0.;
/* Take into account the prog_reset and reset cycles */
total_time_period = (num_prog_clock_cycles + 2) * prog_clock_period + num_op_clock_cycles * op_clock_period;
total_time_period = total_time_period / time_unit;
return total_time_period;
}

15
vpr7_x2p/vpr/SRC/fpga_x2p/base/simulation_utils.h Normal file
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@ -0,0 +1,15 @@
#ifndef SIMULATION_UTILS_H
#define SIMULATION_UTILS_H
int find_operating_phase_simulation_time(const int& factor,
const int& num_op_clock_cycles,
const float& op_clock_period,
const float& timescale);
float find_simulation_time_period(const float &time_unit,
const int &num_prog_clock_cycles,
const float &prog_clock_period,
const int &num_op_clock_cycles,
const float &op_clock_period);
#endif

62
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.cpp
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@ -1,75 +1,45 @@
/***********************************/
/* Synthesizable Verilog Dumping */
/* Xifan TANG, EPFL/LSI */
/***********************************/
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
/*********************************************************************
* This function includes the writer for generating exchangeable
* information, in order to interface different simulators
********************************************************************/
#include <math.h>
#include <time.h>
#include <assert.h>
#include <sys/stat.h>
#include <unistd.h>
#include <map>
#define MINI_CASE_SENSITIVE
#include "ini.h"
/* Include vpr structs*/
#include "util.h"
#include "physical_types.h"
#include "vpr_types.h"
#include "globals.h"
#include "rr_graph.h"
#include "vpr_utils.h"
#include "path_delay.h"
#include "stats.h"
/* Include FPGA-SPICE utils */
#include "linkedlist.h"
#include "fpga_x2p_utils.h"
#include "fpga_x2p_globals.h"
#include "simulation_utils.h"
/* Include verilog utils */
#include "verilog_global.h"
#include "verilog_utils.h"
#include "simulation_info_writer.h"
// Infile Function
static float get_verilog_modelsim_simulation_time_period(const float &time_unit,
const int &num_prog_clock_cycles,
const float &prog_clock_period,
const int &num_op_clock_cycles,
const float &op_clock_period)
{
float total_time_period = 0.;
/* Take into account the prog_reset and reset cycles */
total_time_period = (num_prog_clock_cycles + 2) * prog_clock_period + num_op_clock_cycles * op_clock_period;
total_time_period = total_time_period / time_unit;
return total_time_period;
}
/***** Top-level function *****/
/*********************************************************************
* Top-level function to write an ini file which contains exchangeable
* information, in order to interface different Verilog simulators
********************************************************************/
void print_verilog_simulation_info(const int &num_operating_clock_cycles,
const std::string &verilog_dir_formatted,
const std::string &chomped_circuit_name,
const std::string &src_dir_path,
const size_t &num_program_clock_cycles,
const float &prog_clock_freq,
const float &op_clock_freq)
{
const float &op_clock_freq) {
mINI::INIStructure ini;
// std::map<char, int> units_map;
// units_map['s']=1; // units_map['ms']=1E-3; // units_map['us']=1E-6;
// units_map['ns']=1E-9; // units_map['ps']=1E-12; // units_map['fs']=1E-15;
/* Compute simulation time period */
float simulation_time_period = get_verilog_modelsim_simulation_time_period(1E-3,
num_program_clock_cycles,
1. / prog_clock_freq,
num_operating_clock_cycles,
1. / op_clock_freq);
float simulation_time_period = find_simulation_time_period(1E-3,
num_program_clock_cycles,
1. / prog_clock_freq,
num_operating_clock_cycles,
1. / op_clock_freq);
ini["SIMULATION_DECK"]["PROJECTNAME "] = "ModelSimProject";
ini["SIMULATION_DECK"]["BENCHMARK "] = chomped_circuit_name;
@ -82,4 +52,4 @@ void print_verilog_simulation_info(const int &num_operating_clock_cycles,
mINI::INIFile file("SimulationDeckInfo.ini");
file.generate(ini, true);
}
}

6
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.h
View File

@ -1,5 +1,5 @@
#ifndef VPR_API_H
#define VPR_API_H
#ifndef SIMULATION_INFO_WRITER_H
#define SIMULATION_INFO_WRITER_H
#include <string>
@ -10,4 +10,4 @@ void print_verilog_simulation_info(const int &num_operating_clock_cycles,
const size_t &num_program_clock_cycles,
const float &prog_clock_freq,
const float &op_clock_freq);
#endif
#endif

19
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp
View File

@ -17,6 +17,7 @@
/* Include VPR headers*/
/* Include FPGA-X2P headers*/
#include "simulation_utils.h"
#include "fpga_x2p_utils.h"
#include "fpga_x2p_benchmark_utils.h"
@ -245,18 +246,6 @@ void print_verilog_top_random_testbench_benchmark_instance(std::fstream& fp,
fp << std::endl;
}
/********************************************************************
* Compute the time period for the simulation
*******************************************************************/
static
int get_simulation_time(const int& num_op_clock_cycles,
const float& op_clock_period) {
/* Take into account the prog_reset and reset cycles
* 1e9 is to change the unit to ns rather than second
*/
return (MAGIC_NUMBER_FOR_SIMULATION_TIME * num_op_clock_cycles * op_clock_period) / verilog_sim_timescale;
}
/********************************************************************
* Print Verilog codes to set up a timeout for the simulation
* and dump the waveform to VCD files
@ -583,8 +572,10 @@ void print_verilog_random_top_testbench(const std::string& circuit_name,
print_verilog_top_random_testbench_check(fp, L_logical_blocks, clock_port_names);
int simulation_time = get_simulation_time(simulation_parameters.meas_params.sim_num_clock_cycle,
1./simulation_parameters.stimulate_params.op_clock_freq);
int simulation_time = find_operating_phase_simulation_time(MAGIC_NUMBER_FOR_SIMULATION_TIME,
simulation_parameters.meas_params.sim_num_clock_cycle,
1./simulation_parameters.stimulate_params.op_clock_freq,
verilog_sim_timescale);
/* Add Icarus requirement */
print_verilog_timeout_and_vcd(fp, circuit_name, simulation_time);

4
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_global.h
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@ -2,6 +2,10 @@
#define VERILOG_GLOBAL_H
/* global parameters for dumping synthesizable verilog */
#include <string>
#include "linkedlist.h"
#include "spice_types.h"
extern char* verilog_netlist_file_postfix;
extern float verilog_sim_timescale;
extern char* verilog_timing_preproc_flag; // the flag to enable timing definition during compilation