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clean up the support for std cells

This commit is contained in:
tangxifan 2019-11-05 17:32:05 -07:00
parent aa56d95073
commit 227fb9a1a5
2 changed files with 4 additions and 4 deletions
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6
vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.cpp
View File

@ -155,9 +155,9 @@ void build_essential_modules(ModuleManager& module_manager,
"Building essential (inverter/buffer/logic gate) modules...");
for (const auto& circuit_model : circuit_lib.models()) {
/* We only care about user-defined models */
if ( (false == circuit_lib.model_verilog_netlist(circuit_model).empty())
&& (false == circuit_lib.model_spice_netlist(circuit_model).empty()) ) {
/* Add essential modules upon on demand: only when it is not yet in the module library */
ModuleId module = module_manager.find_module(circuit_lib.model_name(circuit_model));
if (true == module_manager.valid_module_id(module)) {
continue;
}

2
vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph_utils.cpp
View File

@ -28,7 +28,7 @@ ModulePortId find_inverter_buffer_module_port(const ModuleManager& module_manage
VTR_ASSERT(1 == model_ports.size());
/* Find the input and output module ports */
ModulePortId module_port_id = module_manager.find_module_port(module_id, circuit_lib.port_lib_name(model_ports[0]));
ModulePortId module_port_id = module_manager.find_module_port(module_id, circuit_lib.port_prefix(model_ports[0]));
VTR_ASSERT(true == module_manager.valid_module_port_id(module_id, module_port_id));
return module_port_id;