From 227fb9a1a573d806f981d4cd0a6a4ffdf41fc994 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 5 Nov 2019 17:32:05 -0700 Subject: [PATCH] clean up the support for std cells --- .../SRC/fpga_x2p/module_builder/build_essential_modules.cpp | 6 +++--- .../fpga_x2p/module_builder/build_module_graph_utils.cpp | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.cpp index 1769b9d31..9bb471710 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.cpp @@ -155,9 +155,9 @@ void build_essential_modules(ModuleManager& module_manager, "Building essential (inverter/buffer/logic gate) modules..."); for (const auto& circuit_model : circuit_lib.models()) { - /* We only care about user-defined models */ - if ( (false == circuit_lib.model_verilog_netlist(circuit_model).empty()) - && (false == circuit_lib.model_spice_netlist(circuit_model).empty()) ) { + /* Add essential modules upon on demand: only when it is not yet in the module library */ + ModuleId module = module_manager.find_module(circuit_lib.model_name(circuit_model)); + if (true == module_manager.valid_module_id(module)) { continue; } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph_utils.cpp index 241b5f631..fc710a20d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph_utils.cpp @@ -28,7 +28,7 @@ ModulePortId find_inverter_buffer_module_port(const ModuleManager& module_manage VTR_ASSERT(1 == model_ports.size()); /* Find the input and output module ports */ - ModulePortId module_port_id = module_manager.find_module_port(module_id, circuit_lib.port_lib_name(model_ports[0])); + ModulePortId module_port_id = module_manager.find_module_port(module_id, circuit_lib.port_prefix(model_ports[0])); VTR_ASSERT(true == module_manager.valid_module_port_id(module_id, module_port_id)); return module_port_id;