riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

plugged in the refactored formal verification Verilog testbench using random vectors

This commit is contained in:
tangxifan 2019-10-28 15:10:29 -06:00
parent ccabe4ce2a
commit c047fd3cb2
2 changed files with 13 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c
View File

@ -394,7 +394,9 @@ void vpr_fpga_verilog(ModuleManager& module_manager,
my_free(top_testbench_file_path);
}
/* Create vectors for logical blocks */
/* TODO: this should be outside this function!
* Create vectors for logical blocks
*/
std::vector<t_logical_block> L_logical_blocks;
for (int i = 0; i < num_logical_blocks; ++i) {
L_logical_blocks.push_back(logical_block[i]);
@ -418,10 +420,10 @@ void vpr_fpga_verilog(ModuleManager& module_manager,
+ std::string(random_top_testbench_verilog_file_postfix);
/* FIXME: old function TO BE REMOVED */
dump_verilog_random_top_testbench(sram_verilog_orgz_info, chomped_circuit_name,
random_top_testbench_file_path.c_str(), src_dir_path,
std::string(random_top_testbench_file_path + ".bak").c_str(), src_dir_path,
vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts, *(Arch.spice));
/* TODO: remove the .bak when it is ready */
print_verilog_random_top_testbench(std::string(chomped_circuit_name), random_top_testbench_file_path + ".bak",
print_verilog_random_top_testbench(std::string(chomped_circuit_name), random_top_testbench_file_path,
std::string(src_dir_path), L_logical_blocks,
vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts, Arch.spice->spice_params);

16
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp
View File

@ -33,7 +33,7 @@ constexpr char* BENCHMARK_PORT_POSTFIX = "_bench";
constexpr char* CHECKFLAG_PORT_POSTFIX = "_flag";
constexpr char* DEFAULT_CLOCK_NAME = "clk";
constexpr char* BENCHMARK_INSTANCE_NAME = "REF_DUT";
constexpr char* FPGA_INSTANCE_NAME = "REF_DUT";
constexpr char* FPGA_INSTANCE_NAME = "FPGA_DUT";
constexpr char* ERROR_COUNTER = "nb_error";
constexpr int MAGIC_NUMBER_FOR_SIMULATION_TIME = 200;
@ -250,7 +250,7 @@ void print_verilog_top_random_testbench_benchmark_instance(std::fstream& fp,
print_verilog_comment(fp, std::string("----- Reference Benchmark Instanication -------"));
print_verilog_random_testbench_instance(fp, reference_verilog_top_name,
std::string(reference_verilog_top_name + std::string(BENCHMARK_INSTANCE_NAME)),
std::string(BENCHMARK_INSTANCE_NAME),
std::string(BENCHMARK_PORT_POSTFIX), L_logical_blocks);
print_verilog_comment(fp, std::string("----- End reference Benchmark Instanication -------"));
@ -402,8 +402,8 @@ void print_verilog_random_testbench_fpga_instance(std::fstream& fp,
print_verilog_comment(fp, std::string("----- FPGA fabric instanciation -------"));
print_verilog_random_testbench_instance(fp, circuit_name,
std::string(circuit_name + std::string(formal_verification_top_postfix)),
print_verilog_random_testbench_instance(fp, std::string(circuit_name + std::string(formal_verification_top_postfix)),
std::string(FPGA_INSTANCE_NAME),
std::string(FPGA_PORT_POSTFIX), L_logical_blocks);
print_verilog_comment(fp, std::string("----- End FPGA Fabric Instanication -------"));
@ -443,10 +443,10 @@ void print_verilog_top_random_stimuli(std::fstream& fp,
/* Creae clock stimuli */
BasicPort clock_port = generate_verilog_top_clock_port(clock_port_names);
fp << "\t" << generate_verilog_port(VERILOG_PORT_CONKT, clock_port) << " <= 1'b0;" << std::endl;
fp << "\twhile(1) begin" << std::endl;
fp << "\t\t#" << std::setprecision(2) << ((0.5/simulation_parameters.stimulate_params.op_clock_freq)/verilog_sim_timescale) << std::endl;
fp << "\t\t" << generate_verilog_port(VERILOG_PORT_CONKT, clock_port);
fp << "\t\t" << generate_verilog_port(VERILOG_PORT_CONKT, clock_port) << " <= 1'b0;" << std::endl;
fp << "\t\twhile(1) begin" << std::endl;
fp << "\t\t\t#" << std::setprecision(2) << ((0.5/simulation_parameters.stimulate_params.op_clock_freq)/verilog_sim_timescale) << std::endl;
fp << "\t\t\t" << generate_verilog_port(VERILOG_PORT_CONKT, clock_port);
fp << " <= !";
fp << generate_verilog_port(VERILOG_PORT_CONKT, clock_port);
fp << ";" << std::endl;