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start bring back ini writer bit by bit

This commit is contained in:
tangxifan 2019-11-02 18:20:25 -06:00
parent 644ca4f0a4
commit 3ad2a93539
4 changed files with 4 additions and 14 deletions
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2
.travis/script.sh
View File

@ -18,8 +18,6 @@ end_section "OpenFPGA.build"
start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}"
cd -
./vpr7_x2p/vpr/vpr ./openfpga_flow/arch/template/k4_N4_sram_chain_FC_behavioral_verilog_template.xml ./openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.blif --net_file ./openfpga_flow/benchmarks/test_modes/k4_N4/K4n4_test_vpr.net --place_file ./openfpga_flow/benchmarks/test_modes/k4_N4/K4n4_test_vpr.place --route_file ./openfpga_flow/benchmarks/test_modes/k4_N4/K4n4_test_vpr.route --full_stats --nodisp --activity_file ./openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.act --power --tech_properties ./openfpga_flow/tech/PTM_45nm/45nm.xml --fpga_x2p_compact_routing_hierarchy --fpga_verilog --fpga_verilog_dir ./verilog --fpga_verilog_print_autocheck_top_testbench K4n4_test_output_verilog.v --fpga_verilog_include_timing --fpga_verilog_explicit_mapping --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --fpga_verilog_print_sdc_pnr --fpga_verilog_print_user_defined_template --fpga_verilog_print_sdc_analysis --fpga_bitstream_generator --fpga_x2p_rename_illegal_port
echo -e "Testing single-mode architectures";
python3 openfpga_flow/scripts/run_fpga_task.py single_mode --debug --show_thread_logs
#python3 openfpga_flow/scripts/run_fpga_task.py s298

4
vpr7_x2p/vpr/CMakeLists.txt
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@ -65,13 +65,13 @@ if (ENABLE_VPR_GRAPHIC_CXX_FLAG)
libarchfpga
X11
libvtrutil
#libini
libini
readline)
else ()
target_link_libraries(libvpr
libarchfpga
libvtrutil
#libini
libini
readline)
endif()

10
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.cpp
View File

@ -5,8 +5,8 @@
#include <math.h>
#include <time.h>
#include <map>
//#define MINI_CASE_SENSITIVE
//#include "ini.h"
#define MINI_CASE_SENSITIVE
#include "ini.h"
/* Include vpr structs*/
#include "util.h"
@ -30,9 +30,7 @@ void print_verilog_simulation_info(const std::string& simulation_ini_filename,
const int& num_operating_clock_cycles,
const float& prog_clock_freq,
const float& op_clock_freq) {
/*
mINI::INIStructure ini;
*/
// std::map<char, int> units_map;
// units_map['s']=1; // units_map['ms']=1E-3; // units_map['us']=1E-6;
// units_map['ns']=1E-9; // units_map['ps']=1E-12; // units_map['fs']=1E-15;
@ -43,7 +41,6 @@ void print_verilog_simulation_info(const std::string& simulation_ini_filename,
1. / prog_clock_freq,
num_operating_clock_cycles,
1. / op_clock_freq);
/*
ini["SIMULATION_DECK"]["PROJECTNAME "] = "ModelSimProject";
ini["SIMULATION_DECK"]["BENCHMARK "] = circuit_name;
ini["SIMULATION_DECK"]["TOP_TB"] = circuit_name + std::string("_top_formal_verification_random_tb");
@ -52,7 +49,6 @@ void print_verilog_simulation_info(const std::string& simulation_ini_filename,
ini["SIMULATION_DECK"]["VERILOG_PATH "] = std::string(src_dir);
ini["SIMULATION_DECK"]["VERILOG_FILE1"] = std::string(defines_verilog_file_name);
ini["SIMULATION_DECK"]["VERILOG_FILE2"] = std::string(circuit_name + "_include_netlists.v");
*/
/* Use default name if user does not provide one */
std::string ini_fname;
@ -62,8 +58,6 @@ void print_verilog_simulation_info(const std::string& simulation_ini_filename,
ini_fname = simulation_ini_filename;
}
/*
mINI::INIFile file(ini_fname);
file.generate(ini, true);
*/
}

2
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c
View File

@ -437,7 +437,6 @@ void vpr_fpga_verilog(ModuleManager& module_manager,
if (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_simulation_ini) {
/* Print exchangeable files which contains simulation settings */
/*
print_verilog_simulation_info(std::string(vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.simulation_ini_path),
std::string(format_dir_path(chomped_parent_dir)),
std::string(chomped_circuit_name),
@ -446,7 +445,6 @@ void vpr_fpga_verilog(ModuleManager& module_manager,
Arch.spice->spice_params.meas_params.sim_num_clock_cycle,
Arch.spice->spice_params.stimulate_params.prog_clock_freq,
Arch.spice->spice_params.stimulate_params.op_clock_freq);
*/
}
if (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_autocheck_top_testbench) {