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start refactoring auto-check top testbench generation

This commit is contained in:
tangxifan 2019-11-01 16:33:12 -06:00
parent b61b81b8d8
commit 3ae841b80f
1 changed files with 25 additions and 0 deletions
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25
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_autocheck_top_testbench.h
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@ -1,3 +1,11 @@
#ifndef VERILOG_AUTOCHECK_TOP_TESTBENCH_H
#define VERILOG_AUTOCHECK_TOP_TESTBENCH_H
#include <string>
#include <vector>
#include "module_manager.h"
#include "bitstream_manager.h"
#include "circuit_library.h"
void dump_verilog_autocheck_top_testbench(t_sram_orgz_info* cur_sram_orgz_info,
char* circuit_name,
@ -6,3 +14,20 @@ void dump_verilog_autocheck_top_testbench(t_sram_orgz_info* cur_sram_orgz_info,
t_syn_verilog_opts fpga_verilog_opts,
t_spice verilog);
/*
void print_verilog_autocheck_top_testbench(const ModuleManager& module_manager,
const BitstreamManager& bitstream_manager,
const CircuitLibrary& circuit_lib,
const std::vector<CircuitPortId>& global_ports,
const std::vector<t_logical_block>& L_logical_blocks,
const vtr::Point<size_t>& device_size,
const std::vector<std::vector<t_grid_tile>>& L_grids,
const std::vector<t_block>& L_blocks,
const std::string& circuit_name,
const std::string& verilog_fname,
const std::string& verilog_dir,
const t_syn_verilog_opts& fpga_verilog_opts,
const t_spice_params& simulation_parameters);
*/
#endif