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774 Commits

Author SHA1 Message Date
tangxifan 77896379e2 [Arch] Add simulation setting for 8-clock architectures 2021-02-22 11:10:03 -07:00
tangxifan 16debe49f6 [Arch] Add more comments on the 4 clock simulation setting file 2021-02-22 11:04:34 -07:00
tangxifan 0ac75723af [Arch] Add new architecture with 8 clocks 2021-02-22 11:00:45 -07:00
tangxifan b9c2564a7e [Arch] Add VPR architecture with 5 clocks to test counter with 5 clocks 2021-02-22 10:49:21 -07:00
tangxifan bc8aa0ebc6 [Test] Remove routing test from quicklogic's flow test 2021-02-22 10:22:47 -07:00
tangxifan 2dbdc2644f [Benchmark] Remove replicate micro benchmarks 2021-02-22 10:22:19 -07:00
tangxifan 9b6b2068ee [Test] Move MCNC test to benchmark sweep test group 2021-02-22 10:18:34 -07:00
tangxifan c1f4a434e4 [Doc] Update README for the regression test tasks 2021-02-22 10:17:02 -07:00
tangxifan d6a02a985e
Merge pull request #248 from lnis-uofu/add_quicklogic_tests 
Disabling verilog testbench generation for quicklogic tests
 2021-02-22 09:02:29 -07:00
Lalit Sharma d842026672 Disabling verilog testbench generation for quicklogic tests 2021-02-21 21:58:23 -08:00
Lalit Narain Sharma be5e0cdea9
Merge pull request #241 from lnis-uofu/add_quicklogic_tests 
Adding quicklogic tests and updating the corresponding conf file to r…
 2021-02-22 09:50:26 +05:30
Lalit Sharma 576e6753f6 Removing 2 more tests which are variant of and design 2021-02-19 09:11:19 -08:00
Lalit Sharma d4c5a5655a Removing blif file as well as and2 testcase 2021-02-19 08:55:17 -08:00
Lalit Sharma 6de0954ca5 Uncommenting all benchmarks except 2 that requires multiple clocks 2021-02-19 08:40:26 -08:00
tangxifan e08ac1a41e [Test] Deploy synthesizable verilog test to CI 2021-02-18 19:37:45 -07:00
tangxifan e19fc15fec [Test] bug fix in test case 2021-02-18 19:37:45 -07:00
tangxifan affc8cbbc4 [Test] Deploy test to CI 2021-02-18 19:37:45 -07:00
tangxifan 2e88b035ed [Test] Add wire LUT repacker test case 2021-02-18 19:37:44 -07:00
tangxifan 1f097abe99 [Benchmark] Add micro benchmark for FIR filter 2021-02-18 19:37:44 -07:00
Lalit Sharma 69cdc11ea5 Uncommenting the tests that are running fine 2021-02-18 04:17:12 -08:00
tangxifan d85d6e964e
Merge pull request #227 from watcag/master 
Standard-cell flow
 2021-02-17 10:11:34 -07:00
Lalit Sharma 7ee01711c2 Merge remote-tracking branch 'origin/master' into add_quicklogic_tests 2021-02-17 00:06:59 -08:00
Lalit Sharma 44a979288b Adding quicklogic tests and updating the corresponding conf file to run them 2021-02-16 23:08:38 -08:00
tangxifan a819375f69 [Script] Bug fix on the run_fpga_flow.py script when power analysis is disabled 2021-02-16 16:53:13 -07:00
tangxifan 2c2e493739 [Test] Remove quicklogic test from basic tests 2021-02-16 12:29:10 -07:00
tangxifan 9c19e2b365 [Test] Move regression test scripts from workflow to openfpga_flow 2021-02-16 11:55:47 -07:00
Tarachand Pagarani 426b6449d8 change the test to turn off power analysis 2021-02-15 02:45:38 -08:00
Tarachand Pagarani 3a587f663a copy yosys output file in case power analysis setting is off 2021-02-15 02:36:02 -08:00
tangxifan e683e00032 [HDL] Add disclaimer for the frac_lut4_arith HDL codes 2021-02-10 14:50:11 -07:00
tangxifan 9b86f3bb85 Merge branch 'master' into dev 2021-02-09 22:40:45 -07:00
tangxifan 22e675148e [HDL] Add HDL codes for a super LUT with embedded carry logic 2021-02-09 21:13:22 -07:00
tangxifan b81b74aa7c [Arch] Patch architecture to support superLUT-related XML syntax 2021-02-09 20:23:32 -07:00
tangxifan 7dcc14d73f [Arch] Bug fix in the example arch with super LUT 2021-02-09 15:52:22 -07:00
tangxifan 3ae501a5ea [Test] Update test case to use dedicated eblif file 2021-02-09 15:51:57 -07:00
tangxifan 1712ee4edb [Benchmark] Add a dedicated eblif to test the frac lut4 arith architecture 2021-02-09 15:41:21 -07:00
Nachiket Kapre 4c7f4bd82f ahoy nice 2021-02-09 17:38:19 -05:00
tangxifan 2b51b36dd6 [Test] Now use the super LUT arch in the test case 2021-02-09 15:27:44 -07:00
tangxifan 56284059de [Test] Add a test case for a super LUT 2021-02-09 15:25:32 -07:00
tangxifan 304b26c97f [Arch] Add example architectures for superLUT circuit model 2021-02-09 15:11:12 -07:00
Nachiket Kapre 71c76df063 default to ns for time unit -- synopsys dc whines 2021-02-09 17:08:38 -05:00
Nachiket Kapre 6bb2e29f17 default to ns for time unit -- synopsys dc whines 2021-02-09 17:04:52 -05:00
Nachiket Kapre 87c69460df what is going on 2021-02-09 11:33:08 -05:00
Nachiket Kapre cc74c6268a trying fix chan width 2021-02-09 11:28:19 -05:00
Nachiket Kapre 95fe4d7dae adding dff synth 2021-02-09 10:34:54 -05:00
Nachiket Kapre b14b5f975d adding sweep for W 2021-02-09 08:48:25 -05:00
Nachiket Kapre d7967da328 bugfix in alt 2021-02-08 23:04:00 -05:00
Nachiket Kapre 485708423c no need for dff*, but need tap_buf4 2021-02-08 23:00:13 -05:00
Nachiket Kapre cf154d8bb9 no need for dff*, but need tap_buf4 2021-02-08 22:29:55 -05:00
Nachiket Kapre e14c0bf0c4 no need for dff*, but need tap_buf4 2021-02-08 22:28:42 -05:00
Nachiket Kapre 45437fbc46 no need for dff*, but need tap_buf4 2021-02-08 22:27:57 -05:00
Nachiket Kapre 853bf8af43 typos fixed; 2021-02-08 22:03:14 -05:00
Nachiket Kapre d040ba569c merge for consideration; 2021-02-08 21:29:34 -05:00
Nachiket Kapre 94f858fcde merge for consideration; 2021-02-08 21:27:01 -05:00
Nachiket Kapre 0c6d27cf7e merge for consideration; 2021-02-08 21:26:48 -05:00
Nachiket Kapre b4185f7e8c Merge branch 'master' of github.com:lnis-uofu/OpenFPGA 2021-02-08 21:11:30 -05:00
Nachiket Kapre 2344cdcabc merge 2021-02-08 21:11:28 -05:00
tangxifan 1ce94040da
Merge pull request #221 from lnis-uofu/flow_dev 
[Flow] Support multi-user environment for running task
 2021-02-08 12:43:57 -07:00
tangxifan 80a4872ba0
Merge pull request #222 from lnis-uofu/gg_cleanup 
[Flow] ACE is optional during flow script, only runs when power estimation is on
 2021-02-08 10:08:47 -07:00
Ganesh Gore ede5f8ed58 [Flow] Support multi-user enviroment for running task 2021-02-07 22:11:04 -07:00
AurelienAlacchi 00fc3d7622
Merge pull request #217 from lnis-uofu/dev 
Synchronize the out-of-date XML syntax 'disable_in_pack' with VPR upstream
 2021-02-05 09:53:28 -07:00
ganeshgore ee14c15e58
Merge pull request #212 from lnis-uofu/soft_adder_lut_support 
Support overloading LUT bitstream from attributes in .eblif file format
 2021-02-04 21:55:02 -07:00
tangxifan 8853370c60 [Script, Benchmark, Test] Now use circuit format in openfpga shell script to specify eblif file 2021-02-04 20:20:10 -07:00
tangxifan dc09c47411 [Arch] Remove packable from architecture files and replace with disable_packing 2021-02-04 18:03:56 -07:00
tangxifan 224bf6c686 Merge branch 'master' into dev 2021-02-04 17:21:15 -07:00
tangxifan 66bc370c4d [Arch] Use disable_packing in architecture library 2021-02-04 16:29:03 -07:00
tangxifan a4c266d59a [Arch] Add pack patterns for soft adders; Still fail in packing 2021-02-03 19:11:15 -07:00
Ganesh Gore 6cdc31f073 [Flow] ACE is optional duign flow script 2021-02-03 19:07:48 -07:00
tangxifan cac1160bf7 [Arch] Patch QLSOFA architecture to support carry chain pattern; Still buggy for VPR packer; Looking for a solution 2021-02-03 11:20:56 -07:00
Ganesh Gore df4a397470 [Cleanup] Removed deadcode 2021-02-03 10:35:14 -07:00
tangxifan 4c825b27b3 [Benchmark] Change to use adder lut4 to be consistent with architecture 2021-02-03 09:37:48 -07:00
tangxifan 31441c0b64 [Test] Deploy adder_8 to soft adder test 2021-02-03 09:26:38 -07:00
tangxifan 05d63567d0 [Benchmark] Use latest adder eblif file 2021-02-03 09:21:38 -07:00
Lalit Sharma ebe66dea35 Bumping up latest yosys changes related to adder tech mapping 2021-02-03 14:30:06 +05:30
tangxifan 2c06960e4f [Benchmark] Add subckt definition to micro benchmark and2.eblif 2021-02-02 15:51:16 -07:00
tangxifan 021520783b [Arch] Add dummy timing info to adder_lut4 and carry_follower model 2021-02-02 15:49:43 -07:00
tangxifan dc320182b0 [Benchmark] Bug fix in the and2 eblif to cooperate with the architecture models 2021-02-02 15:04:43 -07:00
tangxifan 8e36ed1ab6 [Test] Update task configuration to use and2 eblif 2021-02-02 15:01:15 -07:00
tangxifan 62803dc044 [Benchmark] Add eblif example for and2 benchmark 2021-02-02 14:59:31 -07:00
tangxifan 5e2847bc41 [Test] Update test case to use eblif file 2021-02-02 09:33:41 -07:00
tangxifan 39e6f62d91 [Benchmark] Use eblif in naming the adder_8 micro benchmark 2021-02-02 09:32:42 -07:00
tangxifan d3397f6936 [Script] Remove activity from bitstream setting example script 2021-02-02 09:25:36 -07:00
tangxifan 9ff5e7926b [Test] Update test case to use the adder benchmark 2021-02-02 09:24:39 -07:00
tangxifan 7f14dfbe87 [Script] Add example script to use bitstream setting 2021-02-02 09:18:08 -07:00
tangxifan 04594cb7ab [Test] Adapt bitstream annotatin file to parser's requirement 2021-02-01 17:38:36 -07:00
tangxifan 280c9620aa [Test] Add an example bitstream annotation file 2021-02-01 16:01:21 -07:00
tangxifan a6354fab7c [Arch] Decide to move external bitstream definition to a separated XML file 2021-02-01 15:57:44 -07:00
tangxifan df88e2adc0 [Arch] Add an example definition of external bitstream to openfpga arch with soft adder 2021-02-01 14:26:11 -07:00
tangxifan 10302752a7 [Arch] Bug fix in architecture. Now soft adder modes are accepted 2021-02-01 13:43:39 -07:00
tangxifan d8927e12e8 [Arch] Add soft adder operating mode to test architecture 2021-02-01 12:25:37 -07:00
tangxifan 7f0f7a1c70 [Benchmark] Add micro benchmark 8-bit adder synthesized by Quicklogic script 2021-02-01 12:05:04 -07:00
tangxifan b215b868c1 [HDL] Bug fix in HDL netlist due to port name mismatching 2021-02-01 11:35:25 -07:00
tangxifan e4abe263c3 [Arch] Bug fix 2021-02-01 11:29:27 -07:00
tangxifan fb05e1a938 [Arch] bug fix due to using openfpga cell library 2021-02-01 11:27:21 -07:00
tangxifan 940dce469a [Test] Bug fix for test case configuration 2021-02-01 11:19:47 -07:00
tangxifan a80acfb547 [Test] Add new test case to CI script 2021-02-01 11:16:12 -07:00
tangxifan af630dab1e [Test] Add soft adder test case. This is placeholder. Test arch will be elaborated 2021-02-01 10:53:38 -07:00
tangxifan 9cce411eda [Test] Add adder test cases 2021-02-01 10:42:24 -07:00
tangxifan 0eb949b85a [Arch] Now use the MUX2 cell from openfpga cell library for the QLSOFA 2021-02-01 10:34:32 -07:00
tangxifan e0e2506e32 [HDL] Remove redundant comments 2021-02-01 10:33:08 -07:00
tangxifan 39543f7945 [HDL] Add carry mux2 to cell library 2021-02-01 10:23:46 -07:00