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827 Commits

Author SHA1 Message Date
SergeyDegtyar c597c2f2ae adffs test update (equiv_opt -multiclock). div_mod test fix 2019-09-17 12:19:31 +03:00
Eddie Hung f492567c87 Oops 2019-09-13 18:19:07 -07:00
Eddie Hung a2eee9ebef Add counter-example from @cliffordwolf 2019-09-13 16:41:10 -07:00
Eddie Hung 14d72c39c3 Revert "Make one check $shift(x)? only; change testcase to be 8b" 
This reverts commit e2c2d784c8.
 2019-09-13 16:33:18 -07:00
Eddie Hung a1123b095c Merge remote-tracking branch 'origin/master' into xc7dsp 2019-09-12 12:11:11 -07:00
David Shah 6044fff074
Merge pull request #1370 from YosysHQ/dave/equiv_opt_multiclock 
Add equiv_opt -multiclock
 2019-09-12 12:26:28 +01:00
Eddie Hung 7d644f40ed Add AREG=2 BREG=2 test 2019-09-11 17:05:47 -07:00
Eddie Hung c0f26c2da8 Merge remote-tracking branch 'origin/eddie/peepopt_dffmuxext' into xc7dsp 2019-09-11 13:37:11 -07:00
Eddie Hung bdb5e0f29c Cope with presence of reset muxes too 2019-09-11 13:36:37 -07:00
Eddie Hung f46ef47893 Add more tests 2019-09-11 13:22:41 -07:00
Marcin Kościelnicki f72765090c Add -match-init option to dff2dffs. 2019-09-11 19:38:20 +02:00
Eddie Hung 6a95ecd41d Update test with a/b reset 2019-09-11 10:13:13 -07:00
Eddie Hung 36d6db7f8a Extend test for RSTP and RSTM 2019-09-11 09:09:08 -07:00
David Shah c43e52d2d7 Add equiv_opt -multiclock 
Signed-off-by: David Shah <dave@ds0.me>
 2019-09-11 13:55:59 +01:00
Eddie Hung fc7008671f Merge remote-tracking branch 'origin/eddie/peepopt_dffmuxext' into xc7dsp 2019-09-11 00:57:25 -07:00
Eddie Hung 3a8582081e proc instead of prep 2019-09-11 00:14:06 -07:00
Eddie Hung 6b23c7c227 Merge remote-tracking branch 'origin/eddie/peepopt_dffmuxext' into xc7dsp 2019-09-11 00:07:33 -07:00
Eddie Hung 580faae8ad Add unsigned case 2019-09-11 00:07:17 -07:00
Eddie Hung feb3fa65a3 Merge remote-tracking branch 'origin/master' into xc7dsp 2019-09-11 00:01:31 -07:00
Eddie Hung 1fc50a03fc Add SIMD test 2019-09-09 21:40:06 -07:00
Sean Cross 702ce405c1 tests: ice40: fix div_mod SB_LUT4 count 
This test is failing due to one of the changes present in this patchset.
Adjust the test to match the newly-observed values.

https://github.com/xobs/yosys/compare/smtbmc-msvc2-build-fixes...YosysHQ:xobs/pr1362

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-09-10 08:47:16 +08:00
Marcin Kościelnicki a82e8df7d3 techmap: Add support for extracting init values of ports 2019-09-07 16:30:43 +02:00
Eddie Hung e68507a716 Update macc test 2019-09-06 23:19:03 -07:00
Eddie Hung de8adecd39 Merge branch 'master' of github.com:YosysHQ/yosys 2019-09-06 22:52:00 -07:00
Eddie Hung 173c7936c3 Add missing -assert to equiv_opt 2019-09-06 22:51:44 -07:00
Eddie Hung 97e1520b13 Missing equiv_opt -assert 2019-09-06 22:50:03 -07:00
Eddie Hung e2c2d784c8 Make one check $shift(x)? only; change testcase to be 8b 2019-09-06 22:48:23 -07:00
Eddie Hung 51b559af2c Usee equiv_opt -assert 2019-09-06 22:48:04 -07:00
Eddie Hung 38e73a3788 Merge remote-tracking branch 'origin/eddie/peepopt_dffmuxext' into xc7dsp 2019-09-05 13:01:34 -07:00
Eddie Hung e742478e1d Merge remote-tracking branch 'origin/master' into xc7dsp 2019-09-05 13:01:27 -07:00
Eddie Hung ef0681ea4c simple/peepopt.v tests to various/peepopt.ys with equiv_opt & select 2019-09-05 08:43:22 -07:00
Eddie Hung 11f623cbe0 Revert "abc9 followed by clean otherwise netlist could be invalid for sim" 
This reverts commit 6fe1ca633d.
 2019-09-05 08:25:09 -07:00
Eddie Hung ba629e6a28 Merge remote-tracking branch 'origin/master' into xaig_arrival 2019-09-04 15:36:07 -07:00
Eddie Hung 6fe1ca633d abc9 followed by clean otherwise netlist could be invalid for sim 2019-09-04 15:20:04 -07:00
Eddie Hung 229e54568e Merge remote-tracking branch 'origin/eddie/peepopt_dffmuxext' into xc7dsp 2019-09-04 12:37:48 -07:00
Eddie Hung 3732d421c5 Merge remote-tracking branch 'origin/master' into xc7dsp 2019-09-04 12:37:42 -07:00
Eddie Hung 0cee66e759 Add peepopt_dffmuxext tests 2019-09-04 12:34:44 -07:00
SergeyDegtyar 93f305b1c5 Remove stat command form shifter.ys test 2019-09-04 14:57:45 +03:00
SergeyDegtyar a203c8569c Fix ecp5 tests 
- remove *_synth.v files and generation in scripts;
- change synth_ice40 to synth_ecp5;
 2019-09-04 12:15:52 +03:00
Eddie Hung 0ca0706630 Expand test with `hierarchy' without -auto-top 2019-09-03 12:17:26 -07:00
Eddie Hung 8124716830 Add `read -noverific` before read 2019-09-03 10:52:34 -07:00
Eddie Hung d6a84a78a7 Merge remote-tracking branch 'origin/master' into eddie/deferred_top 2019-09-03 10:49:21 -07:00
SergeyDegtyar 55fbc1a355 Uncomment sat command in memory.ys test. 2019-09-03 12:11:12 +03:00
SergeyDegtyar 11f330ed22 Add tests for ECP5 architecture 2019-09-03 11:53:37 +03:00
Emily 69a5dea89e Use `command -v` rather than `which` 2019-09-03 00:57:32 +01:00
Eddie Hung 2fa3857963 Merge remote-tracking branch 'origin/master' into xaig_arrival 2019-09-02 12:13:44 -07:00
Eddie Hung 4aa505d1b2
Merge pull request #1344 from YosysHQ/eddie/ice40_signed_macc 
ice40_dsp to allow signed multipliers
 2019-09-01 10:11:33 -07:00
Eddie Hung 4290548de3 Make abc9 test a bit more interesting 2019-08-30 20:31:53 -07:00
Eddie Hung 9be9631e5a Add macc test, with equiv_opt not currently passing 2019-08-30 16:18:14 -07:00
Eddie Hung d508dc2906 Update test for ffM 2019-08-30 15:01:08 -07:00
Eddie Hung 7df0e77565 Add mul_unsigned test 2019-08-30 14:35:05 -07:00
Eddie Hung 999fb33fd0
Merge pull request #1340 from YosysHQ/eddie/abc_no_clean 
abc9 to not call "clean" at end of run (often called outside)
 2019-08-30 12:27:09 -07:00
Eddie Hung 76a52712da Improve tests/ice40/macc.ys for SB_MAC16 2019-08-30 12:22:59 -07:00
Eddie Hung eef0676105
Merge pull request #1310 from SergeyDegtyar/master 
Add new tests for ice40 architecture
 2019-08-30 10:54:22 -07:00
Eddie Hung 6e475484b2 Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl 2019-08-30 09:37:32 -07:00
SergeyDegtyar 53912ad649 macc test fix 2019-08-30 16:01:36 +03:00
SergeyDegtyar 17c92dc679 Fix macc test 2019-08-30 15:22:46 +03:00
SergeyDegtyar 94a56c14b7 div_mod test fix 2019-08-30 14:17:03 +03:00
SergeyDegtyar f4a48ce8e6 fix div_mod test 2019-08-30 13:22:11 +03:00
SergeyDegtyar 86f1375ecd Fix test for counter 2019-08-30 12:38:28 +03:00
Sergey f23b540b45
Merge branch 'master' into master 2019-08-30 10:29:47 +03:00
SergeyDegtyar d144748401 Add new tests. 2019-08-30 09:45:33 +03:00
SergeyDegtyar eb0a5b2293 Remove unnecessary common.v(assertions for testbenches). 2019-08-30 09:17:32 +03:00
SergeyDegtyar 8e3abda193 Remove simulation from run-test.sh (unnecessary paths) 2019-08-30 09:11:03 +03:00
SergeyDegtyar 20f4aea480 Remove simulation from run-test.sh 2019-08-30 08:53:35 +03:00
Eddie Hung 6a111ad324 Nicer formatting 2019-08-29 17:24:48 -07:00
Sergey d360693040
Merge pull request #3 from YosysHQ/Sergey/tests_ice40 
Merge my changes to tests_ice40 branch
 2019-08-29 21:07:34 +03:00
Eddie Hung 67587bad7f Add constant expression attribute to test 2019-08-29 09:10:20 -07:00
SergeyDegtyar d588c6898f Add comments for examples from Lattice user guide 2019-08-29 10:49:46 +03:00
Eddie Hung 1fdb3fc98c Add failing test 2019-08-28 19:58:58 -07:00
Eddie Hung 13ecd8b0df Add run-test.sh too 2019-08-28 18:47:48 -07:00
Eddie Hung e301a3dadb Add SB_CARRY to ice40_opt test 2019-08-28 18:46:53 -07:00
Eddie Hung dd42aa87b9 Add ice40_opt test 2019-08-28 18:46:53 -07:00
Eddie Hung b8a9f73089 Comment out *.sh used for testbenches as we have no more 2019-08-28 12:36:20 -07:00
Eddie Hung 87d5d9b8c8 Use equiv for memory and dpram 2019-08-28 12:30:35 -07:00
Eddie Hung ebd0a1875b Use equiv_opt for latches 2019-08-28 12:21:15 -07:00
Eddie Hung 32eef26ee2 Merge remote-tracking branch 'origin/clifford/async2synclatch' into Sergey/tests_ice40 2019-08-28 12:18:32 -07:00
Eddie Hung 64ea147236 Add .gitignore 2019-08-28 09:55:34 -07:00
Eddie Hung 2f493fb465 Use test_pmgen for xilinx_srl 2019-08-28 09:55:09 -07:00
Eddie Hung 2e9e745efa Do not simplemap for variable test 2019-08-28 09:26:08 -07:00
Eddie Hung 975aaf190f Add xilinx_srl test 2019-08-28 09:24:19 -07:00
Eddie Hung ba5d81c7f1 Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl 2019-08-28 09:21:03 -07:00
SergeyDegtyar fe58790f37 Revert "Add tests for ecp5" 
This reverts commit 2270ead09f.
 2019-08-28 09:49:58 +03:00
SergeyDegtyar 2270ead09f Add tests for ecp5 2019-08-28 09:47:03 +03:00
Clifford Wolf 70c0cddb1e
Merge pull request #1325 from YosysHQ/eddie/sat_init 
In sat: 'x' in init attr should be ignored
 2019-08-28 00:18:14 +02:00
Eddie Hung 00387f3927 Revert to using clean 2019-08-27 09:24:32 -07:00
SergeyDegtyar 980830f7b8 Revert "Add tests for ecp5 architecture." 
This reverts commit 134d3fea90.
 2019-08-27 18:28:05 +03:00
Marcin Kościelnicki 5fb4b12cb5 improve clkbuf_inhibit propagation upwards through hierarchy 2019-08-27 17:26:47 +02:00
SergeyDegtyar 134d3fea90 Add tests for ecp5 architecture. 2019-08-27 18:12:18 +03:00
SergeyDegtyar aad9bad326 Add tests for macc and rom; 
Test cases from
https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071;
In both cases synthesized only LUTs and DFFs.
 2019-08-27 13:56:26 +03:00
Eddie Hung 6b5e65919a Revert "In sat: 'x' in init attr should not override constant" 
This reverts commit 2b37a093e9.
 2019-08-26 17:52:57 -07:00
Eddie Hung 528f1c8687 Improve tests to check that clkbuf is connected to expected 2019-08-26 13:45:16 -07:00
Eddie Hung dc87372a97 Wire with init on FF part, 1'bx on non-FF part 2019-08-24 15:05:44 -07:00
Eddie Hung 78b7d8f531 Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl 2019-08-23 11:32:44 -07:00
Eddie Hung a0d85393e3 Check clkbuf_inhibit=1 is ignored for custom selection 2019-08-23 11:15:26 -07:00
Eddie Hung 5628e2ec53 Add simple clkbufmap tests 2019-08-23 11:10:02 -07:00
Eddie Hung d62c10d641 tests/techmap/run-test.sh to cope with *.ys 2019-08-23 11:09:50 -07:00
Eddie Hung 10c41a5cf5 Blocking assignment 2019-08-23 09:11:04 -07:00
SergeyDegtyar c29380b381 Fix pull request 2019-08-23 18:55:01 +03:00
SergeyDegtyar 3c10f58d04 Fix run-test.sh; Add new test for dpram. 2019-08-23 17:00:16 +03:00
SergeyDegtyar 0b25dbf1c6 Fix path in run-test.sh 2019-08-23 12:40:14 +03:00
Eddie Hung fe1b2337fd Do not propagate mem2reg attribute through to result 2019-08-22 16:57:59 -07:00
Eddie Hung 36cf0a3dd5 Remove adffs_tb.v 2019-08-22 16:50:14 -07:00
Eddie Hung 51ffb093b5 In sat: 'x' in init attr should not override constant 2019-08-22 16:43:08 -07:00
Eddie Hung 2b37a093e9 In sat: 'x' in init attr should not override constant 2019-08-22 16:42:19 -07:00
Eddie Hung 66607845ec Remove Xilinx test 2019-08-22 16:18:07 -07:00
Eddie Hung e7a8cdbccf Add shregmap -tech xilinx test 2019-08-22 16:16:54 -07:00
Eddie Hung 698a0e3aaf WIP for equivalency checking memories 2019-08-22 16:05:12 -07:00
Eddie Hung 43e7c4917a Do not print OKAY 2019-08-22 16:05:12 -07:00
Eddie Hung 5061d239ae Fail if iverilog fails 2019-08-22 16:05:12 -07:00
Eddie Hung 8e3754bdb4 Hide tri-state warning message for now 2019-08-22 16:05:12 -07:00
Eddie Hung 659a481482 Remove unused output 2019-08-22 16:05:12 -07:00
Eddie Hung 61087329ef Fix tribuf test 2019-08-22 16:05:12 -07:00
Eddie Hung f9906eed68 Fix comments 2019-08-22 16:05:12 -07:00
Eddie Hung 9224b3bc17 Remove tech independent synthesis 2019-08-22 16:05:12 -07:00
Eddie Hung 388eb3288c Remove dffe instantation 2019-08-22 16:04:50 -07:00
Eddie Hung 9e537a76b5 Move $dffe to dffs.{v,ys} 2019-08-22 16:04:48 -07:00
Eddie Hung c5754d9e8b Make multiplier wider, do not do tech independent synth 2019-08-22 16:04:07 -07:00
Eddie Hung b800059fc1
Merge pull request #1317 from YosysHQ/eddie/opt_expr_shiftx 
opt_expr to trim A port of $shiftx/$shift
 2019-08-22 10:31:27 -07:00
Eddie Hung 6f971470f8 Respect opt_expr -keepdc as per @cliffordwolf 2019-08-22 08:37:27 -07:00
Eddie Hung 379f33af54 Handle $shift and Y_WIDTH > 1 as per @cliffordwolf 2019-08-22 08:22:23 -07:00
Eddie Hung bb1a8a0190 Add test 2019-08-21 21:58:20 -07:00
Eddie Hung a6776ee35e mem2reg to preserve user attributes and src 2019-08-21 13:36:01 -07:00
SergeyDegtyar d945b8a357 Fix all comments from PR 2019-08-21 21:52:07 +03:00
SergeyDegtyar b835ec37cb Add temp directory 2019-08-21 07:53:34 +03:00
Eddie Hung fce8dc7db2 Add test 2019-08-20 20:05:16 -07:00
SergeyDegtyar 71dd412ac5 Fix tests; Remove simulation; 
- Add -map and -assert options for equiv_opt;
	!!! '-assert' option was commented for the next tests (unproven
$equiv cells was found):
		- dffs;
		- div_mod;
		- latches;
		- mul_pow;
- Add design -load;
- Remove simulations;
 2019-08-20 15:52:25 +03:00
Clifford Wolf d0117d7d12
Merge branch 'master' into clifford/pmgen 2019-08-20 11:39:23 +02:00
Clifford Wolf 6ffb910d12 Add test case for real parameters 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-20 11:38:21 +02:00
SergeyDegtyar 153ec0541c Add new tests for ice40 architecture 2019-08-20 07:50:05 +03:00
whitequark 4a942ba7b9 proc_clean: fix order of switch insertion. 
Fixes #1268.
 2019-08-19 16:44:23 +00:00
Clifford Wolf 21699e5840 Add *.sv to tests/simple_abc9/.gitignore 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-19 13:04:57 +02:00
Clifford Wolf 1e3dd0a2da Merge branch 'master' of github.com:YosysHQ/yosys into clifford/pmgen 2019-08-19 13:04:06 +02:00
Eddie Hung e34f2de55d Merge remote-tracking branch 'origin/master' into clifford/testfast 2019-08-18 21:29:15 -07:00
Eddie Hung f5170a7eda Removal of more `stat` calls from tests 2019-08-18 21:28:45 -07:00
whitequark 101235400c
Merge branch 'master' into eddie/pr1266_again 2019-08-18 08:04:10 +00:00
Clifford Wolf 9e940f1276 Speed up "make test" and related cleanups 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-17 14:37:07 +02:00
Clifford Wolf f20be90436 Add test for pmtest_test "reduce" demo pattern 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-17 14:05:10 +02:00
Eddie Hung 51d28645da Merge https://github.com/bogdanvuk/yosys into bogdanvuk/opt_share 2019-08-16 13:40:29 -07:00
Clifford Wolf 40c40d9f5d Do not use Verific in tests/various/write_gzip.ys 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-16 14:22:46 +02:00
Eddie Hung 12c692f6ed Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder" 
This reverts commit c851dc1310, reversing
changes made to f54bf1631f.
 2019-08-12 12:06:45 -07:00
Eddie Hung 88d5185596 Merge remote-tracking branch 'origin/master' into eddie/fix_1262 2019-08-11 21:13:40 -07:00
David Shah f9020ce2b3
Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER" 2019-08-10 17:14:48 +01:00
Eddie Hung 0adf81cb91 Add $alu tests 2019-08-09 12:13:17 -07:00
Eddie Hung 8350dfb809 Add alumacc versions of opt_expr tests 2019-08-09 10:30:53 -07:00
Eddie Hung 9300111601 Add new $alu test, remove wreduce 2019-08-09 10:22:06 -07:00
Eddie Hung 313c9ec8df Cleanup some more 2019-08-09 10:13:49 -07:00
Eddie Hung d9c1664462 Simplify opt_expr tests using equiv_opt 2019-08-09 10:08:17 -07:00
Eddie Hung 8bf45f34c4 Remove dump call 2019-08-07 21:36:02 -07:00
Eddie Hung 2b6cdfb39f Move tests/various/opt* into tests/opt/ 2019-08-07 21:35:48 -07:00
Eddie Hung d5e8c0e6d3 Remove ice40_unlut call, simply do equiv_opt on synth_ice40 2019-08-07 21:33:56 -07:00
Eddie Hung 35bf509603 Add testcase from removed opt_ff.{v,ys} 2019-08-07 21:31:32 -07:00
Eddie Hung 4545bf482f Remove tests/opt/opt_ff.{v,ys} as they don't seem to do anything but run 2019-08-07 16:48:38 -07:00
Clifford Wolf e9a756aa7a
Merge pull request #1213 from YosysHQ/eddie/wreduce_add 
wreduce/opt_expr: improve width reduction for $add and $sub cells
 2019-08-07 14:27:35 +02:00
Clifford Wolf 48f7682e32
Merge pull request #1240 from ucb-bar/firrtl-properties+pow+xnor 
Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog semantic differences.
 2019-08-07 12:31:32 +02:00
Bogdan Vukobratovic 067b44938c Fix wrong results when opt_share called before opt_clean 2019-08-07 09:30:58 +02:00
Eddie Hung 2d1b517b01 Add signed opt_expr tests 2019-08-06 15:40:30 -07:00
Eddie Hung 769c750c22 Add signed test 2019-08-06 15:38:43 -07:00
Eddie Hung 51b39219cd Move LSB tests from wreduce to opt_expr 2019-08-06 15:24:49 -07:00
Eddie Hung 26cb3e7afc Merge remote-tracking branch 'origin/master' into eddie/wreduce_add 2019-08-06 14:50:00 -07:00
David Shah 3a3da678ad Add test for writing gzip-compressed files 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-06 17:43:04 +01:00
Bogdan Vukobratovic 6a796accc0 Support various binary operators in opt_share 2019-08-04 19:06:38 +02:00
Bogdan Vukobratovic d8be5ce6ba Tabs to spaces in opt_share examples 2019-08-03 12:35:46 +02:00
Bogdan Vukobratovic 280c4e7794 Fix spacing in opt_share tests, change wording in opt_share help 2019-08-03 12:28:46 +02:00
Jim Lawson 3b8c917025 Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog semantic differences. 
Use FIRRTL spec vlaues for definition of FIRRTL widths.
Added support for '$pos`, `$pow` and `$xnor` cells.
Enable tests/simple/operators.v since all operators tested there are now supported.
Disable FIRRTL tests of tests/simple/{defvalue.sv,implicit_ports.v,wandwor.v} since they currently generate FIRRTL compilation errors.
 2019-07-31 09:27:38 -07:00
Bogdan Vukobratovic c075486c59 Reimplement opt_share to work on $alu and $pmux 2019-07-28 16:03:54 +02:00
Bogdan Vukobratovic 07c4a7d438 Implement opt_share 
This pass identifies arithmetic operators that share an operand and whose
results are used in mutually exclusive cases controlled by a multiplexer, and
merges them together by multiplexing the other operands
 2019-07-26 11:36:48 +02:00
David Shah 933db0410e Add support for reading gzip'd input files 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-26 10:23:58 +01:00
Eddie Hung c926eeb43a Add another test 2019-07-19 14:02:46 -07:00
Eddie Hung 5bd088a686 Add one more test with trimming Y_WIDTH of $sub 2019-07-19 13:11:30 -07:00
Eddie Hung 415a2716df Be more explicit 2019-07-19 12:53:18 -07:00
Eddie Hung 4e9b1d36fa Add tests for sub too 2019-07-19 12:50:11 -07:00
Eddie Hung 3839bd50f2 Add test 2019-07-19 12:43:02 -07:00
Eddie Hung 8a2a2cd035 Forgot to commit 2019-07-16 12:44:26 -07:00
Eddie Hung dd10d2b00d Add tests for cmp2lut on LUT6 2019-07-16 12:11:59 -07:00
Eddie Hung 41243a53b3 Update test with more accurate LUT mask 2019-07-12 21:00:59 -07:00
Clifford Wolf 9546ccdbd3 Fix tests/various/async FFL test 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-07-09 22:44:39 +02:00
Clifford Wolf 5138621482 Improve tests/various/async, disable failing ffl test 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-07-09 22:21:25 +02:00
Clifford Wolf c18b23f055 Add tests/various/async.{sh,v} 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-07-09 20:58:59 +02:00
Clifford Wolf 3dd92fcd15 Improve tests/various/run-test.sh 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-07-09 20:58:28 +02:00
Clifford Wolf f8512864cd Add tests/simple_abc9/.gitignore 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-07-09 20:58:01 +02:00
Eddie Hung de26328130
Merge pull request #1156 from YosysHQ/eddie/fix_abc9_unknown_cell 
write_xaiger to treat unknown cell connections as keep-s
 2019-07-03 09:43:00 -07:00
Clifford Wolf e38b2ac648
Merge pull request #1147 from YosysHQ/clifford/fix1144 
Improve specify dummy parser
 2019-07-03 12:30:37 +02:00
Clifford Wolf 1f173210eb Fix tests/various/specify.v 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-07-03 11:25:05 +02:00
Clifford Wolf ba36567908 Some cleanups in "ignore specify parser" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-07-03 11:22:10 +02:00
Eddie Hung 9c556e3c02 Add test 2019-07-02 19:13:40 -07:00
Eddie Hung 8455d1f4ff
Merge pull request #1150 from YosysHQ/eddie/script_from_wire 
Add "script -select [selection]" to allow commands to be taken from wires
 2019-07-02 10:20:42 -07:00
Eddie Hung 81a717e9b7 Update test for Pass::call_on_module() 2019-07-02 08:22:31 -07:00
Eddie Hung 90382a0f6d Update test too 2019-07-02 08:19:23 -07:00
David Shah d45936fe5f memory_dff: Fix checking of feedback mux input when more than one mux 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-02 13:35:50 +01:00
Eddie Hung 04459cb30a Comment out invalid syntax 2019-06-30 11:48:01 -07:00
Eddie Hung fd2fb4f0f0 Merge branch 'master' into eddie/script_from_wire 2019-06-28 14:56:34 -07:00
Eddie Hung 0ec7c09756 autotest.sh to define _AUTOTB when test_autotb 2019-06-28 14:56:22 -07:00
Eddie Hung 64f6b0c747 Try command in another module 2019-06-28 13:41:32 -07:00
Eddie Hung 2c6aaef3db Add test 2019-06-28 13:32:09 -07:00
Eddie Hung da5f830395
Merge pull request #1098 from YosysHQ/xaig 
"abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
 2019-06-28 10:59:03 -07:00
Eddie Hung dc677c791d Add test from #1144, and try reading without '-specify' flag 2019-06-28 10:12:48 -07:00
Clifford Wolf 74945dd738
Merge pull request #1146 from gsomlo/gls-test-abc-ext 
tests: use optional ABCEXTERNAL when specified
 2019-06-28 10:30:31 +02:00
Clifford Wolf 1c7ce251f3
Merge pull request #1046 from bogdanvuk/master 
Optimizing DFFs whose initial value prevents their value from changing
 2019-06-28 08:30:18 +02:00
Gabriel L. Somlo 6f1c137989 tests: use optional ABCEXTERNAL when specified 
Commits 65924fd1, abc40924, and ebe29b66 hard-code the invocation
of yosys-abc, which fails if ABCEXTERNAL was specified during the
build. Allow tests to utilize an optional, externally specified
abc binary.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2019-06-27 23:00:13 -04:00