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1319 Commits

Author SHA1 Message Date
Clifford Wolf 3ab79a231b Bugfix in handling of array instances with empty ports 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-31 18:09:31 +02:00
Clifford Wolf cee4b1e6bc Disable memory_dff for initialized FFs 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-28 17:16:15 +02:00
Clifford Wolf 74efafc1cf Add some cleanup code to memory_nordff 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-28 16:42:06 +02:00
Robert Ou 9763e4d830 Fix infinite loop in abc command under emscripten 2018-05-18 22:42:39 -07:00
Robert Ou bfce3a7479 Add an option to statically link abc into yosys 
This is currently incomplete because the output filter no longer works.
 2018-05-18 22:35:28 -07:00
Aman Goel 6e63df6dd0 Correction to -expose with setundef 2018-05-15 13:06:23 -04:00
Clifford Wolf fe80b39f56 Fix iopadmap for loops between tristate IO buffers 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-15 14:02:27 +02:00
Clifford Wolf edd297fb1c Fix iopadmap for cases where IO pins already have buffers on them 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-15 13:13:43 +02:00
Aman Goel 8b9a8c7f91 Minor correction 
Minor typo error correction in -expose with setundef
 2018-05-14 18:58:49 -04:00
Aman Goel b4a303a1b7 Corrections to option -expose in setundef pass 2018-05-13 20:13:54 -04:00
Aman Goel 9286acb687 Add option -expose to setundef pass 
Option -expose converts undriven wires to inputs.

Example usage: setundef -undriven -expose [selection]
 2018-05-13 16:53:35 -04:00
Clifford Wolf 0fad1570b5 Some cleanups in setundef.cc 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-13 16:36:12 +02:00
Christian Krämer c1ecb1b2f1 Add "#ifdef __FreeBSD__" 
(Re-commit e3575a8 with corrected author field)
 2018-05-13 13:08:26 +02:00
Clifford Wolf 1167538d26 Revert "Add "#ifdef __FreeBSD__"" 
This reverts commit e3575a86c5.
 2018-05-13 13:06:36 +02:00
Clifford Wolf 587056447e Add optimization of tristate buffer with constant control input 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-12 15:18:27 +02:00
Clifford Wolf 11406a8082 Add "hierarchy -simcheck" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-12 13:59:13 +02:00
Johnny Sorocil e3575a86c5 Add "#ifdef __FreeBSD__" 2018-05-05 13:02:44 +02:00
Clifford Wolf 145c685de0 Add ABC FAQ to "help abc" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-04 21:59:31 +02:00
Clifford Wolf a572b49538 Replace -ignore_redef with -[no]overwrite 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-03 15:25:59 +02:00
Clifford Wolf 705c366a91 Added missing dont_use handling for SR FFs to dfflibmap 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-04-05 11:01:45 +02:00
Clifford Wolf 665eec3d53 Removed $timescale from "sat" command VCD writer 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-29 12:38:41 +02:00
Clifford Wolf ee3c12d6d9 Chenged "extensions_map" to "extensions_list" in hierarchy.cc 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-27 14:12:57 +02:00
Sergi Granell f93f8aaa11 passes/hierarchy: Reduce code duplication in expand_module 
This also makes it easier to add new file extensions support.

Signed-off-by: Sergi Granell <xerpi.g.12@gmail.com>
 2018-03-27 09:35:20 +02:00
Clifford Wolf 491c352da7 Add .sv support to "hierarchy -libdir" 2018-03-26 21:19:00 +02:00
Clifford Wolf 08225f49a4 Add "expose -input" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-12 13:52:52 +01:00
Clifford Wolf 83ffb23739 Add "setundef -undef" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-12 13:52:35 +01:00
Clifford Wolf a74f805ba0 Fix handling of src attributes in flatten 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-10 13:55:30 +01:00
Clifford Wolf 73c01dca65 Add "memory_nordff" pass 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-06 23:31:51 +01:00
Clifford Wolf 61a9e2eeb3 Fix connwrappers help message 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-04 22:54:34 +01:00
Clifford Wolf d31584c649 Add $dlatchsr support to clk2fflogic 2018-02-26 12:20:28 +01:00
Clifford Wolf fba499b866 Fix opt_rmdff handling of $dlatchsr 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-02-26 11:46:05 +01:00
Clifford Wolf eb67a7532b Add $allconst and $allseq cell types 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-02-23 13:14:47 +01:00
Clifford Wolf 717abc93a8 Recognize stand-alone obj pattern even when it contains a slash 2018-02-13 14:55:24 +01:00
Clifford Wolf 9337e4999d Improve log messages in equiv_make 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-01-19 16:20:40 +01:00
Clifford Wolf 9ac560f5d3 Add "dffinit -highlow" and fix synth_intel 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-01-09 18:42:19 +01:00
Clifford Wolf a96c775a73 Add support for "yosys -E" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-01-07 16:36:13 +01:00
Clifford Wolf 446ccf1f05 Bugfix in hierarchy blackbox module port width handling 2018-01-07 16:35:22 +01:00
Clifford Wolf c80315cea4 Bugfix in hierarchy handling of blackbox module ports 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-01-05 13:28:45 +01:00
Clifford Wolf fefb652d56
Merge pull request #480 from Fatsie/liberty_value_expression 
Value of properties can be expression.
 2018-01-04 13:30:00 +01:00
Clifford Wolf 2d140a44eb Temporarily derive blackbox modules in hierarchy to evaluate port widths 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-01-04 13:23:29 +01:00
Staf Verhaegen 92eb841f0a Value of properties can be expression. 
Example found in the 2007.03 Liberty Reference Manual that was also found
in the wild:

    input_voltage(CMOS) {
        vil : 0.3 * VDD ;
        vih : 0.7 * VDD ;
        vimin : -0.5 ;
        vimax : VDD + 0.5 ;
    }

Current implementation just parses the expression but no interpretation is done.
 2018-01-03 21:37:17 +00:00
Clifford Wolf 6132e6e72a Fix a bug in clk2fflogic memory handling 2017-12-14 03:05:55 +01:00
Clifford Wolf 590e6961cb Add clk2fflogic memory support 2017-12-14 02:07:31 +01:00
Clifford Wolf 88182e46d7 Check for memories in clk2fflogic 2017-12-13 19:14:34 +01:00
Clifford Wolf ca2adc30c9 Add warnings for driver-driver conflicts between FFs (and other cells) and constants 2017-12-12 17:13:27 +01:00
Clifford Wolf 9ae25039fb Add support for editline as replacement for readline 2017-11-08 02:55:00 +01:00
Clifford Wolf 4f31cb6dad Add "ltp" command 2017-10-31 12:40:25 +01:00
Clifford Wolf c238f45ecf Fix memory corruption bug in opt_rmdff 2017-10-26 18:02:15 +02:00
Clifford Wolf 1e502ef5a0 Fix typo in opt_clean log message 2017-10-26 18:01:48 +02:00
Clifford Wolf 716dbc9274 Revert 90be0d8 as it causes endless loops for some designs 2017-10-14 11:57:25 +02:00
Kaj Tuomi 90be0d800b Fix input vector for reduce cells. 2017-10-12 13:05:10 +03:00
Clifford Wolf 7c57d8fbb4 Rewrite ABC output to include proper net names in timing report 2017-10-10 13:32:58 +02:00
Clifford Wolf 3f22f48eeb Add blackbox command 2017-10-04 18:30:42 +02:00
Andrew Zonenberg 2b65b65d70 Added missing "break" 2017-09-15 17:54:52 -07:00
Andrew Zonenberg 7b3966714c Implemented off-chain support for extract_reduce 2017-09-15 13:59:18 -07:00
Andrew Zonenberg 3404934c9c extract_reduce now only removes the head of the chain, relying on "clean" to delete upstream cells. Added "-allow-off-chain" flag, but it's currently ignored. 2017-09-15 13:59:05 -07:00
Clifford Wolf ce78717e36 Merge pull request #412 from azonenberg/reduce-fixes 
extract_reduce: Fix segfault on "undriven" inputs
 2017-09-14 22:36:25 +02:00
Robert Ou ab1bf8d661 extract_reduce: Fix segfault on "undriven" inputs 
This is easily triggered when un-techmapping if the technology-specific
cell library isn't loaded. Outputs of technology-specific cells will be
seen as inputs, and nets using those outputs will be seen as undriven.
Just ignore these cells because they can't be part of a reduce chain
anyways.
 2017-09-14 12:54:44 -07:00
Clifford Wolf 498526cc0b Merge pull request #411 from azonenberg/counter-extraction-fixes 
Various improvements and bug fixes to extract_counter
 2017-09-14 21:44:26 +02:00
Andrew Zonenberg 66e8986ae7 Minor changes to opt_demorgan requested during code review 2017-09-14 10:35:25 -07:00
Andrew Zonenberg 367d6b2194 Fixed bug where counter extraction on non-GreenPAK devices incorrectly handled parallel counter output 2017-09-14 10:27:10 -07:00
Andrew Zonenberg c8f2f082c6 Added support for inferring counters with reset to full scale instead of zero 2017-09-14 10:26:43 -07:00
Andrew Zonenberg 122532b7e1 Added RESET_TO_MAX parameter to $__COUNT_ cell. Cannot yet be extracted. 2017-09-14 10:26:32 -07:00
Andrew Zonenberg 0484ad666d Added support for inferring counters with active-low reset 2017-09-14 10:26:21 -07:00
Andrew Zonenberg a84172b23b Initial support for extraction of counters with clock enable 2017-09-14 10:26:10 -07:00
Andrew Zonenberg c4a70a8cc3 Fixed typo in comment. Fixed bug where extract_counter would create up counters when it meant to create down counters. 2017-09-14 10:25:51 -07:00
Andrew Zonenberg 6da5d36968 Initial version of opt_demorgan is functioning for AND/OR gates. Not the prettiest results for bus inputs, but this can be improved 2017-09-12 18:47:46 -07:00
Clifford Wolf f9d023c53f Add src attribute to extra cells generated by proc_dlatch 2017-09-09 10:18:08 +02:00
Clifford Wolf 7d41c5e177 Further improve extract_fa (but still buggy) 2017-09-02 16:39:17 +02:00
Clifford Wolf 18609f3df8 Merge branch 'master' of github.com:cliffordwolf/yosys 2017-09-01 12:35:09 +02:00
Clifford Wolf 8a66bd30c6 Update more stuff to use get_src_attribute() and set_src_attribute() 2017-09-01 12:26:55 +02:00
Jason Lowdermilk 8dc6083de7 updated to use get_src_attribute() and set_src_attribute(). 2017-08-31 14:51:56 -06:00
Andrew Zonenberg ed1e3ed39b extract_counter: Added optimizations to remove unused high-order bits 2017-08-30 18:15:12 -07:00
Andrew Zonenberg 634f18be96 extract_counter: Minor changes requested to comply with upstream policy, fixed a few typos 2017-08-30 16:28:25 -07:00
Jason Lowdermilk 32c0f1193e Add support for source line tracking through synthesis phase 2017-08-29 14:46:35 -06:00
Andrew Zonenberg 3fc1b9f3fd Finished refactoring counter extraction to be nice and generic. Implemented techmapping from $__COUNT_ to GP_COUNTx cells. 2017-08-28 22:18:57 -07:00
Andrew Zonenberg 46b01f05bb Refactored extract_counter to be generic vs GreenPAK specific 2017-08-28 22:18:47 -07:00
Andrew Zonenberg b5c15636c5 Refactoring: Renamed greenpak4_counters pass to extract_counter, moved it to techmap/ since it's going to become a generic pass 2017-08-28 22:18:34 -07:00
Clifford Wolf 908f34aafc Rename recover_reduce to extract_reduce, fix args handling 2017-08-28 19:52:06 +02:00
Clifford Wolf 3aad3ed3da Merge branch 'recover-reduce' of https://github.com/azonenberg/yosys into azonenberg-recover-reduce 2017-08-28 19:46:17 +02:00
Clifford Wolf ebbb0e9479 Further improve extract_fa pass 2017-08-28 19:43:26 +02:00
Robert Ou 849b885775 recover_reduce: Update documentation 
The documentation now describes the commands performed in the deleted
recover_reduce script.
 2017-08-27 02:19:19 -07:00
Robert Ou 74d0f17fd4 recover_reduce: Reindent using tabs 2017-08-27 02:12:41 -07:00
Robert Ou 8a5887464c recover_reduce: Rename recover_reduce_core to recover_reduce 
Clifford has commented on PR #387 stating that he does not like the
driver script and would prefer to only have the core script with
appropriate notes in the documentation.

Also rename to .cc (rather than .cpp) for consistency.
 2017-08-27 02:01:32 -07:00
Robert Ou 99dad40ed0 recover_reduce: Add driver script for the $reduce_* recover feature 
Conflicts:
	passes/techmap/Makefile.inc
 2017-08-27 01:57:20 -07:00
Robert Ou 8b7dc792ee recover_reduce_core: Finish implementing the core function 2017-08-27 01:56:49 -07:00
Robert Ou fa310c98f8 recover_reduce_core: Initial commit 
Conflicts:
	passes/techmap/Makefile.inc
 2017-08-27 01:56:49 -07:00
Clifford Wolf 68c42f3a19 Don't track , ... contradictions through x/z-bits 2017-08-25 16:18:17 +02:00
Clifford Wolf db6d78a186 Add removing of redundant pairs of bits in ==, ===, !=, and !== to opt_expr 2017-08-25 16:02:15 +02:00
Clifford Wolf 382cc90c65 Further improve extract_fa (seems to be fully functional now) 2017-08-25 13:41:54 +02:00
Clifford Wolf 0bf612506c Rename "adders" to "extract_fa" 2017-08-25 12:04:40 +02:00
Clifford Wolf 15cdda7c4b Towards more generic "adder" function extractor 2017-08-23 14:20:10 +02:00
Clifford Wolf 51cbec7f75 Add experimental adders pass 2017-08-22 13:52:13 +02:00
Clifford Wolf df3e6e1ec9 Remove some dead code from fsm_map 2017-08-21 15:02:16 +02:00
Clifford Wolf ca53fba44a Rename "singleton" pass to "uniquify" 2017-08-20 12:31:50 +02:00
Clifford Wolf d38a64b1cf More intuitive handling of "cd .." for singleton modules 2017-08-19 00:15:12 +02:00
Clifford Wolf bbdf7d9c66 Add "sim -zinit -rstlen" 2017-08-18 12:54:17 +02:00
Clifford Wolf d30cc60ba9 Add "sim" support for memories 2017-08-18 11:44:50 +02:00
Clifford Wolf 0be738eaac Add support for assert/assume/cover to "sim" command 2017-08-18 10:24:14 +02:00
Clifford Wolf 92e4b5aa77 Add writeback mode to "sim" command 2017-08-17 15:54:51 +02:00