Marcelina Kościelnicka
af54b8bc61
Naming fixes.
2020-07-05 22:21:59 +02:00
Marcelina Kościelnicka
f3f55ae7c2
dfflegalize: Prefer mapping dff to sdff before adff
...
This ensures that, when both sync and async FFs are available and abc9
is involved, the sync FFs will be used, and will thus remain available
for sequential synthesis.
2020-07-05 12:01:43 +02:00
Marcelina Kościelnicka
7afcb72c98
opt_expr: Fix crash on $mul optimization with more zeros removed than Y has.
...
Fixes #2221 .
2020-07-05 06:31:58 +02:00
Eddie Hung
27a9d1b6e6
abc9: only techmap (* abc9_flop *) modules
2020-07-04 19:45:10 +02:00
Eddie Hung
0ba79feb6f
abc9: techmap from user design to allow abc9_flop modules to be composed
...
from other primitives
2020-07-04 19:45:10 +02:00
Rupert Swarbrick
a9b61080a4
Add newlines to help text for dfflegalize
...
I think these were probably missed by accident. Spotted because GCC
spits out lots of messages like this:
passes/techmap/dfflegalize.cc:114:7: warning: zero-length gnu_printf format string [-Wformat-zero-length]
114 | log("");
| ^~
(because we tell GCC that the first argument to log() looks like a
printf control string in log.h, and a zero length such string triggers
a warning).
2020-07-03 12:30:12 +02:00
clairexen
e4b9e64d1b
Merge pull request #2208 from boqwxp/qbfsat-cleanup
...
qbfsat: Cleanup and refactoring
2020-07-02 17:48:37 +02:00
clairexen
5428666151
Merge pull request #2186 from YosysHQ/mwk/dfflegalize
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Add dfflegalize pass.
2020-07-02 17:46:11 +02:00
clairexen
d3422f8a5e
Merge pull request #2211 from YosysHQ/mwk/fix-fmcombine-ff
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fmcombine: use the master ff cell type list
2020-07-02 17:43:48 +02:00
clairexen
5dbf91847a
Merge pull request #2210 from YosysHQ/mwk/fix-opt_merge
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opt_merge: use the master FF type list
2020-07-02 17:43:34 +02:00
Alberto Gonzalez
56f98b9e3d
qbfsat: Remove useless comment and #ifndef guards.
2020-07-01 19:55:16 +00:00
Alberto Gonzalez
3345d39e6f
qbfsat: Specify default values for some options in the help message.
2020-07-01 19:55:16 +00:00
Alberto Gonzalez
95e8016811
qbfsat: Clean up external executable command lines and update temporary directory name.
2020-07-01 19:55:16 +00:00
Alberto Gonzalez
8cd60be654
qbfsat: Clean up and refactor data structures into `qbfsat.h`.
2020-07-01 19:55:16 +00:00
clairexen
b1707407a0
Merge pull request #2138 from boqwxp/qbfsat-oflag
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qbfsat: Add `-O[012]` options to control pre-solving simplification with ABC
2020-07-01 16:35:27 +02:00
clairexen
2b0f6e24e2
Merge pull request #2206 from boqwxp/qbfsat-fix-name-specialization
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qbfsat: Fix name-based hole specialization
2020-07-01 16:34:32 +02:00
Marcelina Kościelnicka
e3564b4502
Add dfflegalize pass.
2020-07-01 01:57:15 +02:00
Marcelina Kościelnicka
7c91f13f51
fmcombine: use the master ff cell type list
2020-06-30 21:07:17 +02:00
Marcelina Kościelnicka
77b15dd8e9
opt_merge: use the master FF type list
2020-06-30 20:57:35 +02:00
clairexen
3fb5b4fd8a
Merge pull request #2199 from YosysHQ/mmicko/sim_memory
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sim - error when memrd and memwr detected
2020-06-30 17:12:51 +02:00
clairexen
275cee71f6
Merge pull request #2201 from YosysHQ/fix_test_cell_ilang
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Use ID macro to fix assertion
2020-06-30 17:11:13 +02:00
Alberto Gonzalez
83c595aaac
qbfsat: Add `-O[012]` options to control pre-solving simplification with ABC.
...
Thanks to @mwk for the gate mapping part of the ABC scripts.
Co-Authored-By: Marcelina Kościelnicka <mwk@0x04.net>
2020-06-30 06:44:17 +00:00
Alberto Gonzalez
f544a2cc84
qbfsat: Fix name-based hole specialization.
...
Look for unique connections in the containing module with the $anyconst port Y SigBit on the RHS and use those. If no such connection is found, fall back to using the name of the $anyconst port Y SigBit.
2020-06-30 01:53:21 +00:00
whitequark
a97c13f0ca
techmap: don't drop attributes on replaced cells.
...
This was introduced in 76c4ee4ea5
.
Fixes #2204 .
2020-06-29 23:14:13 +00:00
Miodrag Milanović
4160acc0b1
Merge pull request #2200 from YosysHQ/mmicko/fix_expose
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expose pass fix
2020-06-29 15:16:29 +02:00
Miodrag Milanovic
405b4e97a1
Give error that options are exclusive
2020-06-29 14:45:49 +02:00
Miodrag Milanovic
0545a042f3
cleanup
2020-06-29 14:42:48 +02:00
Miodrag Milanovic
5aae936044
Use ID macro to fix assertion
2020-06-29 13:18:13 +02:00
Miodrag Milanovic
87717d67d1
expose pass fix
2020-06-29 11:56:43 +02:00
Miodrag Milanovic
48b6d3272c
sim - error when memrd and memwr detected
2020-06-29 10:33:39 +02:00
Xiretza
e2cfe57edd
test_cell: don't generate directional shifts with \B_SIGNED=1
...
This was made an explicit error in e97e33d
, "kernel: require \B_SIGNED=0
on $shl, $sshl, $shr, $sshr.".
2020-06-28 21:30:16 +02:00
clairexen
c7d71f436d
Merge pull request #2168 from whitequark/assert-unused-exprs
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Use (and ignore) the expression provided to log_assert in NDEBUG builds
2020-06-25 18:21:51 +02:00
clairexen
21209d632e
Merge pull request #2135 from boqwxp/qbfsat-timeinfo
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log and qbfsat: Also include child process usage in `PerformanceTimer::query()` and report the time for each call to the QBF-SAT solver
2020-06-25 18:18:09 +02:00
clairexen
fb6441731a
Merge pull request #2093 from boqwxp/qbfsat-bugfixes
...
qbfsat: Multiple bugfixes
2020-06-25 18:14:17 +02:00
Marcelina Kościelnicka
8f12c5b063
simplemap: Fix $dffsre mapping.
2020-06-23 23:16:43 +02:00
Marcelina Kościelnicka
88e7f90663
Update dff2dffe, dff2dffs, zinit to new FF types.
2020-06-23 18:24:53 +02:00
Marcelina Kościelnicka
832acc8648
Add new FF types to simplemap.
2020-06-23 15:40:02 +02:00
Marcelina Kościelnicka
119f79d8b9
Add support for new FF types in some opt passes.
2020-06-23 15:40:02 +02:00
Marcelina Kościelnicka
b0bee396a8
Add new builtin FF types
...
The new types include:
- FFs with async reset and enable (`$adffe`, `$_DFFE_[NP][NP][01][NP]_`)
- FFs with sync reset (`$sdff`, `$_SDFF_[NP][NP][01]_`)
- FFs with sync reset and enable, reset priority (`$sdffs`, `$_SDFFE_[NP][NP][01][NP]_`)
- FFs with sync reset and enable, enable priority (`$sdffce`, `$_SDFFCE_[NP][NP][01][NP]_`)
- FFs with async reset, set, and enable (`$dffsre`, `$_DFFSRE_[NP][NP][NP][NP]_`)
- latches with reset or set (`$adlatch`, `$_DLATCH_[NP][NP][01]_`)
The new FF types are not actually used anywhere yet (this is left
for future commits).
2020-06-23 15:40:02 +02:00
Alberto Gonzalez
a564cc806f
log, qbfsat: Include child process time in `PerformanceTimer::query()` and report the time for each call to the QBF-SAT solver.
2020-06-21 02:16:52 +00:00
Alberto Gonzalez
62a9e62a1b
qbfsat: Simplify solution recovery parsing and tweak the solution regexes.
2020-06-21 02:16:11 +00:00
Alberto Gonzalez
e1fedf054e
qbfsat: Avoid instantiating `AttrObject`s directly.
...
Co-Authored-By: Claire Wolf <claire@symbioticeda.com>
2020-06-21 02:16:11 +00:00
Alberto Gonzalez
08cede4669
qbfsat: Simplify solution format and replace `SigBit::str()` with `log_signal()`.
...
Co-Authored-By: Claire Wolf <claire@symbioticeda.com>
2020-06-21 02:16:11 +00:00
Alberto Gonzalez
4ab41c6435
qbfsat: Fixes three bugs.
...
1. Infinite loop in the optimization procedure when the first solution found while maximizing is at zero.
2. A signed-ness issue when maximizing.
3. Erroneously entering bisection mode with no wire to optimize.
2020-06-21 02:16:11 +00:00
Alberto Gonzalez
a3d1f8637a
qbfsat: Use bit precise mapping for hole value wires and a more robust hole spec for writing to and specializing from a solution file.
2020-06-21 02:16:11 +00:00
whitequark
c8c3c7af87
Use [[maybe_unused]] instead of YS_ATTRIBUTE(unused).
...
[[maybe_unused]] is available since C++17, so this commit adds
a polyfill YS_MAYBE_UNUSED. Once we require C++17 we can drop it.
2020-06-19 15:48:58 +00:00
whitequark
118e4caa37
Remove YS_ATTRIBUTE(unused) where present just for log_assert()/log_debug().
2020-06-19 15:48:58 +00:00
whitequark
ede4b10da8
Merge pull request #2173 from whitequark/use-cxx11-final-override
...
Use C++11 final/override/[[noreturn]]
2020-06-19 06:15:33 +00:00
whitequark
7191dd16f9
Use C++11 final/override keywords.
2020-06-18 23:34:52 +00:00
Alberto Gonzalez
76dfa81790
cutpoint: Improve efficiency by iterating over module ports instead of module wires.
2020-06-18 17:42:36 +00:00
N. Engelhardt
dfde1cf1c5
Merge pull request #2153 from boqwxp/splitnets-cleanup
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splitnets: Cleanup and efficiency improvements
2020-06-18 19:16:55 +02:00
whitequark
5439faebf9
Merge pull request #2142 from whitequark/splitnets-hdlname
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splitnets: propagate (*hdlname*) and disambiguate via start_offset
2020-06-18 16:57:24 +00:00
Anonymous Maarten
60fb9cabcf
msvc does not support designated initializers in structs
2020-06-17 16:20:52 +02:00
Alberto Gonzalez
f5d7cd60f5
splitnets: Clean up pseudo-private member usage
2020-06-13 05:47:55 +00:00
Alberto Gonzalez
b70de98bd1
splitnets: Slightly improve efficiency by avoiding some unnecessary lookups
2020-06-13 05:26:30 +00:00
whitequark
2139a5c21a
splitnets: propagate (*hdlname*) and disambiguate via start_offset.
...
This allows reliably coalescing the split wires later.
2020-06-10 19:59:08 +00:00
Claire Wolf
0bd70e8222
Drive-by modernization in sat.cc
...
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-06-09 22:48:26 +02:00
Claire Wolf
3c7122c378
Do not optimize away FFs in "prep" and Verific fron-end
...
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-06-09 15:54:14 +02:00
whitequark
98e1080345
flatten: accept processes.
2020-06-09 09:56:23 +00:00
whitequark
fbb346ea91
flatten: preserve original object names via hdlname attribute.
2020-06-08 20:19:41 +00:00
whitequark
8d821dbbdb
flatten: only prepend $flatten once per wire.
2020-06-08 20:19:41 +00:00
whitequark
a1814b732f
flatten: make hygienic.
...
Before this commit, `flatten` matched the template objects with
the newly created objects solely by their name. Because of this,
it could be confused by code such as:
module bar();
$dff a();
endmodule
module foo();
bar b();
$dff \b.a ();
endmodule
After this commit, `flatten` avoids every possible case of name
collision.
Fixes #2106 .
2020-06-08 19:30:21 +00:00
clairexen
369dcb4e82
Merge pull request #2085 from rswarbrick/select
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Silence warning in select.cc and pass some more args by ref
2020-06-08 15:55:52 +02:00
clairexen
0f209378a8
Merge pull request #2089 from rswarbrick/modports
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Simplify a modport check in hierarchy.cc
2020-06-08 15:48:11 +02:00
clairexen
fbd0d8d5f0
Merge pull request #2105 from whitequark/split-flatten-off-techmap
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Split `flatten` from `techmap` and simplify it
2020-06-08 15:27:15 +02:00
Marcelina Kościelnicka
28b9f49c94
fsm_extract: avoid calling log_signal to determine wire name
...
log_signal can result in a string with spaces (when bit selection is
involved), which breaks the rule of IdString not containing whitespace.
Instead, remove the sigspec from the name entirely — given that the
resulting wire will have no users, it will be removed later anyway,
so its name doesn't really matter.
Fixes #2118
2020-06-08 03:49:58 +02:00
Eddie Hung
69850204c4
Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improve
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abc9: -dff improvements
2020-06-04 08:15:25 -07:00
whitequark
5a5a9b4ffe
flatten: clean up log messages.
2020-06-04 12:22:59 +00:00
whitequark
d731fe054b
flatten: topologically sort modules.
2020-06-04 12:22:59 +00:00
Eddie Hung
45cd323055
Merge pull request #2082 from YosysHQ/eddie/abc9_scc_fixes
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abc9: fixes around handling combinatorial loops
2020-06-03 17:35:46 -07:00
whitequark
6268bdfe6f
flatten: simplify.
...
`flatten` cannot derive modules in most cases because that would just
yield processes, and it does not support `-autoproc`; in practice
`flatten` has to be preceded by a call to `hierarchy`, which makes
deriving unnecessary.
2020-06-04 00:02:12 +00:00
whitequark
d3e2100306
flatten: simplify. NFC.
...
Remove redundant sigmaps.
2020-06-04 00:02:12 +00:00
whitequark
66255dab4e
flatten: simplify.
...
Flattening does not benefit from topologically sorting cells within
a module when processing them.
2020-06-04 00:02:12 +00:00
whitequark
5d2b6d1394
flatten: simplify. NFC.
...
Flatten is non-recursive and doesn't need to keep track of handled
cells.
2020-06-04 00:02:12 +00:00
whitequark
3c3fa774e5
flatten: simplify. NFC.
...
Flattening always does "non-recursive" mapping.
2020-06-04 00:02:12 +00:00
whitequark
e561a3a76f
flatten: simplify. NFC.
...
The `celltypeMap` always maps `x` to `{x}`.
2020-06-04 00:02:12 +00:00
whitequark
6783876807
flatten: simplify. NFC.
...
The `design` and `map` designs are always the same when flattening.
2020-06-04 00:02:12 +00:00
whitequark
9338ff66b9
RTLIL: factor out RTLIL::Module::addMemory. NFC.
2020-06-04 00:02:12 +00:00
whitequark
ebbbe2156e
flatten: rename techmap-related stuff. NFC.
2020-06-04 00:02:12 +00:00
whitequark
76c4ee4ea5
techmap, flatten: remove dead options.
...
After splitting the passes, some options can never be activated,
and most conditions involving them become dead. Remove them, and also
all of the newly dead code.
2020-06-04 00:02:12 +00:00
whitequark
6ac54a74fe
flatten: split from techmap.
...
Although the two passes started out very similar, they diverged over
time and now have little in common. Moreover, `techmap` is extremely
complex while `flatten` does not have to be, and this complexity
interferes with improving `flatten`.
2020-06-03 15:34:03 +00:00
whitequark
fb5b070e7e
techmap: remove dead variable. NFC.
2020-06-03 01:44:06 +00:00
whitequark
0a74368bfc
techmap: use C++11 default member initializers. NFC.
2020-06-02 23:43:20 +00:00
whitequark
f3e86bb32a
techmap: simplify.
...
`rewrite_filename` is already called in `Frontend::extra_args`.
2020-06-02 23:43:20 +00:00
whitequark
68d747f767
techmap: use +/techmap.v instead of an ad-hoc code generator.
2020-06-02 23:43:20 +00:00
clairexen
ff785cdb46
Merge pull request #1862 from boqwxp/cleanup_techmap
...
Clean up `passes/techmap/techmap.cc`
2020-05-31 20:40:48 +02:00
Eddie Hung
08d9703ecb
abc9_ops: fix comment
2020-05-30 09:01:03 -07:00
Eddie Hung
fe273faad1
Merge pull request #2081 from YosysHQ/eddie/blackbox_ast
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blackbox: use Module::makeblackbox() method
2020-05-30 08:59:20 -07:00
Eddie Hung
ea4374a223
abc9_ops: update messaging (credit to @Xiretza for spotting)
2020-05-30 08:57:48 -07:00
clairexen
ea46ed81f9
Merge pull request #2018 from boqwxp/qbfsat-timeout
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smtbmc and qbfsat: Add timeout option to set solver timeouts for Z3, Yices, and CVC4.
2020-05-30 15:04:51 +02:00
Eddie Hung
b17e8495b8
abc9_ops: optimise to not derive unless attribute exists
2020-05-29 17:33:10 -07:00
Eddie Hung
d3b53bc495
abc9_ops: -reintegrate use SigMap to remove (* init *) from $_DFF_[NP]_
2020-05-29 17:17:40 -07:00
clairexen
94c1035389
Merge pull request #1885 from Xiretza/mod-rem-cells
...
Fix modulo/remainder semantics
2020-05-29 16:37:23 +02:00
clairexen
5874a14d65
Merge pull request #2017 from boqwxp/qbfsat-cvc4
...
qbfsat: Add support for CVC4.
2020-05-29 16:23:10 +02:00
clairexen
1c8d5a08a0
Merge pull request #2016 from boqwxp/qbfsat-yices
...
qbfsat: Add `-solver` option and allow choice of Z3 or Yices, making Yices the default.
2020-05-29 16:21:45 +02:00
Xiretza
edd8ff2c07
Add flooring division operator
...
The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $divfloor cell provides this flooring division.
This commit also fixes the handling of $div in opt_expr, which was
previously optimized as if it was $divfloor.
2020-05-28 22:59:04 +02:00
Xiretza
17163cf43a
Add flooring modulo operator
...
The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $modfloor cell provides this flooring modulo (also known as "remainder"
in several languages, but this name is ambiguous).
This commit also fixes the handling of $mod in opt_expr, which was
previously optimized as if it was $modfloor.
2020-05-28 22:59:03 +02:00
whitequark
0d99522b3c
Merge pull request #2095 from rswarbrick/hier-typo
...
Fix small typos in documentation for hierarchy command
2020-05-28 10:49:14 +00:00
Rupert Swarbrick
1158bbf7db
Fix small typos in documentation for hierarchy command
2020-05-28 11:39:44 +01:00
Alberto Gonzalez
5896ffd56f
printattrs: Simplify `get_indent_str()`.
...
Co-Authored-By: Xiretza <xiretza@xiretza.xyz>
2020-05-28 05:34:28 +00:00
Alberto Gonzalez
f671c99cb8
printattrs: Refactor indentation string building for clarity.
...
Co-Authored-By: whitequark <whitequark@whitequark.org>
2020-05-27 23:15:07 +00:00
Rupert Swarbrick
d681c9df85
Pass some more args by reference in select.cc
...
Before this patch, the code passed around std::string objects by
value. It's probably not a hot-spot, but it can't hurt to avoid the
copying.
Removing the copy and clean-up code means the resulting code is ~6.1kb
smaller when compiled with GCC 9.3 and standard settings.
2020-05-27 09:42:23 +01:00
Rupert Swarbrick
061d1f0c07
Minor optimisations in select.cc's match_ids function
...
- Pass a string argument by reference
- Avoid multiple calls to IdString::str and IdString::c_str
- Avoid combining checks for size > 0 and first char (C strings are
null terminated, so foo[0] != '\0' implies that foo has positive
length)
2020-05-27 09:36:33 +01:00
Rupert Swarbrick
0d9beb5b2e
Silence warning in select.cc
...
With GCC 9.3, at least, compiling select.cc spits out a warning about
an implausible bound being passed to strncmp. This comes from inlining
IdString::compare(): it turns out that passing std::string::npos as a
bound to strncmp triggers it.
This patch replaces the compare call with a memcmp with the same
effect. The repeated calls to IdString::c_str are slightly
inefficient, but I'll address that in a follow-up commit.
2020-05-27 09:34:15 +01:00
Alberto Gonzalez
e50e4ee285
printattrs: Use `flags` to pretty-print the `RTLIL::Const` appropriately.
...
Co-Authored-By: whitequark <whitequark@whitequark.org>
2020-05-27 08:00:00 +00:00
Alberto Gonzalez
b8365547e9
misc: Add `printattrs` command.
2020-05-27 08:00:00 +00:00
Rupert Swarbrick
7746bba69a
Simplify a modport check in hierarchy.cc
...
This code originally comes from commit 458a940
. When an interface is
used via a modport, code in genrtlil.cc sets '\\interface_type' and
'\\interface_modport' properties on the wire.
In hierarchy.cc, we pick up the modport name and add it to a dict
called modports_used_in_submodule (that maps connection source to
modport name).
Before this patch, the modport name is retrieved as a strpool and then
iterated over in an arbitrary order, discarding all entries but the
last. In practice, the pool will always have 0 or 1 entries because
the string used to construct it is a valid identifier, so doesn't
contain any pipe symbols.
This patch changes the code to retrieve the modport name as just a
string. This will have the same effect in practice, but may be a bit
less confusing!
The code also gets moved down closer to where the result is used,
which might be a bit more efficient since we won't always get as far
as the check.
The patch also removes some commented-out code, which I think was
intended to add some typechecking at some point, but was never
implemented. Since this dates back to October 2018, I think it makes
more sense to just take it out.
2020-05-26 16:50:42 +01:00
Eddie Hung
00c5ceb1f2
abc9_ops: -prep_xaiger exclude (* abc9_keep *) wires from toposort
2020-05-25 16:40:53 -07:00
Alberto Gonzalez
9847a4eea8
smtbmc and qbfsat: Add timeout option to set solver timeouts for Z3, Yices, and CVC4.
2020-05-25 20:39:30 +00:00
Alberto Gonzalez
f9eef5e3f7
qbfsat: Add support for CVC4.
2020-05-25 20:39:03 +00:00
Alberto Gonzalez
903456c267
qbfsat: Add `-solver` option and allow choice of Z3 or Yices, making Yices the default.
...
Ensures that "BV" is the logic whenever solving an exists-forall problem with Yices, moves the "(set-logic ...)" directive above any non-info line, sets the `ef-max-iters` parameter to a very high number when using Yices in exists-forall mode so as not to prematurely abandon difficult problems, and does not provide the incompatible "--incremental" Yices argument when in exists-forall mode.
2020-05-25 20:38:29 +00:00
Eddie Hung
721283ac2a
blackbox: re-use existing Module::makeblackbox() method
2020-05-25 10:53:49 -07:00
Eddie Hung
7bad23f19c
abc9_ops: -reintegrate to preserve flop names
2020-05-25 08:43:33 -07:00
clairexen
ae11156c90
Merge pull request #2015 from boqwxp/qbfsat-bisection
...
qbfsat: Add an iterative bisection optimization method and make it the default.
2020-05-25 15:50:18 +02:00
Alberto Gonzalez
ac41f8a9c7
qbfsat: Remove cruft inadvertently left untouched in commit 86fc49a9d6
.
2020-05-23 00:53:09 +00:00
Alberto Gonzalez
aea0fd5ed4
qbfsat: Add bisection mode and make it the default.
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Also adds `-nooptimize` and reorganizes `qbfsat.cc` a bit.
2020-05-23 00:53:09 +00:00
Eddie Hung
4f0f321169
abc9_ops: update comment
2020-05-21 21:39:13 -07:00
Miodrag Milanović
637650597b
Merge pull request #2059 from boqwxp/logger-vector-to-dict
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log: Use `dict` instead of `std::vector<std::pair>` for `log_expect_{error, warning, log}` to better express the intent that each element is unique.
2020-05-21 15:36:30 +02:00
Eddie Hung
2d573a0ff6
Merge pull request #1926 from YosysHQ/eddie/abc9_auto_dff
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abc9: support seq synthesis when module has (* abc9_flop *) and bypass non-combinatorial (* abc9_box *)
2020-05-18 08:06:50 -07:00
Alberto Gonzalez
8297afe925
log: Use `dict` instead of `std::vector<std::pair>` for `log_expect_{error, warning, log}` to better express the intent that each element is unique.
2020-05-15 00:55:32 +00:00
Eddie Hung
67fc0c3698
abc9: use (* abc9_keep *) instead of (* abc9_scc *); apply to $_DFF_?_
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instead of moving them to $__ prefix
2020-05-14 16:44:35 -07:00
Eddie Hung
07eecff9cc
Merge pull request #2055 from YosysHQ/eddie/logger_multiple
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logger: fix for multiple calls with same pattern
2020-05-14 15:30:08 -07:00
Alberto Gonzalez
e173291649
techmap: Replace naughty `const_cast<>()`s.
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Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
2020-05-14 20:06:55 +00:00
Alberto Gonzalez
97fd304cbe
techmap: Replace pseudo-private member usage with the range accessor function and some naughty `const_cast<>()`s.
2020-05-14 20:06:55 +00:00
Eddie Hung
36bb201dd9
techmap: sort celltypeMap as it determines techmap order
2020-05-14 20:06:55 +00:00
Alberto Gonzalez
ce62d0751a
Replace `std::set`s using custom comparators with `pool`.
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Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
2020-05-14 20:06:55 +00:00
Eddie Hung
dabeb1e8a1
techmap: prefix special wires with backslash for use as IdString
2020-05-14 20:06:55 +00:00
Alberto Gonzalez
bd54d67ad4
Further clean up `passes/techmap/techmap.cc`.
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Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
2020-05-14 20:06:54 +00:00
Alberto Gonzalez
982562ff13
Use `emplace()` for more efficient insertion into various `dict`s.
2020-05-14 20:06:54 +00:00
Alberto Gonzalez
c658d9d59d
Build constant bits directly rather than constructing an object and copying its bits.
2020-05-14 20:06:54 +00:00
Alberto Gonzalez
f235f212ea
Replace `std::set` with `pool` for `cell_to_inbit` and `outbit_to_cell`.
2020-05-14 20:06:54 +00:00
Alberto Gonzalez
6294621825
Use `emplace()` rather than `insert()`.
2020-05-14 20:06:54 +00:00
Alberto Gonzalez
dfcb936cd5
Clean up pseudo-private member usage and ensure range iteration uses references where possible to avoid unnecessary copies.
2020-05-14 20:06:54 +00:00
Alberto Gonzalez
a4755c50c3
Clean up extraneous buffer.
2020-05-14 20:06:54 +00:00
Alberto Gonzalez
7857782575
Replace `std::map` with `dict` for `unique_bit_id`.
2020-05-14 20:06:54 +00:00
Alberto Gonzalez
6d64d768b0
Replace `std::map` with `dict` for `port_new2old_map`, `port_connmap`, and `cellbits_to_tplbits`.
2020-05-14 20:06:54 +00:00
Alberto Gonzalez
5cb4ae4666
Replace `std::map` with `dict` for `connbits_map`, `cell_to_inbit`, and `outbit_to_cell`.
2020-05-14 20:06:54 +00:00
Alberto Gonzalez
c43017fc08
Replace `std::map` with `dict` for `TechmapWires` type.
2020-05-14 20:06:54 +00:00
Alberto Gonzalez
644e55b3d3
Replace `std::map` with `dict` for `celltypeMap`.
2020-05-14 20:06:53 +00:00
Alberto Gonzalez
67f4046c05
Replace `std::set` with `pool` for `handled_cells` and `techmap_wire_names`.
2020-05-14 20:06:53 +00:00
Alberto Gonzalez
64c16f8c13
Replace `std::map` with `dict` for `positional_ports`.
2020-05-14 20:06:53 +00:00
Alberto Gonzalez
2fb4931e5b
Add specialized `hash()` for type `dict` and use a `dict` instead of a `std::map` for `techmap_cache` and `techmap_do_cache`.
2020-05-14 20:06:53 +00:00
Alberto Gonzalez
437f3fb342
Replace `std::map` with `dict` for `simplemap_mappers`.
2020-05-14 20:06:53 +00:00
Alberto Gonzalez
99b586b283
Use `nullptr` instead of `NULL` in `passes/techmap/techmap.cc`.
2020-05-14 20:06:53 +00:00
Alberto Gonzalez
5f7f213c7f
Replace `std::string` and `RTLIL::IdString` with `IdString` in `passes/techmap/techmap.cc`.
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Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
2020-05-14 20:06:53 +00:00
Alberto Gonzalez
e49fdee404
Do not modify design modules while iterating over `modules()`.
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Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
2020-05-14 20:06:53 +00:00
Alberto Gonzalez
985a29ff3b
Clean up pseudo-private member usage, superfluous `std::vector` instantiation, and `RTLIL::id2cstr()` usage in `passes/techmap/techmap.cc`.
2020-05-14 20:06:53 +00:00
Eddie Hung
7b3a4a1fff
opt_expr: Sx to Sz; spotted by @Xiretza
2020-05-14 12:14:23 -07:00
Eddie Hung
73b7ea713c
Merge pull request #1994 from YosysHQ/eddie/fix_bug1758
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opt_expr: improve single-bit $and/$or/$xor/$xnor cells; gate cells too
2020-05-14 11:56:22 -07:00
Eddie Hung
425867d175
logger: clean up doc
2020-05-14 10:38:31 -07:00