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290 Commits

Author SHA1 Message Date
Clifford Wolf 4c733301e6 Fixed cstr_buf for std::string with small string optimization 2015-06-11 13:39:49 +02:00
Clifford Wolf 3a6abc9bf6 Improvements in cellaigs.cc and "json -aig" 2015-06-11 10:48:16 +02:00
Clifford Wolf 1ae360cf72 AigMaker refactoring 2015-06-10 23:00:12 +02:00
Clifford Wolf e534881794 Added "json -aig" 2015-06-10 08:13:56 +02:00
luke whittlesey 2f90499e3d $mem cell in verilog backend : grouped writes by clock 2015-06-08 17:35:40 -04:00
luke whittlesey a8fe040906 Bug fix in $mem verilog backend + changed tests/bram flow of make test. 2015-06-04 16:12:40 -04:00
Clifford Wolf 08a4af3cde Improvements in BLIF front-end 2015-05-24 08:03:21 +02:00
Clifford Wolf 4744bb95fb Some fixes for $mem in verilog back-end 2015-05-20 13:55:50 +02:00
Clifford Wolf 42348cddd9 Merge pull request #63 from wluker/verilog-backend-mem 
Fixed bug in $mem cell verilog code generation.
 2015-05-11 21:38:06 +02:00
luke whittlesey 3bb5f064b8 Fixed bug in $mem cell verilog code generation. 2015-05-11 14:05:18 -04:00
Clifford Wolf 9e56739634 Disabled broken $mem support in verilog backend 2015-05-10 21:38:41 +02:00
luke whittlesey 6de8fea2c7 Made changes recommended by Clifford Wolf ... 
Removed bit_check_equal(), used RTLIL::SigBit for individual bits, used
dict<> instead of std::map, and used RTLIL::SigSpec instead of
std::vector.
 2015-05-10 11:33:24 -04:00
luke whittlesey 2c1e150297 Verilog backend for $mem cells should now be able to handle different 
write-enable bits and RD_TRANSPARENT parameter settings.
 2015-05-08 15:29:51 -04:00
luke whittlesey c0b68f4848 Added support for $mem cells in the verilog backend. 2015-05-07 13:03:09 -04:00
eddiehung 7c62318239 Fix for all zero mask 2015-05-03 12:53:09 +01:00
eddiehung 079c1205fe Escape '<' and '>' some more 2015-05-03 10:37:20 +01:00
eddiehung 872e13321c For vtr, escape angle brackets as well 2015-04-28 08:56:00 +01:00
eddiehung 058deb777e blifwriter: write out .names for true/false/undef type == '-' 2015-04-28 08:55:26 +01:00
Clifford Wolf d176e613c2 Minor fixes in handling of "init" attribute 2015-04-09 15:12:26 +02:00
Clifford Wolf aa0ab975b9 Removed "techmap -share_map" (use "-map +/filename" instead) 2015-04-08 12:13:53 +02:00
Clifford Wolf c0e2b3eb11 Added "port_directions" to write_json output 2015-04-06 01:49:58 +02:00
Clifford Wolf b0c0ede879 Added "init" attribute support to verilog backend 2015-04-04 18:06:52 +02:00
Ahmed Irfan 13e2e71ebe Update README 
corrected url
 2015-04-03 17:11:45 +02:00
Ahmed Irfan ed750f0a55 Delete btor.ys 
.ys script not needed
 2015-04-03 16:45:54 +02:00
Ahmed Irfan e82e4f7df4 Update README 
pmux cell is implemented
 2015-04-03 16:45:14 +02:00
Ahmed Irfan ea2e0297d5 separated memory next from write cell 2015-04-03 16:41:50 +02:00
Clifford Wolf 67e6dcd34a Added Verilog backend $dffsr support 2015-03-18 08:01:37 +01:00
Clifford Wolf 6c8fdb1829 Documentation for JSON format, added attributes 2015-03-06 10:21:21 +01:00
Clifford Wolf adc12ce46e Json bugfix 2015-03-03 09:41:41 +01:00
Clifford Wolf 4fc63f27a1 Json backend improvements 2015-03-03 09:28:44 +01:00
Clifford Wolf 795a6e1d04 Added write_blif -attr 2015-03-02 23:47:45 +01:00
Clifford Wolf 8b488983d0 Added JSON backend 2015-03-02 23:30:58 +01:00
Clifford Wolf 5d4f513c3b Added $assume support to write_smt2 2015-02-26 19:02:55 +01:00
Clifford Wolf ff3f2448b1 Minor "write_smt2" help msg change 2015-02-22 16:30:02 +01:00
Clifford Wolf 4b89dd983c Added "<mod>_a" and "<mod>_i" to write_smt2 output 2015-02-22 16:19:10 +01:00
Clifford Wolf 756b4064b2 Fixed "write_verilog -attr2comment" handling of "*/" in strings 2015-02-13 22:48:10 +01:00
Clifford Wolf 6978f3a77b Added EDIF backend support for multi-bit cell ports 2015-02-01 15:43:35 +01:00
Clifford Wolf fb8c755726 Shorter "dump" options 2015-01-31 23:52:36 +01:00
Clifford Wolf 2a9ad48eb6 Added ENABLE_NDEBUG makefile options 2015-01-24 12:16:46 +01:00
Clifford Wolf 43951099cf Added dict/pool.sort() 2015-01-24 00:13:27 +01:00
Clifford Wolf 146f769bee Cosmetic changes in verilog output format 2015-01-02 22:57:08 +01:00
Clifford Wolf eefe78be09 Fixed memory->start_offset handling 2015-01-01 12:56:01 +01:00
Clifford Wolf 9e6fb0b02c Replaced std::unordered_map as implementation for Yosys::dict 2014-12-26 21:35:22 +01:00
Clifford Wolf a6c96b986b Added Yosys::{dict,nodict,vector} container types 2014-12-26 10:53:21 +01:00
Clifford Wolf e8c12e5f0c Various fixes and improvements in "write_smt2 -bv" 2014-12-25 20:28:34 +01:00
Clifford Wolf 68233baa1f Various fixes and improvements in write_smt2 2014-12-25 17:52:31 +01:00
Clifford Wolf 95f17dbab0 Added support for most BV cell types to write_smt2 2014-12-25 15:37:02 +01:00
Clifford Wolf 1c3d51375f Added "write_smt2 -bv" and other write_smt2 improvements 2014-12-25 13:30:20 +01:00
Clifford Wolf e548483c91 Added write_smt2 (only gate level logic supported so far) 2014-12-24 16:17:57 +01:00
Clifford Wolf edb3c9d0c4 Renamed extend() to extend_xx(), changed most users to extend_u0() 2014-12-24 09:51:17 +01:00
Clifford Wolf 5df192e71c Added $dffe support to write_verilog 2014-12-20 00:03:20 +01:00
Clifford Wolf 30de490d86 Fixed another bug in write_blif handling of $lut cells 2014-12-19 17:54:44 +01:00
Clifford Wolf b95051fb70 Fixed writing of $lut cells in BLIF backend 2014-12-17 11:13:57 +01:00
Clifford Wolf e01254d824 Added "write_blif -undef" and support for special "-" true/false/undef type 2014-12-14 18:00:38 +01:00
Clifford Wolf 59d11978fc Added "write_blif -blackbox" 
based on code by Eddie Hung from
https://github.com/eddiehung/yosys/commit/1e481661cb4a4
 2014-12-14 17:45:03 +01:00
Clifford Wolf 32dce4a870 Added "blif -unbuf" feature 2014-12-14 17:37:46 +01:00
Clifford Wolf fe829bdbdc Added log_warning() API 2014-11-09 10:44:23 +01:00
Clifford Wolf 461594bb83 Fixed generation of temp names in verilog backend 2014-11-07 14:40:06 +01:00
Clifford Wolf 4569a747f8 Renamed SIZE() to GetSize() because of name collision on Win32 2014-10-10 17:07:24 +02:00
Clifford Wolf f9a307a50b namespace Yosys 2014-09-27 16:17:53 +02:00
Ahmed Irfan d3c67ad9b6 Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor 
added case for memwr cell that is used in muxes (same cell is used more than one time)
corrected bug for xnor and logic_not
added pmux cell translation

Conflicts:
	backends/btor/btor.cc
 2014-09-22 11:35:04 +02:00
Clifford Wolf 309623ff17 Sorting of object names in ilang backend 2014-09-19 15:50:34 +02:00
ahmedirfan1983 b783dbe148 fixed memory next issue, when same memory is written in different case statement 
fixed reduce_xnor, logic_not bug translation bug
 2014-09-18 11:19:48 +02:00
Clifford Wolf 9329a76818 Various bug fixes (related to $macc model testing) 2014-09-06 20:30:46 +02:00
Ruben Undheim 79cbf9067c Corrected spelling mistakes found by lintian 2014-09-06 08:47:06 +02:00
Clifford Wolf 8927aa6148 Removed $bu0 cell type 2014-09-04 02:07:52 +02:00
Clifford Wolf b9cb483f3e Using $pos models for $bu0 2014-09-03 21:20:59 +02:00
Ahmed Irfan 2446b6fbef added $pmux cell translation 2014-09-02 14:47:51 +02:00
Clifford Wolf e07698818d Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::data 2014-09-01 11:36:02 +02:00
Clifford Wolf 19cff41eb4 Changed frontend-api from FILE to std::istream 2014-08-23 15:03:55 +02:00
Clifford Wolf 5dce303a2a Changed backend-api from FILE to std::ostream 2014-08-23 13:54:21 +02:00
Clifford Wolf f82c978e08 Fixed AOI/OAI expr handling in verilog backend 2014-08-16 22:05:09 +02:00
Clifford Wolf 47c2637a96 Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_ 2014-08-16 18:29:39 +02:00
Clifford Wolf b64b38eea2 Renamed $lut ports to follow A-Y naming scheme 2014-08-15 14:18:40 +02:00
Clifford Wolf f092b50148 Renamed $_INV_ cell type to $_NOT_ 2014-08-15 14:11:40 +02:00
Clifford Wolf 746aac540b Refactoring of CellType class 2014-08-14 15:46:51 +02:00
Clifford Wolf 88cf00ce78 Be more conservative with printing decimal numbers in verilog backend 2014-08-02 21:54:02 +02:00
Clifford Wolf ca1b5d50e0 Improved verilog output for ordinary $mux cells 2014-08-02 21:10:08 +02:00
Clifford Wolf 04727c7e0f No implicit conversion from IdString to anything else 2014-08-02 18:58:40 +02:00
Clifford Wolf b9bd22b8c8 More cleanups related to RTLIL::IdString usage 2014-08-02 13:19:57 +02:00
Clifford Wolf cdae8abe16 Renamed port access function on RTLIL::Cell, added param access functions 2014-07-31 16:38:54 +02:00
Clifford Wolf 1cb25c05b3 Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace 2014-07-31 13:19:47 +02:00
Clifford Wolf e6df25bf74 Renamed "write_autotest" to "test_autotb" and moved to passes/tests/ 2014-07-29 21:12:50 +02:00
Clifford Wolf 397b00252d Added $shift and $shiftx cell types (needed for correct part select behavior) 2014-07-29 16:35:13 +02:00
Clifford Wolf 27a872d1e7 Added support for "upto" wires to Verilog front- and back-end 2014-07-28 14:25:03 +02:00
Clifford Wolf 3c45277ee0 Added wire->upto flag for signals such as "wire [0:7] x;" 2014-07-28 12:12:13 +02:00
Clifford Wolf 7bd2d1064f Using log_assert() instead of assert() 2014-07-28 11:27:48 +02:00
Clifford Wolf 10e5791c5e Refactoring: Renamed RTLIL::Design::modules to modules_ 2014-07-27 11:18:30 +02:00
Clifford Wolf 4c4b602156 Refactoring: Renamed RTLIL::Module::cells to cells_ 2014-07-27 01:51:45 +02:00
Clifford Wolf f9946232ad Refactoring: Renamed RTLIL::Module::wires to wires_ 2014-07-27 01:49:51 +02:00
Clifford Wolf 3f4e3ca8ad More RTLIL::Cell API usage cleanups 2014-07-26 16:14:02 +02:00
Clifford Wolf 97a59851a6 Added RTLIL::Cell::has(portname) 2014-07-26 16:11:28 +02:00
Clifford Wolf f8fdc47d33 Manual fixes for new cell connections API 2014-07-26 15:58:23 +02:00
Clifford Wolf b7dda72302 Changed users of cell->connections_ to the new API (sed command) 
git grep -l 'connections_' | xargs sed -i -r -e '
	s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
	s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
	s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
	s/(->|\.)connections_.push_back/\1connect/g;
	s/(->|\.)connections_/\1connections()/g;'
 2014-07-26 15:58:23 +02:00
Clifford Wolf cc4f10883b Renamed RTLIL::{Module,Cell}::connections to connections_ 2014-07-26 11:58:03 +02:00
Clifford Wolf 5826670009 Various RTLIL::SigSpec related code cleanups 2014-07-25 14:25:42 +02:00
Clifford Wolf 6aa792c864 Replaced more old SigChunk programming patterns 2014-07-24 23:10:58 +02:00
Clifford Wolf c094c53de8 Removed RTLIL::SigSpec::optimize() 2014-07-23 20:32:28 +02:00
Clifford Wolf a62c21c9c6 Removed RTLIL::SigSpec::expand() method 2014-07-23 19:34:51 +02:00
Clifford Wolf ec923652e2 Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3 2014-07-23 09:52:55 +02:00
Clifford Wolf a8d3a68971 Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3 2014-07-23 09:49:43 +02:00
Clifford Wolf 28b3fd05fa SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw() 2014-07-22 20:58:44 +02:00
Clifford Wolf 4b4048bc5f SigSpec refactoring: using the accessor functions everywhere 2014-07-22 20:39:37 +02:00
Clifford Wolf a233762a81 SigSpec refactoring: renamed chunks and width to __chunks and __width 2014-07-22 20:39:37 +02:00
Clifford Wolf 4147b55c23 Added "autoidx" statement to ilang file format 2014-07-21 15:15:18 +02:00
Clifford Wolf a30e2857c7 Use functions instead of always blocks for $mux/$pmux/$safe_pmux in verilog backend 2014-07-20 02:16:30 +02:00
Clifford Wolf 0c67393313 Added support for $bu0 to verilog backend 2014-07-20 01:56:16 +02:00
Clifford Wolf fad8558eb5 Merged OSX fixes from Siesh1oo with some modifications 2014-03-13 12:48:10 +01:00
Clifford Wolf f7bd0a5232 Use log_abort() and log_assert() in BTOR backend 2014-03-07 15:56:10 +01:00
Clifford Wolf 337b461d26 Added $lut support to blif backend (by user eddiehung from reddit) 2014-02-22 14:25:32 +01:00
Clifford Wolf 038eac7414 Better handling of nameDef and nameRef in edif backend 2014-02-21 13:40:43 +01:00
Clifford Wolf f3ff29d410 Fixed instantiating multi-bit ports in edif backend 2014-02-21 13:10:36 +01:00
Clifford Wolf 79f8944811 Renamed "write_blif -subckt" to "write_blif -icells" and added -gates and -param 2014-02-21 10:40:15 +01:00
Ahmed Irfan ac896c63e2 modified btor synthesis script for correct use of splice command. 2014-02-12 13:38:28 +01:00
Ahmed Irfan 45e468114a disabling splice command in the script 2014-02-11 15:43:03 +01:00
Ahmed Irfan 1d64b3e008 register output corrected 2014-02-11 13:28:05 +01:00
Ahmed Irfan e8f6b8f201 added concat and slice cell translation 2014-02-11 13:06:01 +01:00
Clifford Wolf fc3b3c4ec3 Added $slice and $concat cell types 2014-02-07 17:44:57 +01:00
Clifford Wolf f4f230d7cc Fixed gcc compiler warnings with release build 2014-02-06 22:49:14 +01:00
Clifford Wolf 583636f0ad Added BTOR backend README file 2014-02-05 18:31:10 +01:00
Clifford Wolf 968ae31cac Added support for dump -append 2014-02-04 23:45:30 +01:00
Clifford Wolf a6750b3753 Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem) 2014-02-03 13:01:45 +01:00
Clifford Wolf fa103e55ad Merge branch 'btor' of https://github.com/ahmedirfan1983/yosys 2014-01-26 02:29:19 +01:00
Johann Glaser f13b3518aa beautified write_intersynth 2014-01-25 20:16:38 +01:00
Ahmed Irfan 0325efe172 root bug corrected 2014-01-25 19:33:24 +01:00
Ahmed Irfan 137742786e removed regex include 2014-01-24 18:04:37 +01:00
Ahmed Irfan 2e44b1b73a merged clifford changes + removed regex 2014-01-24 17:35:42 +01:00
Clifford Wolf 210dda286f Use techmap -share_map in btor scripts 2014-01-24 15:52:16 +01:00
Clifford Wolf 6804edd5d4 Moved btor scripts to backends/btor/ 2014-01-24 15:48:07 +01:00
Ahmed Irfan aa3cb20e1e slice bug corrected 2014-01-20 18:35:52 +01:00
Ahmed Irfan c347f2825f assert feature 2014-01-20 10:45:02 +01:00
Ahmed Irfan 9a689f33a5 verilog default options pull 
shift operator width issues
 2014-01-17 19:32:35 +01:00
Ahmed Irfan c7a2e582aa slice error corrected 2014-01-16 20:16:01 +01:00
Ahmed Irfan 3a1490888d width issues 
dff cell for more than one registers
 2014-01-15 17:36:33 +01:00
Ahmed Irfan 661b5a993e BTOR backend 2014-01-14 12:03:53 +01:00
Ahmed Irfan 06482c046b Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor 2014-01-03 10:54:54 +01:00
Ahmed Irfan ffd768ce86 btor 2014-01-03 10:52:44 +01:00
Clifford Wolf 74d0de3b74 Updated manual/command-reference-manual.tex 2013-12-28 12:14:47 +01:00
Clifford Wolf 369bf81a70 Added support for non-const === and !== (for miter circuits) 2013-12-27 14:20:15 +01:00
Clifford Wolf f4b46ed31e Replaced signed_parameters API with CONST_FLAG_SIGNED 2013-12-04 14:24:44 +01:00
Clifford Wolf 93a70959f3 Replaced RTLIL::Const::str with generic decoder method 2013-12-04 14:14:05 +01:00
Clifford Wolf b5afd75b0a Fixed gentb_constant handling in autotest backend 2013-12-04 09:09:42 +01:00
Clifford Wolf ed441346ca Added dump -m and -n options 2013-11-29 10:33:36 +01:00
Clifford Wolf 41205afc39 Added proper dumping of signed/unsigned parameters to verilog backend 2013-11-24 17:47:22 +01:00
Clifford Wolf 0ef22c7609 Added support for signed parameters in ilang 2013-11-24 17:37:27 +01:00
Clifford Wolf f71e27dbf1 Remove auto_wire framework (smarter than the verilog standard) 2013-11-24 17:29:11 +01:00
Clifford Wolf 1e6836933d Added modelsim support to autotest 2013-11-24 15:10:43 +01:00
Clifford Wolf 28093d9dd2 Added "top" attribute to mark top module in hierarchy 2013-11-24 05:03:43 +01:00
Clifford Wolf 295e352ba6 Renamed "placeholder" to "blackbox" 2013-11-22 15:01:12 +01:00
Clifford Wolf 40d9542647 Implemented $_DFFSR_ expression generator in verilog backend 2013-11-21 21:52:30 +01:00