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caravel
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  • 6570429234 Continued work on the power routing. Also updated the management core wrapper view with the LEF view from caravel_pico. Tim Edwards 2021-11-20 22:04:46 -0500
  • 8f75362f82 Start of power routing. Tim Edwards 2021-11-20 18:04:43 -0500
  • b0d3217280 Replaced the gpio_defaults_block_0000.mag layout with gpio_defaults_block.mag so that it contains a valid layout after processing by Openlane (since the verilog module is named gpio_defaults_block). Corrected the orientation of the defaults block layouts on the right side of Caravel and erased the incorrect routing there. Reinstated the copyright, user ID text, open source logo, and Caravel logo. Revised the gen_gpio_defaults.py script to handle the first five GPIOs in the same way as the others, although as fixed entries which cannot be modified by the user project designer. Tim Edwards 2021-11-20 13:43:49 -0500
  • 1c18c1dae9 [DATA] Update caravel manarabdelaty 2021-11-20 17:28:59 +0200
  • 331fdee2bb [DATA] Update HK module (li1 routing: 249um) manarabdelaty 2021-11-20 15:13:16 +0200
  • 5cd3843f00 [DATA] Update gpio_control_block (li1 used 2um) manarabdelaty 2021-11-20 14:43:20 +0200
  • 37fb2d6766 [DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1) manarabdelaty 2021-11-20 13:06:23 +0200
  • ededa9ed35 [DATA] Update caravel layout with the latest views for the mgmt_protect and mgmt_core manarabdelaty 2021-11-19 16:51:28 +0200
  • 866755f228 [DATA] Update mgmt_protect mag/gds to remove the shorted power nets manarabdelaty 2021-11-19 15:50:36 +0200
  • bf6ad67934 [DATA] Update gpio_control_block pin order to fix shorts at the top level manarabdelaty 2021-11-19 13:13:24 +0200
  • 581a22de6a [DATA] Update mgmt_protect (removed all li1 routing ) manarabdelaty 2021-11-19 13:11:18 +0200
  • 2574eada93 [DATA] Add initial caravel layout manarabdelaty 2021-11-19 01:35:11 +0200
  • 61bf3c651e [DATA] Update mgmt_protect pin placement manarabdelaty 2021-11-19 01:33:11 +0200
  • 53b3a9013e [DATA] Update HK pin placement manarabdelaty 2021-11-19 01:30:14 +0200
  • 37a07e291b [DATA] Update digital_pll pin placement to have it align with the HK manarabdelaty 2021-11-19 01:28:40 +0200
  • 64bdd6230d [DATA] Update caravel_clocking module floorplan manarabdelaty 2021-11-19 01:26:29 +0200
  • abc8031729 Merge branch 'main' of https://github.com/efabless/caravel_openframe into main manarabdelaty 2021-11-18 15:28:25 +0200
  • 488d8fc5bb Fixed another missing line from the management protect block call in caravel.v. Tim Edwards 2021-11-18 08:25:13 -0500
  • b71c8bbb36 Merge branch 'main' of https://github.com/efabless/caravel_openframe into main manarabdelaty 2021-11-17 21:09:58 +0200
  • 7b82c143b7 Fixed two signals on the mgmt_protect in caravel that got merged and scrambled somehow. Tim Edwards 2021-11-17 14:08:47 -0500
  • 96ef5c83fd Corrected the corner pad connections to vssd and vccd, which were still pointing to vssd1/vccd1/vssd2/vccd2, variously in chip_io.v and chip_io_alt.v Tim Edwards 2021-11-17 11:44:32 -0500
  • 3cc88cd7fd Add USE POWER/USE GROUND properties to the simple_port lef view manarabdelaty 2021-11-17 17:57:23 +0200
  • 979d34b7a9 Merge branch 'main' of https://github.com/efabless/caravel_openframe into main manarabdelaty 2021-11-17 16:43:59 +0200
  • 1f55f46596 [DATA] Add chip_io views with the fixed clamped3 pad manarabdelaty 2021-11-17 16:42:36 +0200
  • 5f1a0029f5 Made the same corrections to caravan as were made to caravel (clock -> clock_core in caravel_clocking, VPWR -> vccd_core and VGND -> vssd_core in the instances of modules that were pulled from the management SoC to the top level). Tim Edwards 2021-11-17 09:06:42 -0500
  • b5fe87304a [RTL] Fix power connection to HK/digital_pll/caravel clocking, also fix resetb connection manarabdelaty 2021-11-17 13:17:23 +0200
  • 1b300d7b59 [DATA] Add digital user project wrapper manarabdelaty 2021-11-17 13:13:11 +0200
  • d7ae2e1ac1 [RTL] Move inverter from top level to HK manarabdelaty 2021-11-16 13:59:17 +0200
  • bb1c9fe528 Removed two references for single-macro verilog files that are no longer in the PDK but have been folded into larger library files. With the most recent push to open_pdks to fix an error in the I/O verilog library, the verilog testbenches once again pass. Tim Edwards 2021-11-15 17:53:48 -0500
  • 559675d392 Corrected chip_io and chip_io_alt layouts to restore the accidentally deleted "resetb_core_h" port label. Corrected the chip_io and chip_io_alt verilog RTL files to replace the user area power supply clamp cells with the new clamped3 cell from open_pdks. Tim Edwards 2021-11-15 17:13:43 -0500
  • f18a219be4 Modified the set_user_id script so that if it happens to be run on a repository where the user_id_programming GDS has been compressed, it will handle it correctly. Tim Edwards 2021-11-15 16:41:04 -0500
  • 098b4befb2 Add gds view for chip_io manarabdelaty 2021-11-15 23:02:01 +0200
  • a5dbe91965 Merge branch 'main' of https://github.com/efabless/caravel_openframe into main manarabdelaty 2021-11-15 21:19:43 +0200
  • f28950695d Made adjustments to the padframe routing to move all routes closer to the padframe and free up more space for routing in the chip interior. Tim Edwards 2021-11-15 11:52:08 -0500
  • 46540437af [DATA] Add gds/lef/maglef/gl views for the user_id_programming block manarabdelaty 2021-11-15 18:17:32 +0200
  • 10cf11fbf5 Add gds/lef views for simple_por manarabdelaty 2021-11-15 18:08:22 +0200
  • 6203460f57 [DATA] Add views for xres_buf manarabdelaty 2021-11-15 18:07:02 +0200
  • aefa72281c Added the files for the simple_por block design, and placed the latest hardened macro components into the caravel and caravan layouts. Tim Edwards 2021-11-15 10:34:52 -0500
  • 72b2c724c9 [DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz manarabdelaty 2021-11-15 15:50:43 +0200
  • 4c9f7630ff Merge branch 'main' of https://github.com/efabless/caravel_openframe into main manarabdelaty 2021-11-15 13:24:42 +0200
  • 56f672bbd8 [DATA] Add HK views manarabdelaty 2021-11-15 13:23:54 +0200
  • 85a1ffc5aa [DATA] Add views for the mgmt_protect manarabdelaty 2021-11-13 12:34:33 +0200
  • 67e48e53c5 Corrected minor DRC errors around the padframe cell and in the new caravan logo layout. Current design is DRC clean with the new open_pdks maglef views of the I/O cells. Tim Edwards 2021-11-12 16:12:12 -0500
  • 46dd9493f6 Removed some vestiges of top-level routing that were left over from the previous version of the caravel and caravan layouts. Tim Edwards 2021-11-12 13:45:58 -0500
  • d5ef31e391 Added an empty management core wrapper to the caravel top level. Tim Edwards 2021-11-12 12:17:52 -0500
  • 856539ca59 Update storage testbench to work with one 2K block manarabdelaty 2021-11-12 17:14:21 +0200
  • 112ed53751 Modified the Makefile so that "make lvs-gds-" works better (maybe not perfectly) when run on chip-io or anything with a pad cell. Tim Edwards 2021-11-11 08:48:14 -0500
  • 27fdba364b Added user 1.8V power supply rails to the chip_io and chip_io_alt layouts. Because the 1.8V domains are no longer within the pad ring buses, they need to be connected together in the cell. These internal lines were previously in the power routing cells. Tim Edwards 2021-11-10 17:13:43 -0500
  • 7820f7a969 Updated the floorplan. Tim Edwards 2021-11-10 12:21:22 -0500
  • 38dbd8d5d9 Added logo graphic for Caravan. Tim Edwards 2021-11-09 22:47:31 -0500
  • 8da7d5124b Added a logo for Caravel. Tim Edwards 2021-11-09 17:18:20 -0500
  • 89bb33fbc0 Merge branch 'main' of https://github.com/efabless/caravel_openframe into main manarabdelaty 2021-11-08 13:35:16 +0200
  • bee7b4ed78 Add initial config for the digital_pll manarabdelaty 2021-11-08 13:34:59 +0200
  • 4a27ea4c6b Finished first draft of the gen_gpio_defaults.py script, which now makes backup copies of caravel and caravan layouts and replaces the cell name of any gpio defaults block that is changed from the contents of user_defines.v. NOTE: user_defines.v ultimately must reside in the user project. The Makefile should copy the user's version into the caravel directory space before running the script, or else the script should be rewritten to reference the user's project area when reading user_defines.v. Tim Edwards 2021-11-07 21:51:00 -0500
  • 27e0c94997 Added caravan top level and seeded with the GPIO control blocks, default blocks, and updated copyright. Tim Edwards 2021-11-06 22:34:49 -0400
  • cd906cbf8a Updated the copyright block for the new designs. Added caravel layout and placed the GPIO control blocks and default blocks. Tim Edwards 2021-11-06 22:13:19 -0400
  • 6a93ea582d Added a script which parses the file "user_defines.v" in verilog/rtl/, and creates all the layout files needed to represent all unique combinations of defaults used in the file. Not done: Modifying the top level layout to use the correct defaults (because the top level layout does not yet exist). Tim Edwards 2021-11-06 21:19:42 -0400
  • f53590d4b5 Split the layout of the GPIO defaults block into three versions, for the three parameterized values used in the RTL verilog. Modified the "user_defines.v" file to create verilog definitions that match the C-style definitions from "defs.h", for convenience/simplicity. Tim Edwards 2021-11-06 13:28:26 -0400
  • 33140b67a5 Edited the gpio_defaults_block layout like the user_id_programming cell to have landing sites for vias on both the HI and LO pins of each conb_1 cell, in preparation for via programming. Tim Edwards 2021-11-06 12:59:49 -0400
  • 59076d499a Update gpio_defaults_block to align the pins with the gpio_control_block manarabdelaty 2021-11-05 23:27:32 +0200
  • 49c506f052 Update gpio_control_block after constrainting the clock period to be half the mgmt_core frequency manarabdelaty 2021-11-05 18:36:43 +0200
  • e68664101c Update gpio_control_block manarabdelaty 2021-11-05 16:54:24 +0200
  • 53b09f43d1 Add gpio_defaults_block views manarabdelaty 2021-11-05 12:33:36 +0200
  • 78ce7265c1 Update gpio_control block manarabdelaty 2021-11-04 17:58:58 +0200
  • cb9990f97e harden gpio_control_block manarabdelaty 2021-11-04 16:19:12 +0200
  • 8b055a380c Add top level makefile manarabdelaty 2021-11-04 16:16:39 +0200
  • b8dda9c3b1 (1) Corrected an error from a recent commit where the reset was fixed by moving from after the managment protect to before it, but an inversion of the signal was missed, leading to an incorrect wb_rst_i passed to housekeeping. (2) Revised the method to load the serial GPIO data chain from a 2-pin, I2C-like method to a more straightforward 3-pin method with separate reset, clock, and load pins. The load pin propagates through the chaing like the other two. Added a bit-bang signal for the load signal as well. (3) Added an implied buffer after the data output of the GPIO control block to ensure that the data arrives at the next control block after the clock, to prevent hold violations. Tim Edwards 2021-11-03 23:18:36 -0400
  • ba932643e6 Changed the chip_io and chip_io_alt layouts to implement the continuous ring of vccd and vssd. The clamp connections for the vccd1/vssd1 and vccd2/vssd2 pads still need to be done, although the pads themselves have been changed to the base cell, matching the new verilog RTL. Tim Edwards 2021-11-03 15:57:46 -0400
  • e09640425a Added the user-power-down version of hkspi (hkspi_power) to the list of patterns to run in the Makefile for verilog dv, since that pattern has been debugged and now runs correctly. Tim Edwards 2021-11-03 11:33:13 -0400
  • 3b89cf0efa Corrected the clock signal into the housekeeping module, which was incorrectly assigned to the clock on the user side of the managment protect block, causing it to be undefined when the user area power supply is down. The "hkspi_power" testbench which tests using the housekeeping SPI while the user area power is grounded now works correctly. Tim Edwards 2021-11-03 11:30:39 -0400
  • fe1fcbc3a5 Modified the padframe definition to keep the vccd domain continuous around the entire padframe. The vccd1 and vccd2 domains are local to their respective pads, and any bus routing must be done inside the padframe. This means that all pads operate on global vddio for 3.3V as before, but also global vccd for 1.8V. The user 1.8V voltage domain only goes as far as the input to the GPIO control block. Tim Edwards 2021-11-03 10:53:09 -0400
  • 1d359690ac Added testbench for checking that the housekeeping SPI is accessible when the user area is powered down. Because this requires some changes to the padframe definition, this testbench currently fails. Tim Edwards 2021-11-02 21:58:47 -0400
  • 9fb3925649 Updated the OSHW (open source hardware) icon graphic layout, which was badly digitized, and not taking advantage of the allowance of 45 degree angles on metal5. Tim Edwards 2021-11-01 17:25:34 -0400
  • dd66d1e5ca Renamed the poorly and awkwardly named "sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped" cell to the simpler (and easier to remember) "xres_buf". Tim Edwards 2021-10-31 21:43:09 -0400
  • a2aacdb5d2 Removed some commented-out test code from sram_exec.c to make the code clearer and less cluttered. Tim Edwards 2021-10-31 17:06:05 -0400
  • a360b77618 Added a testbench that demonstrates copying a portion of a program in flash into SRAM and executing it. Tim Edwards 2021-10-31 16:58:44 -0400
  • 11fe006532 Added documentation on the clocking and DLL blocks. Tim Edwards 2021-10-29 12:09:20 -0400
  • 1397ceb464 Added simple floorplan drawings for caravel. Tim Edwards 2021-10-28 22:49:59 -0400
  • 00e0a5f603 Corrected the two failing testbenches (which needed fixing because the implementation of the housekeeping module changed the addresses of the signals being exercised). Tim Edwards 2021-10-28 22:20:46 -0400
  • 787f1c3dae Added back wishbone verification tests, specifically those related to areas not part of the management SoC, including chip_io, mgmt_protect, and mprj_ctrl and sysctrl_wb (which are now part of housekeeping). The two housekeeping tests fail and need to be debugged. Tim Edwards 2021-10-28 17:26:06 -0400
  • 11165bfe3d Added entries in defs.h for the new input enable lines from the management SoC to the management protect block, and updated the documentation to include the new wishbone interface for those signals, and the additional signals on the management SoC pinout. Tim Edwards 2021-10-28 10:13:14 -0400
  • 3a57940371 Revised the management protect block to include protections against an unconnected wishbone bus (unconnected inputs). Added the missing signals for the user IRQ enables to management protect (which have to come from the management SoC). Tim Edwards 2021-10-27 19:36:43 -0400
  • a67cbcb01c Added back a couple more files related to the user ID programming block. Tim Edwards 2021-10-26 10:40:55 -0400
  • a7148378a0 Added as many of the magic database layout files as are expected to remain unchanged between the caravel and caravel_openframe repositories. Tim Edwards 2021-10-26 10:27:03 -0400
  • 1e7400c0ac Removed unused definitions from user_defines.v, and added more explanatory comments. Tim Edwards 2021-10-25 16:36:18 -0400
  • 745eee1baa Created an "open frame" version of caravan (and revised the one for caravel, since it had not been updated since a number of changes to the caravel top level module). Tim Edwards 2021-10-25 16:29:12 -0400
  • bc9944ce20 Updated the caravan netlist and implemented the caravan testbench. Tim Edwards 2021-10-25 15:08:13 -0400
  • a7fec91c4c Update to the back-door wishbone access to housekeeping to better implement the arbitration between SPI and back-door. The back-door access flags when it is going to do a read or write, and the SPI can have an invalid read or fail a write if the SPI is too fast, but the wishbone access should be valid. As long as the SPI is much slower than the core clock (say, 1MHz) then there should be no contention, which means that contention can always be avoided simply by slowing the SPI signaling down. Tim Edwards 2021-10-24 16:58:47 -0400
  • e6a94449ce Modified the housekeeping SPI to generate a read strobe (or rather status) so that between rdstb and wrstb, the SPI signals when it is about to read or write a byte. The back-door wishbone interface then stalls the CPU during these periods. That allows the CPU to continue running while the SPI is being accessed without data collisions and without having to stall for the entire time CSB is held low. Because SCK is asynchronous to the clock, rare collisions are still possible; this is not expected to be an issue but might be worth investigating. Tim Edwards 2021-10-23 22:06:24 -0400
  • e5c90daddd Implemented a system for setting the GPIO power-on defaults through via programming. The values for each of the GPIOs at power-up are defined in the "user_defines.v" file. For the verilog, they are applied as parameters. For the layout, they will need to be separately defined cells for each of the GPIOs, or at least for each set of unique default values. Tim Edwards 2021-10-23 17:18:30 -0400
  • a8ccbf2890 Added block diagrams for documentation. Tim Edwards 2021-10-22 12:01:08 -0400
  • 3ffe67e652 Changed the SRAM read-only port signal names to match the change made to the management SoC wrapper definition---this is just making the nomenclature better (no functional change). Tim Edwards 2021-10-22 11:51:07 -0400
  • a15593b217 Added a simple block diagram of the organization of the Caravel harness chip. Tim Edwards 2021-10-21 22:40:46 -0400
  • e474dbbc99 Corrected the last testbenches, added a new testbench for the spi_master since the original one was folded into the sysctrl testbench, but that testbench no longer uses the SPI master. Moved the SPI master from being an overlay of the housekeeping SPI to occupying GPIO pins 32 to 35. Made GPIO 35 a bidirectional pin like 36 and 37 so that the output enable from the SPI master can be used. Tim Edwards 2021-10-21 19:48:24 -0400
  • 43ced83bd8 Correction to the mprj_bitbang testbench to run the test without running into issues of contention between the SPI and wishbone interfaces. The testbench now passes, although the contention isn't handled particularly well. Tim Edwards 2021-10-21 10:57:20 -0400
  • d0f74db23b Updated pinout in documentation (doc/README file) Tim Edwards 2021-10-20 10:24:41 -0400
  • 000a5266ef Corrected an error in the bitbang testbench (but it does not cause the testbench to pass). Tim Edwards 2021-10-19 23:10:51 -0400
  • 184f4a637c Added the rest of the testbenches: mprj_bitbang, perf, pll, qspi, and storage. Not all of these pass simulation checks. Added back the bit-bang control of the GPIO programming. Added back the read-only interface between the housekeeping module and the SRAM 2nd port. Revised the memory map text document to reflect the addition of the SRAM ports. There is not yet a testbench for the SRAM read-only interface. Tim Edwards 2021-10-19 19:05:47 -0400
  • 767342e183 Added a completely revised sysctrl testbench based on accessing the housekeeping SPI through the back-door wishbone interface. Checks most of the SPI registers (but could do more). Tim Edwards 2021-10-19 17:32:20 -0400
  • e2f6a02688 Added and verified testbenches timer, timer2, uart, and user_pass_thru. Tim Edwards 2021-10-18 21:53:09 -0400