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caravel
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Merge branch 'main' of https://github.com/efabless/caravel_openframe into main

This commit is contained in:
manarabdelaty 2021-11-17 21:09:58 +02:00
parent 3cc88cd7fd 7b82c143b7
commit b71c8bbb36
3 changed files with 7 additions and 6 deletions
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3
verilog/rtl/caravel.v
View File

@ -487,7 +487,8 @@ module caravel (
.user_irq_ena(user_irq_ena),
.la_data_out_core(la_data_out_user),
.la_data_out_mprj(la_data_out_mprj),
.la_data_in_core(la_data_in_mprj),
.la_data_in_core(la_data_in_user),
.la_data_in_mprj(la_data_in_mprj),
.la_oenb_mprj(la_oenb_mprj),
.la_iena_mprj(la_iena_mprj),

2
verilog/rtl/chip_io.v
View File

@ -396,7 +396,7 @@ module chip_io(
.VSSA(vssa2),
.VSWITCH(vddio),
.VDDA(vdda2),
.VCCD(vccd2),
.VCCD(vccd),
.VCCHIB(vccd)
`else
.VCCHIB()

8
verilog/rtl/chip_io_alt.v
View File

@ -453,11 +453,11 @@ module chip_io_alt #(
.VSSIO_Q(vssio_q),
.AMUXBUS_A(analog_a),
.AMUXBUS_B(analog_b),
.VSSD(vssd1),
.VSSD(vssd),
.VSSA(vssa1),
.VSWITCH(vddio),
.VDDA(vdda1),
.VCCD(vccd1),
.VCCD(vccd),
.VCCHIB(vccd)
`else
.VCCHIB()
@ -471,11 +471,11 @@ module chip_io_alt #(
.VSSIO_Q(vssio_q),
.AMUXBUS_A(analog_a),
.AMUXBUS_B(analog_b),
.VSSD(vssd2),
.VSSD(vssd),
.VSSA(vssa2),
.VSWITCH(vddio),
.VDDA(vdda2),
.VCCD(vccd2),
.VCCD(vccd),
.VCCHIB(vccd)
`else
.VCCHIB()