From 96ef5c83fdfdaaf01b138e80b4005cecbcd374fd Mon Sep 17 00:00:00 2001
From: Tim Edwards <tim@opencircuitdesign.com>
Date: Wed, 17 Nov 2021 11:44:32 -0500
Subject: [PATCH 1/2] Corrected the corner pad connections to vssd and vccd,
 which were still pointing to vssd1/vccd1/vssd2/vccd2, variously in chip_io.v
 and chip_io_alt.v

---
 verilog/rtl/chip_io.v     | 2 +-
 verilog/rtl/chip_io_alt.v | 8 ++++----
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/verilog/rtl/chip_io.v b/verilog/rtl/chip_io.v
index bb3caccf..3659cad7 100644
--- a/verilog/rtl/chip_io.v
+++ b/verilog/rtl/chip_io.v
@@ -396,7 +396,7 @@ module chip_io(
 		.VSSA(vssa2),
 		.VSWITCH(vddio),
 		.VDDA(vdda2),
-		.VCCD(vccd2),
+		.VCCD(vccd),
 		.VCCHIB(vccd)
 `else
 		.VCCHIB()
diff --git a/verilog/rtl/chip_io_alt.v b/verilog/rtl/chip_io_alt.v
index 8c80dddd..a283544e 100644
--- a/verilog/rtl/chip_io_alt.v
+++ b/verilog/rtl/chip_io_alt.v
@@ -453,11 +453,11 @@ module chip_io_alt #(
 		.VSSIO_Q(vssio_q),
 		.AMUXBUS_A(analog_a),
 		.AMUXBUS_B(analog_b),
-		.VSSD(vssd1),
+		.VSSD(vssd),
 		.VSSA(vssa1),
 		.VSWITCH(vddio),
 		.VDDA(vdda1),
-		.VCCD(vccd1),
+		.VCCD(vccd),
 		.VCCHIB(vccd)
 `else
 		.VCCHIB()
@@ -471,11 +471,11 @@ module chip_io_alt #(
 		.VSSIO_Q(vssio_q),
 		.AMUXBUS_A(analog_a),
 		.AMUXBUS_B(analog_b),
-		.VSSD(vssd2),
+		.VSSD(vssd),
 		.VSSA(vssa2),
 		.VSWITCH(vddio),
 		.VDDA(vdda2),
-		.VCCD(vccd2),
+		.VCCD(vccd),
 		.VCCHIB(vccd)
 `else
 		.VCCHIB()

From 7b82c143b70e71b2eea9e973fa268256e463c16f Mon Sep 17 00:00:00 2001
From: Tim Edwards <tim@opencircuitdesign.com>
Date: Wed, 17 Nov 2021 14:08:47 -0500
Subject: [PATCH 2/2] Fixed two signals on the mgmt_protect in caravel that got
 merged and scrambled somehow.

---
 verilog/rtl/caravel.v | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index 124bcf3b..3d039a4a 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v
@@ -487,7 +487,8 @@ module caravel (
 	.user_irq_ena(user_irq_ena),
 	.la_data_out_core(la_data_out_user),
 	.la_data_out_mprj(la_data_out_mprj),
-	.la_data_in_core(la_data_in_mprj),
+	.la_data_in_core(la_data_in_user),
+	.la_data_in_mprj(la_data_in_mprj),
 	.la_oenb_mprj(la_oenb_mprj),
 	.la_iena_mprj(la_iena_mprj),