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Corrected the corner pad connections to vssd and vccd, which were 

still pointing to vssd1/vccd1/vssd2/vccd2, variously in chip_io.v
and chip_io_alt.v
This commit is contained in:
Tim Edwards 2021-11-17 11:44:32 -05:00
parent 979d34b7a9
commit 96ef5c83fd
2 changed files with 5 additions and 5 deletions
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2
verilog/rtl/chip_io.v
View File

@ -396,7 +396,7 @@ module chip_io(
.VSSA(vssa2),
.VSWITCH(vddio),
.VDDA(vdda2),
.VCCD(vccd2),
.VCCD(vccd),
.VCCHIB(vccd)
`else
.VCCHIB()

8
verilog/rtl/chip_io_alt.v
View File

@ -453,11 +453,11 @@ module chip_io_alt #(
.VSSIO_Q(vssio_q),
.AMUXBUS_A(analog_a),
.AMUXBUS_B(analog_b),
.VSSD(vssd1),
.VSSD(vssd),
.VSSA(vssa1),
.VSWITCH(vddio),
.VDDA(vdda1),
.VCCD(vccd1),
.VCCD(vccd),
.VCCHIB(vccd)
`else
.VCCHIB()
@ -471,11 +471,11 @@ module chip_io_alt #(
.VSSIO_Q(vssio_q),
.AMUXBUS_A(analog_a),
.AMUXBUS_B(analog_b),
.VSSD(vssd2),
.VSSD(vssd),
.VSSA(vssa2),
.VSWITCH(vddio),
.VDDA(vdda2),
.VCCD(vccd2),
.VCCD(vccd),
.VCCHIB(vccd)
`else
.VCCHIB()